diff options
Diffstat (limited to '')
63 files changed, 723 insertions, 651 deletions
diff --git a/test/arch/aarch64/arch.py b/test/arch/aarch64/arch.py index d2f5114e..70a44053 100644 --- a/test/arch/aarch64/arch.py +++ b/test/arch/aarch64/arch.py @@ -1,8 +1,10 @@ +from __future__ import print_function import sys import time from pdb import pm -from miasm2.arch.aarch64.arch import * -from miasm2.core.locationdb import LocationDB +from miasm.core.utils import decode_hex +from miasm.arch.aarch64.arch import * +from miasm.core.locationdb import LocationDB loc_db = LocationDB() @@ -1824,25 +1826,25 @@ reg_tests_aarch64 = [ def h2i(s): - return s.replace(' ', '').decode('hex') + return decode_hex(s.replace(' ', '')) ts = time.time() for s, l in reg_tests_aarch64[:]: - print "-" * 80 - print s[:12], l + print("-" * 80) + print(s[:12], l) s = s[12:] b = h2i((l)) mn = mn_aarch64.dis(b, 'l') - print [str(x) for x in mn.args] - print s - print mn + print([str(x) for x in mn.args]) + print(s) + print(mn) assert(str(mn) == s) l = mn_aarch64.fromstring(s, loc_db, 'l') assert(str(l) == s) a = mn_aarch64.asm(l) - print [x for x in a] - print repr(b) + print([x for x in a]) + print(repr(b)) assert(b in a) diff --git a/test/arch/aarch64/unit/asm_test.py b/test/arch/aarch64/unit/asm_test.py index 677d474f..fe59f0d8 100644 --- a/test/arch/aarch64/unit/asm_test.py +++ b/test/arch/aarch64/unit/asm_test.py @@ -1,13 +1,15 @@ import sys import os -from miasm2.arch.aarch64.arch import mn_aarch64, base_expr, variable -from miasm2.core import parse_asm -from miasm2.expression.expression import * -from miasm2.core import asmblock -from elfesteem.strpatchwork import StrPatchwork -from miasm2.analysis.machine import Machine -from miasm2.jitter.csts import * +from future.utils import viewitems + +from miasm.arch.aarch64.arch import mn_aarch64, base_expr, variable +from miasm.core import parse_asm +from miasm.expression.expression import * +from miasm.core import asmblock +from miasm.loader.strpatchwork import StrPatchwork +from miasm.analysis.machine import Machine +from miasm.jitter.csts import * reg_and_id = dict(mn_aarch64.regs.all_regs_ids_byname) @@ -28,10 +30,10 @@ class Asm_Test(object): loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) s = StrPatchwork() patches = asmblock.asm_resolve_final(mn_aarch64, blocks, loc_db) - for offset, raw in patches.items(): + for offset, raw in viewitems(patches): s[offset] = raw - self.assembly = str(s) + self.assembly = bytes(s) def run(self): run_addr = 0 diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index f86c3cfb..c8f2d433 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -1,13 +1,16 @@ +from __future__ import print_function import time -from miasm2.arch.arm.arch import * -from miasm2.core.locationdb import LocationDB + +from miasm.core.utils import decode_hex, encode_hex +from miasm.arch.arm.arch import * +from miasm.core.locationdb import LocationDB from pdb import pm loc_db = LocationDB() def h2i(s): - return s.replace(' ', '').decode('hex') + return decode_hex(s.replace(' ', '')) def u16swap(i): @@ -225,19 +228,19 @@ reg_tests_arm = [ ts = time.time() for s, l in reg_tests_arm: - print "-" * 80 + print("-" * 80) s = s[12:] b = h2i((l)) mn = mn_arm.dis(b, 'l') - print [str(x) for x in mn.args] - print s - print mn + print([str(x) for x in mn.args]) + print(s) + print(mn) assert(str(mn) == s) l = mn_arm.fromstring(s, loc_db, 'l') assert(str(l) == s) a = mn_arm.asm(l) - print [x for x in a] - print repr(b) + print([x for x in a]) + print(repr(b)) assert(b in a) reg_tests_armt = [ @@ -692,30 +695,30 @@ reg_tests_armt = [ ] -print "#" * 40, 'armthumb', '#' * 40 +print("#" * 40, 'armthumb', '#' * 40) for s, l in reg_tests_armt: - print "-" * 80 + print("-" * 80) s = s[12:] b = h2i((l)) - print b.encode('hex') + print(encode_hex(b)) mn = mn_armt.dis(b, 'l') - print [str(x) for x in mn.args] - print s - print mn + print([str(x) for x in mn.args]) + print(s) + print(mn) assert(str(mn) == s) l = mn_armt.fromstring(s, loc_db, 'l') assert(str(l) == s) - print 'Asm..', l + print('Asm..', l) a = mn_armt.asm(l) - print [x for x in a] - print repr(b) + print([x for x in a]) + print(repr(b)) assert(b in a) -print 'TEST time', time.time() - ts +print('TEST time', time.time() - ts) # speed test arm -o = "" +o = b"" for s, l in reg_tests_arm: s = s[12:] b = h2i((l)) @@ -731,11 +734,11 @@ while off < bs.getlen(): mn = mn_arm.dis(bs, 'l', off) instr_num += 1 off += 4 -print 'instr per sec:', instr_num / (time.time() - ts) +print('instr per sec:', instr_num // (time.time() - ts)) # speed test thumb -o = "" +o = b"" for s, l in reg_tests_armt: s = s[12:] b = h2i((l)) @@ -751,7 +754,7 @@ while off < bs.getlen(): mn = mn_armt.dis(bs, 'l', off) instr_num += 1 off += mn.l -print 'instr per sec:', instr_num / (time.time() - ts) +print('instr per sec:', instr_num // (time.time() - ts)) import cProfile cProfile.run(r'mn_arm.dis("\xe1\xa0\xa0\x06", "l")') diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py index d94b7ded..f38d48e9 100755 --- a/test/arch/arm/sem.py +++ b/test/arch/arm/sem.py @@ -1,15 +1,18 @@ #! /usr/bin/env python2 #-*- coding:utf-8 -*- +from __future__ import print_function import unittest import logging -from miasm2.ir.symbexec import SymbolicExecutionEngine -from miasm2.arch.arm.arch import mn_arm as mn -from miasm2.arch.arm.sem import ir_arml as ir_arch -from miasm2.arch.arm.regs import * -from miasm2.expression.expression import * -from miasm2.core.locationdb import LocationDB +from future.utils import viewitems + +from miasm.ir.symbexec import SymbolicExecutionEngine +from miasm.arch.arm.arch import mn_arm as mn +from miasm.arch.arm.sem import ir_arml as ir_arch +from miasm.arch.arm.regs import * +from miasm.expression.expression import * +from miasm.core.locationdb import LocationDB from pdb import pm logging.getLogger('cpuhelper').setLevel(logging.ERROR) @@ -23,7 +26,7 @@ def M(addr): def compute(asm, inputstate={}, debug=False): loc_db = LocationDB() sympool = dict(regs_init) - sympool.update({k: ExprInt(v, k.size) for k, v in inputstate.iteritems()}) + sympool.update({k: ExprInt(v, k.size) for k, v in viewitems(inputstate)}) ir_tmp = ir_arch(loc_db) ircfg = ir_tmp.new_ircfg() symexec = SymbolicExecutionEngine(ir_tmp, sympool) @@ -34,17 +37,17 @@ def compute(asm, inputstate={}, debug=False): lbl = ir_tmp.add_instr_to_ircfg(instr, ircfg) symexec.run_at(ircfg, lbl) if debug: - for k, v in symexec.symbols.items(): + for k, v in viewitems(symexec.symbols): if regs_init.get(k, None) != v: - print k, v + print(k, v) out = {} - for k, v in symexec.symbols.items(): + for k, v in viewitems(symexec.symbols): if k in EXCLUDE_REGS: continue elif regs_init.get(k, None) == v: continue elif isinstance(v, ExprInt): - out[k] = long(v) + out[k] = int(v) else: out[k] = v return out @@ -58,210 +61,210 @@ class TestARMSemantic(unittest.TestCase): def test_shift(self): # §A8.4: Shifts applied to a register self.assertEqual( - compute('MOV R4, R4 ', {R4: 0xDEADBEEFL, }), {R4: 0xDEADBEEFL, }) + compute('MOV R4, R4 ', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 LSL 0') self.assertEqual( - compute('MOV R4, R4 LSL 1', {R4: 0xDEADBEEFL, }), {R4: 0xBD5B7DDEL, }) + compute('MOV R4, R4 LSL 1', {R4: 0xDEADBEEF, }), {R4: 0xBD5B7DDE, }) self.assertEqual( - compute('MOV R4, R4 LSL 16', {R4: 0xDEADBEEFL, }), {R4: 0xBEEF0000L, }) + compute('MOV R4, R4 LSL 16', {R4: 0xDEADBEEF, }), {R4: 0xBEEF0000, }) self.assertEqual( - compute('MOV R4, R4 LSL 31', {R4: 0xDEADBEEFL, }), {R4: 0x80000000L, }) + compute('MOV R4, R4 LSL 31', {R4: 0xDEADBEEF, }), {R4: 0x80000000, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 LSL 32') self.assertEqual( - compute('MOV R4, R4 LSL R5', {R4: 0xDEADBEEFL, R5: 0xBADBAD01L, }), {R4: 0xBD5B7DDEL, R5: 0xBADBAD01L, }) + compute('MOV R4, R4 LSL R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xBD5B7DDE, R5: 0xBADBAD01, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 LSR 0') self.assertEqual( - compute('MOV R4, R4 LSR 1', {R4: 0xDEADBEEFL, }), {R4: 0x6F56DF77L, }) + compute('MOV R4, R4 LSR 1', {R4: 0xDEADBEEF, }), {R4: 0x6F56DF77, }) self.assertEqual( - compute('MOV R4, R4 LSR 16', {R4: 0xDEADBEEFL, }), {R4: 0x0000DEADL, }) + compute('MOV R4, R4 LSR 16', {R4: 0xDEADBEEF, }), {R4: 0x0000DEAD, }) self.assertEqual( - compute('MOV R4, R4 LSR 31', {R4: 0xDEADBEEFL, }), {R4: 0x00000001L, }) + compute('MOV R4, R4 LSR 31', {R4: 0xDEADBEEF, }), {R4: 0x00000001, }) self.assertEqual( - compute('MOV R4, R4 LSR 32', {R4: 0xDEADBEEFL, }), {R4: 0xDEADBEEFL, }) + compute('MOV R4, R4 LSR 32', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 LSR 33') self.assertEqual( - compute('MOV R4, R4 LSR R5', {R4: 0xDEADBEEFL, R5: 0xBADBAD01L, }), {R4: 0x6F56DF77L, R5: 0xBADBAD01L, }) + compute('MOV R4, R4 LSR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0x6F56DF77, R5: 0xBADBAD01, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 ASR 0') self.assertEqual( - compute('MOV R4, R4 ASR 1', {R4: 0xDEADBEEFL, }), {R4: 0xEF56DF77L, }) + compute('MOV R4, R4 ASR 1', {R4: 0xDEADBEEF, }), {R4: 0xEF56DF77, }) self.assertEqual( - compute('MOV R4, R4 ASR 16', {R4: 0xDEADBEEFL, }), {R4: 0xFFFFDEADL, }) + compute('MOV R4, R4 ASR 16', {R4: 0xDEADBEEF, }), {R4: 0xFFFFDEAD, }) self.assertEqual( - compute('MOV R4, R4 ASR 31', {R4: 0xDEADBEEFL, }), {R4: 0xFFFFFFFFL, }) + compute('MOV R4, R4 ASR 31', {R4: 0xDEADBEEF, }), {R4: 0xFFFFFFFF, }) self.assertEqual( - compute('MOV R4, R4 ASR 32', {R4: 0xDEADBEEFL, }), {R4: 0xDEADBEEFL, }) + compute('MOV R4, R4 ASR 32', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 ASR 33') self.assertEqual( - compute('MOV R4, R4 ASR R5', {R4: 0xDEADBEEFL, R5: 0xBADBAD01L, }), {R4: 0xEF56DF77L, R5: 0xBADBAD01L, }) + compute('MOV R4, R4 ASR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xEF56DF77, R5: 0xBADBAD01, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 ROR 0') self.assertEqual( - compute('MOV R4, R4 ROR 1', {R4: 0xDEADBEEFL, }), {R4: 0xEF56DF77L, }) + compute('MOV R4, R4 ROR 1', {R4: 0xDEADBEEF, }), {R4: 0xEF56DF77, }) self.assertEqual( - compute('MOV R4, R4 ROR 16', {R4: 0xDEADBEEFL, }), {R4: 0xBEEFDEADL, }) + compute('MOV R4, R4 ROR 16', {R4: 0xDEADBEEF, }), {R4: 0xBEEFDEAD, }) self.assertEqual( - compute('MOV R4, R4 ROR 31', {R4: 0xDEADBEEFL, }), {R4: 0xBD5B7DDFL, }) + compute('MOV R4, R4 ROR 31', {R4: 0xDEADBEEF, }), {R4: 0xBD5B7DDF, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 ROR 32') self.assertEqual( - compute('MOV R4, R4 ROR R5', {R4: 0xDEADBEEFL, R5: 0xBADBAD01L, }), {R4: 0xEF56DF77L, R5: 0xBADBAD01L, }) - self.assertEqual(compute('MOV R4, R4 RRX ', {cf: 0L, R4: 0xDEADBEEFL, }), { - cf: 0L, R4: 0x6F56DF77L, }) - self.assertEqual(compute('MOV R4, R4 RRX ', {cf: 1L, R4: 0xDEADBEEFL, }), { - cf: 1L, R4: 0xEF56DF77L, }) + compute('MOV R4, R4 ROR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xEF56DF77, R5: 0xBADBAD01, }) + self.assertEqual(compute('MOV R4, R4 RRX ', {cf: 0, R4: 0xDEADBEEF, }), { + cf: 0, R4: 0x6F56DF77, }) + self.assertEqual(compute('MOV R4, R4 RRX ', {cf: 1, R4: 0xDEADBEEF, }), { + cf: 1, R4: 0xEF56DF77, }) def test_ADC(self): # §A8.8.1: ADC{S}{<c>}{<q>} {<Rd>,} <Rn>, #<const> self.assertRaises( ValueError, compute, 'ADC R4, 0x00000001 ') self.assertEqual(compute('ADC R4, R4, 0x00000001 ', { - cf: 0L, R4: 0x00000000L, }), {cf: 0L, R4: 0x00000001L, }) + cf: 0, R4: 0x00000000, }), {cf: 0, R4: 0x00000001, }) self.assertEqual(compute('ADC R4, R4, 0x00000000 ', { - cf: 1L, R4: 0x00000000L, }), {cf: 1L, R4: 0x00000001L, }) + cf: 1, R4: 0x00000000, }), {cf: 1, R4: 0x00000001, }) self.assertEqual(compute('ADC PC, R4, 0x00000001 ', { - cf: 0L, R4: 0xFFFFFFFFL, PC: 0x55555555L, }), {cf: 0L, R4: 0xFFFFFFFFL, PC: 0x00000000L, }) + cf: 0, R4: 0xFFFFFFFF, PC: 0x55555555, }), {cf: 0, R4: 0xFFFFFFFF, PC: 0x00000000, }) self.assertEqual(compute('ADC PC, R4, 0x00000000 ', { - cf: 1L, R4: 0xFFFFFFFFL, PC: 0x55555555L, }), {cf: 1L, R4: 0xFFFFFFFFL, PC: 0x00000000L, }) - self.assertEqual(compute('ADCS R4, R4, 0x80000000 ', {cf: 0L, R4: 0x80000000L, }), { - nf: 0L, zf: 1L, cf: 1L, of: 1L, R4: 0x00000000L, }) - self.assertEqual(compute('ADCS R4, R4, 0xFF000000 ', {cf: 1L, R4: 0x00FFFFFEL, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xFFFFFFFFL, }) + cf: 1, R4: 0xFFFFFFFF, PC: 0x55555555, }), {cf: 1, R4: 0xFFFFFFFF, PC: 0x00000000, }) + self.assertEqual(compute('ADCS R4, R4, 0x80000000 ', {cf: 0, R4: 0x80000000, }), { + nf: 0, zf: 1, cf: 1, of: 1, R4: 0x00000000, }) + self.assertEqual(compute('ADCS R4, R4, 0xFF000000 ', {cf: 1, R4: 0x00FFFFFE, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xFFFFFFFF, }) self.assertEqual(compute('ADCS PC, R4, 0x00000000 ', { - cf: 0L, R4: 0x00000000L, PC: 0x55555555L, }), {cf: 0L, R4: 0x00000000L, PC: 0x00000000L, }) + cf: 0, R4: 0x00000000, PC: 0x55555555, }), {cf: 0, R4: 0x00000000, PC: 0x00000000, }) self.assertEqual(compute('ADCS PC, R4, 0xFF000000 ', { - cf: 1L, R4: 0x01000000L, PC: 0x55555555L, }), {cf: 1L, R4: 0x01000000L, PC: 0x00000001L, }) + cf: 1, R4: 0x01000000, PC: 0x55555555, }), {cf: 1, R4: 0x01000000, PC: 0x00000001, }) # §A8.8.2: ADC{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {,<shift>} self.assertRaises( ValueError, compute, 'ADC R4, R5 ') self.assertEqual(compute('ADC R4, R4, R5 ', { - cf: 1L, R4: 0xFFFFFFFFL, R5: 0x00000000L, }), {cf: 1L, R4: 0x00000000L, R5: 0x00000000L, }) + cf: 1, R4: 0xFFFFFFFF, R5: 0x00000000, }), {cf: 1, R4: 0x00000000, R5: 0x00000000, }) self.assertEqual(compute('ADC R4, R4, R5 LSL 1 ', { - cf: 0L, R4: 0x00000001L, R5: 0x00000008L, }), {cf: 0L, R4: 0x00000011L, R5: 0x00000008L, }) + cf: 0, R4: 0x00000001, R5: 0x00000008, }), {cf: 0, R4: 0x00000011, R5: 0x00000008, }) self.assertEqual(compute('ADC R4, R4, R5 LSR 2 ', { - cf: 1L, R4: 0x00000000L, R5: 0x80000041L, }), {cf: 1L, R4: 0x20000011L, R5: 0x80000041L, }) + cf: 1, R4: 0x00000000, R5: 0x80000041, }), {cf: 1, R4: 0x20000011, R5: 0x80000041, }) self.assertEqual(compute('ADC R4, R4, R5 ASR 3 ', { - cf: 0L, R4: 0x00000001L, R5: 0x80000081L, }), {cf: 0L, R4: 0xF0000011L, R5: 0x80000081L, }) + cf: 0, R4: 0x00000001, R5: 0x80000081, }), {cf: 0, R4: 0xF0000011, R5: 0x80000081, }) self.assertEqual(compute('ADC R4, R4, R5 ROR 4 ', { - cf: 1L, R4: 0xFFFFFFFFL, R5: 0x0000010FL, }), {cf: 1L, R4: 0xF0000010L, R5: 0x0000010FL, }) + cf: 1, R4: 0xFFFFFFFF, R5: 0x0000010F, }), {cf: 1, R4: 0xF0000010, R5: 0x0000010F, }) self.assertEqual(compute('ADC R4, R4, R5 RRX ', { - cf: 1L, R4: 0xFFFFFFFFL, R5: 0x00000101L, }), {cf: 1L, R4: 0x80000080L, R5: 0x00000101L, }) - self.assertEqual(compute('ADCS R4, R4, R5 ', {cf: 1L, R4: 0xFFFFFFFFL, R5: 0x00000000L, }), { - nf: 0L, zf: 1L, cf: 1L, of: 0L, R4: 0x00000000L, R5: 0x00000000L, }) - self.assertEqual(compute('ADCS R4, R4, R5 LSL 1 ', {cf: 0L, R4: 0x00000001L, R5: 0x00000008L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x00000011L, R5: 0x00000008L, }) - self.assertEqual(compute('ADCS R4, R4, R5 LSR 2 ', {cf: 1L, R4: 0x00000000L, R5: 0x80000041L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x20000011L, R5: 0x80000041L, }) - self.assertEqual(compute('ADCS R4, R4, R5 ASR 3 ', {cf: 0L, R4: 0x00000001L, R5: 0x80000081L, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xF0000011L, R5: 0x80000081L, }) - self.assertEqual(compute('ADCS R4, R4, R5 ROR 4 ', {cf: 1L, R4: 0xFFFFFFFFL, R5: 0x0000010FL, }), { - nf: 1L, zf: 0L, cf: 1L, of: 0L, R4: 0xF0000010L, R5: 0x0000010FL, }) - self.assertEqual(compute('ADCS R4, R4, R5 RRX ', {cf: 1L, R4: 0xFFFFFFFFL, R5: 0x00000101L, }), { - nf: 1L, zf: 0L, cf: 1L, of: 0L, R4: 0x80000080L, R5: 0x00000101L, }) + cf: 1, R4: 0xFFFFFFFF, R5: 0x00000101, }), {cf: 1, R4: 0x80000080, R5: 0x00000101, }) + self.assertEqual(compute('ADCS R4, R4, R5 ', {cf: 1, R4: 0xFFFFFFFF, R5: 0x00000000, }), { + nf: 0, zf: 1, cf: 1, of: 0, R4: 0x00000000, R5: 0x00000000, }) + self.assertEqual(compute('ADCS R4, R4, R5 LSL 1 ', {cf: 0, R4: 0x00000001, R5: 0x00000008, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x00000011, R5: 0x00000008, }) + self.assertEqual(compute('ADCS R4, R4, R5 LSR 2 ', {cf: 1, R4: 0x00000000, R5: 0x80000041, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x20000011, R5: 0x80000041, }) + self.assertEqual(compute('ADCS R4, R4, R5 ASR 3 ', {cf: 0, R4: 0x00000001, R5: 0x80000081, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xF0000011, R5: 0x80000081, }) + self.assertEqual(compute('ADCS R4, R4, R5 ROR 4 ', {cf: 1, R4: 0xFFFFFFFF, R5: 0x0000010F, }), { + nf: 1, zf: 0, cf: 1, of: 0, R4: 0xF0000010, R5: 0x0000010F, }) + self.assertEqual(compute('ADCS R4, R4, R5 RRX ', {cf: 1, R4: 0xFFFFFFFF, R5: 0x00000101, }), { + nf: 1, zf: 0, cf: 1, of: 0, R4: 0x80000080, R5: 0x00000101, }) # §A8.8.3: ADC{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <type> <Rs> self.assertEqual(compute('ADC R4, R6, R4 LSL R5', { - cf: 0L, R4: 0x00000001L, R5: 0x00000004L, R6: 0L, }), {cf: 0L, R4: 0x00000010L, R5: 0x00000004L, R6: 0L, }) + cf: 0, R4: 0x00000001, R5: 0x00000004, R6: 0, }), {cf: 0, R4: 0x00000010, R5: 0x00000004, R6: 0, }) self.assertEqual(compute('ADC R4, R6, R4 LSR R5', { - cf: 1L, R4: 0x00000110L, R5: 0x80000004L, R6: 0L, }), {cf: 1L, R4: 0x00000012L, R5: 0x80000004L, R6: 0L, }) + cf: 1, R4: 0x00000110, R5: 0x80000004, R6: 0, }), {cf: 1, R4: 0x00000012, R5: 0x80000004, R6: 0, }) self.assertEqual(compute('ADC R4, R6, R4 ASR R5', { - cf: 0L, R4: 0x80000010L, R5: 0xF0000001L, R6: 0L, }), {cf: 0L, R4: 0xC0000008L, R5: 0xF0000001L, R6: 0L, }) + cf: 0, R4: 0x80000010, R5: 0xF0000001, R6: 0, }), {cf: 0, R4: 0xC0000008, R5: 0xF0000001, R6: 0, }) self.assertEqual(compute('ADC R4, R6, R4 ROR R5', { - cf: 1L, R4: 0x000000FFL, R5: 0x00000F04L, R6: 0L, }), {cf: 1L, R4: 0xF0000010L, R5: 0x00000F04L, R6: 0L, }) - self.assertEqual(compute('ADCS R4, R6, R4 LSL R5', {cf: 0L, R4: 0x00000001L, R5: 0x00000004L, R6: 0L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x00000010L, R5: 0x00000004L, R6: 0L, }) - self.assertEqual(compute('ADCS R4, R6, R4 LSR R5', {cf: 1L, R4: 0x00000110L, R5: 0x80000004L, R6: 0L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x00000012L, R5: 0x80000004L, R6: 0L, }) - self.assertEqual(compute('ADCS R4, R6, R4 ASR R5', {cf: 0L, R4: 0x80000010L, R5: 0xF0000001L, R6: 0L, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xC0000008L, R5: 0xF0000001L, R6: 0L, }) - self.assertEqual(compute('ADCS R4, R6, R4 ROR R5', {cf: 1L, R4: 0x000000FFL, R5: 0x00000F04L, R6: 0L, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xF0000010L, R5: 0x00000F04L, R6: 0L, }) + cf: 1, R4: 0x000000FF, R5: 0x00000F04, R6: 0, }), {cf: 1, R4: 0xF0000010, R5: 0x00000F04, R6: 0, }) + self.assertEqual(compute('ADCS R4, R6, R4 LSL R5', {cf: 0, R4: 0x00000001, R5: 0x00000004, R6: 0, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x00000010, R5: 0x00000004, R6: 0, }) + self.assertEqual(compute('ADCS R4, R6, R4 LSR R5', {cf: 1, R4: 0x00000110, R5: 0x80000004, R6: 0, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x00000012, R5: 0x80000004, R6: 0, }) + self.assertEqual(compute('ADCS R4, R6, R4 ASR R5', {cf: 0, R4: 0x80000010, R5: 0xF0000001, R6: 0, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xC0000008, R5: 0xF0000001, R6: 0, }) + self.assertEqual(compute('ADCS R4, R6, R4 ROR R5', {cf: 1, R4: 0x000000FF, R5: 0x00000F04, R6: 0, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xF0000010, R5: 0x00000F04, R6: 0, }) def test_ADD(self): # §A8.8.{5,9}: ADD{S}{<c>}{<q>} {<Rd>,} <Rn>, #<const> self.assertRaises( ValueError, compute, 'ADD R4, 0x00000001L ') self.assertEqual(compute('ADD R4, R4, 0x00000001 ', { - R4: 0x00000000L, }), {R4: 0x00000001L, }) + R4: 0x00000000, }), {R4: 0x00000001, }) self.assertEqual(compute('ADD R4, R4, 0x00000000 ', { - R4: 0x00000000L, }), {R4: 0x00000000L, }) + R4: 0x00000000, }), {R4: 0x00000000, }) self.assertEqual(compute('ADD PC, R4, 0x00000001 ', { - R4: 0xFFFFFFFFL, PC: 0x55555555L, }), {R4: 0xFFFFFFFFL, PC: 0x00000000L, }) + R4: 0xFFFFFFFF, PC: 0x55555555, }), {R4: 0xFFFFFFFF, PC: 0x00000000, }) self.assertEqual(compute('ADD PC, R4, 0x00000000 ', { - R4: 0xFFFFFFFFL, PC: 0x55555555L, }), {R4: 0xFFFFFFFFL, PC: 0xFFFFFFFFL, }) - self.assertEqual(compute('ADDS R4, R4, 0x80000000 ', {R4: 0x80000000L, }), { - nf: 0L, zf: 1L, cf: 1L, of: 1L, R4: 0x00000000L, }) - self.assertEqual(compute('ADDS R4, R4, 0xFF000000 ', {R4: 0x00FFFFFEL, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xFFFFFFFEL, }) + R4: 0xFFFFFFFF, PC: 0x55555555, }), {R4: 0xFFFFFFFF, PC: 0xFFFFFFFF, }) + self.assertEqual(compute('ADDS R4, R4, 0x80000000 ', {R4: 0x80000000, }), { + nf: 0, zf: 1, cf: 1, of: 1, R4: 0x00000000, }) + self.assertEqual(compute('ADDS R4, R4, 0xFF000000 ', {R4: 0x00FFFFFE, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xFFFFFFFE, }) self.assertEqual(compute('ADDS PC, R4, 0x00000000 ', { - R4: 0x00000000L, PC: 0x55555555L, }), {R4: 0x00000000L, PC: 0x00000000L, }) + R4: 0x00000000, PC: 0x55555555, }), {R4: 0x00000000, PC: 0x00000000, }) self.assertEqual(compute('ADDS PC, R4, 0xFF000000 ', { - R4: 0x01000000L, PC: 0x55555555L, }), {R4: 0x01000000L, PC: 0x00000000L, }) + R4: 0x01000000, PC: 0x55555555, }), {R4: 0x01000000, PC: 0x00000000, }) # SP special part self.assertEqual(compute('ADD R4, SP, 0x00000001 ', { - R4: 0x00000000L, SP: 0x00000000L, }), {R4: 0x00000001L, SP: 0x00000000L, }) + R4: 0x00000000, SP: 0x00000000, }), {R4: 0x00000001, SP: 0x00000000, }) # §A8.8.{7,11}: ADD{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {,<shift>} self.assertRaises( ValueError, compute, 'ADD R4, R5 ') self.assertEqual(compute('ADD R4, R4, R5 ', { - R4: 0xFFFFFFFFL, R5: 0x00000001L, }), {R4: 0x00000000L, R5: 0x00000001L, }) + R4: 0xFFFFFFFF, R5: 0x00000001, }), {R4: 0x00000000, R5: 0x00000001, }) self.assertEqual(compute('ADD R4, R4, R5 LSL 1 ', { - R4: 0x00000001L, R5: 0x00000008L, }), {R4: 0x00000011L, R5: 0x00000008L, }) + R4: 0x00000001, R5: 0x00000008, }), {R4: 0x00000011, R5: 0x00000008, }) self.assertEqual(compute('ADD R4, R4, R5 LSR 2 ', { - R4: 0x00000000L, R5: 0x80000041L, }), {R4: 0x20000010L, R5: 0x80000041L, }) + R4: 0x00000000, R5: 0x80000041, }), {R4: 0x20000010, R5: 0x80000041, }) self.assertEqual(compute('ADD R4, R4, R5 ASR 3 ', { - R4: 0x00000001L, R5: 0x80000081L, }), {R4: 0xF0000011L, R5: 0x80000081L, }) + R4: 0x00000001, R5: 0x80000081, }), {R4: 0xF0000011, R5: 0x80000081, }) self.assertEqual(compute('ADD R4, R4, R5 ROR 4 ', { - R4: 0xFFFFFFFFL, R5: 0x0000010FL, }), {R4: 0xF000000FL, R5: 0x0000010FL, }) + R4: 0xFFFFFFFF, R5: 0x0000010F, }), {R4: 0xF000000F, R5: 0x0000010F, }) self.assertEqual(compute('ADD R4, R4, R5 RRX ', { - cf: 1L, R4: 0xFFFFFFFFL, R5: 0x00000101L, }), {cf: 1L, R4: 0x8000007FL, R5: 0x00000101L, }) - self.assertEqual(compute('ADDS R4, R4, R5 ', {R4: 0xFFFFFFFFL, R5: 0x00000001L, }), { - nf: 0L, zf: 1L, cf: 1L, of: 0L, R4: 0x00000000L, R5: 0x00000001L, }) - self.assertEqual(compute('ADDS R4, R4, R5 LSL 1 ', {R4: 0x00000001L, R5: 0x00000008L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x00000011L, R5: 0x00000008L, }) - self.assertEqual(compute('ADDS R4, R4, R5 LSR 2 ', {R4: 0x00000000L, R5: 0x80000041L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x20000010L, R5: 0x80000041L, }) - self.assertEqual(compute('ADDS R4, R4, R5 ASR 3 ', {R4: 0x00000001L, R5: 0x80000081L, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xF0000011L, R5: 0x80000081L, }) - self.assertEqual(compute('ADDS R4, R4, R5 ROR 4 ', {R4: 0xFFFFFFFFL, R5: 0x0000010FL, }), { - nf: 1L, zf: 0L, cf: 1L, of: 0L, R4: 0xF000000FL, R5: 0x0000010FL, }) - self.assertEqual(compute('ADDS R4, R4, R5 RRX ', {cf: 1L, R4: 0xFFFFFFFFL, R5: 0x00000101L, }), { - nf: 1L, zf: 0L, cf: 1L, of: 0L, R4: 0x8000007FL, R5: 0x00000101L, }) + cf: 1, R4: 0xFFFFFFFF, R5: 0x00000101, }), {cf: 1, R4: 0x8000007F, R5: 0x00000101, }) + self.assertEqual(compute('ADDS R4, R4, R5 ', {R4: 0xFFFFFFFF, R5: 0x00000001, }), { + nf: 0, zf: 1, cf: 1, of: 0, R4: 0x00000000, R5: 0x00000001, }) + self.assertEqual(compute('ADDS R4, R4, R5 LSL 1 ', {R4: 0x00000001, R5: 0x00000008, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x00000011, R5: 0x00000008, }) + self.assertEqual(compute('ADDS R4, R4, R5 LSR 2 ', {R4: 0x00000000, R5: 0x80000041, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x20000010, R5: 0x80000041, }) + self.assertEqual(compute('ADDS R4, R4, R5 ASR 3 ', {R4: 0x00000001, R5: 0x80000081, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xF0000011, R5: 0x80000081, }) + self.assertEqual(compute('ADDS R4, R4, R5 ROR 4 ', {R4: 0xFFFFFFFF, R5: 0x0000010F, }), { + nf: 1, zf: 0, cf: 1, of: 0, R4: 0xF000000F, R5: 0x0000010F, }) + self.assertEqual(compute('ADDS R4, R4, R5 RRX ', {cf: 1, R4: 0xFFFFFFFF, R5: 0x00000101, }), { + nf: 1, zf: 0, cf: 1, of: 0, R4: 0x8000007F, R5: 0x00000101, }) # SP special part self.assertEqual(compute('ADD R4, SP, R4 LSR 1 ', { - R4: 0x00000002L, SP: 0x00000000L, }), {R4: 0x00000001L, SP: 0x00000000L, }) + R4: 0x00000002, SP: 0x00000000, }), {R4: 0x00000001, SP: 0x00000000, }) # §A8.8.8: ADD{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <type> <Rs> self.assertEqual(compute('ADD R4, R6, R4 LSL R5', { - R4: 0x00000001L, R5: 0x00000004L, R6: 0L, }), {R4: 0x00000010L, R5: 0x00000004L, R6: 0L, }) + R4: 0x00000001, R5: 0x00000004, R6: 0, }), {R4: 0x00000010, R5: 0x00000004, R6: 0, }) self.assertEqual(compute('ADD R4, R6, R4 LSR R5', { - R4: 0x00000110L, R5: 0x80000004L, R6: 0L, }), {R4: 0x00000011L, R5: 0x80000004L, R6: 0L, }) + R4: 0x00000110, R5: 0x80000004, R6: 0, }), {R4: 0x00000011, R5: 0x80000004, R6: 0, }) self.assertEqual(compute('ADD R4, R6, R4 ASR R5', { - R4: 0x80000010L, R5: 0xF0000001L, R6: 0L, }), {R4: 0xC0000008L, R5: 0xF0000001L, R6: 0L, }) + R4: 0x80000010, R5: 0xF0000001, R6: 0, }), {R4: 0xC0000008, R5: 0xF0000001, R6: 0, }) self.assertEqual(compute('ADD R4, R6, R4 ROR R5', { - R4: 0x000000FFL, R5: 0x00000F04L, R6: 0L, }), {R4: 0xF000000FL, R5: 0x00000F04L, R6: 0L, }) - self.assertEqual(compute('ADDS R4, R6, R4 LSL R5', {R4: 0x00000001L, R5: 0x00000004L, R6: 0L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x00000010L, R5: 0x00000004L, R6: 0L, }) - self.assertEqual(compute('ADDS R4, R6, R4 LSR R5', {R4: 0x00000110L, R5: 0x80000004L, R6: 0L, }), { - nf: 0L, zf: 0L, cf: 0L, of: 0L, R4: 0x00000011L, R5: 0x80000004L, R6: 0L, }) - self.assertEqual(compute('ADDS R4, R6, R4 ASR R5', {R4: 0x80000010L, R5: 0xF0000001L, R6: 0L, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xC0000008L, R5: 0xF0000001L, R6: 0L, }) - self.assertEqual(compute('ADDS R4, R6, R4 ROR R5', {R4: 0x000000FFL, R5: 0x00000F04L, R6: 0L, }), { - nf: 1L, zf: 0L, cf: 0L, of: 0L, R4: 0xF000000FL, R5: 0x00000F04L, R6: 0L, }) + R4: 0x000000FF, R5: 0x00000F04, R6: 0, }), {R4: 0xF000000F, R5: 0x00000F04, R6: 0, }) + self.assertEqual(compute('ADDS R4, R6, R4 LSL R5', {R4: 0x00000001, R5: 0x00000004, R6: 0, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x00000010, R5: 0x00000004, R6: 0, }) + self.assertEqual(compute('ADDS R4, R6, R4 LSR R5', {R4: 0x00000110, R5: 0x80000004, R6: 0, }), { + nf: 0, zf: 0, cf: 0, of: 0, R4: 0x00000011, R5: 0x80000004, R6: 0, }) + self.assertEqual(compute('ADDS R4, R6, R4 ASR R5', {R4: 0x80000010, R5: 0xF0000001, R6: 0, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xC0000008, R5: 0xF0000001, R6: 0, }) + self.assertEqual(compute('ADDS R4, R6, R4 ROR R5', {R4: 0x000000FF, R5: 0x00000F04, R6: 0, }), { + nf: 1, zf: 0, cf: 0, of: 0, R4: 0xF000000F, R5: 0x00000F04, R6: 0, }) # Test against qemu - self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x1L, R3: 0x1L}), - { nf: 0L, zf: 0L, cf: 0L, of: 0L, R2: 0x00000001L, R3: 0x00000002L}) - self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x1L, R3: 0x7FFFFFFFL}), - { nf: 1L, zf: 0L, cf: 0L, of: 1L, R2: 0x00000001L, R3: 0x80000000L}) - self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x80000000L, R3: 0x80000000L}), - { nf: 0L, zf: 1L, cf: 1L, of: 1L, R2: 0x80000000L, R3: 0x00000000L}) - self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x7FFFFFFFL, R3:0x7FFFFFFFL}), - { nf: 1L, zf: 0L, cf: 0L, of: 1L, R2: 0x7FFFFFFFL, R3:0xFFFFFFFEL}) - self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0L, R3:0}), - { nf: 0L, zf: 1L, cf: 0L, of: 0L, R2: 0L, R3:0}) - self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0xFFFFFFFFL, R3:0xFFFFFFFFL}), - { nf: 1L, zf: 0L, cf: 1L, of: 0L, R2: 0xFFFFFFFFL, R3:0xFFFFFFFEL}) + self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x1, R3: 0x1}), + { nf: 0, zf: 0, cf: 0, of: 0, R2: 0x00000001, R3: 0x00000002}) + self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x1, R3: 0x7FFFFFFF}), + { nf: 1, zf: 0, cf: 0, of: 1, R2: 0x00000001, R3: 0x80000000}) + self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x80000000, R3: 0x80000000}), + { nf: 0, zf: 1, cf: 1, of: 1, R2: 0x80000000, R3: 0x00000000}) + self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0x7FFFFFFF, R3:0x7FFFFFFF}), + { nf: 1, zf: 0, cf: 0, of: 1, R2: 0x7FFFFFFF, R3:0xFFFFFFFE}) + self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0, R3:0}), + { nf: 0, zf: 1, cf: 0, of: 0, R2: 0, R3:0}) + self.assertEqual(compute('ADDS R3, R2, R3 ', {R2: 0xFFFFFFFF, R3:0xFFFFFFFF}), + { nf: 1, zf: 0, cf: 1, of: 0, R2: 0xFFFFFFFF, R3:0xFFFFFFFE}) @@ -275,26 +278,26 @@ class TestARMSemantic(unittest.TestCase): # §A8.8.13: AND{S}{<c>}{<q>} {<Rd>,} <Rn>, #<const> self.assertRaises( ValueError, compute, 'AND R4, 0x00000001 ') - self.assertEqual(compute('AND R4, R4, 0x00000001 ', {R4: 0xDEADBEEFL, }), {R4: 0x00000001L, }) - self.assertEqual(compute('AND R4, R4, 0x00000000 ', {R4: 0x00000000L, }), {R4: 0x00000000L, }) - self.assertEqual(compute('AND PC, R4, 0x00000001 ', {R4: 0xFFFFFFFFL, PC: 0x55555555L, }), {R4: 0xFFFFFFFFL, PC: 0x00000001L, }) - self.assertEqual(compute('AND PC, R4, 0x00000000 ', {R4: 0xFFFFFFFFL, PC: 0x55555555L, }), {R4: 0xFFFFFFFFL, PC: 0x00000000L, }) + self.assertEqual(compute('AND R4, R4, 0x00000001 ', {R4: 0xDEADBEEF, }), {R4: 0x00000001, }) + self.assertEqual(compute('AND R4, R4, 0x00000000 ', {R4: 0x00000000, }), {R4: 0x00000000, }) + self.assertEqual(compute('AND PC, R4, 0x00000001 ', {R4: 0xFFFFFFFF, PC: 0x55555555, }), {R4: 0xFFFFFFFF, PC: 0x00000001, }) + self.assertEqual(compute('AND PC, R4, 0x00000000 ', {R4: 0xFFFFFFFF, PC: 0x55555555, }), {R4: 0xFFFFFFFF, PC: 0x00000000, }) # §A8.8.14: AND{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {,<shift>} self.assertRaises( ValueError, compute, 'AND R4, R5 ') - self.assertEqual(compute('AND R4, R4, R5 ', {R4: 0xFFFFFFFEL, R5: 0x00000001L, }), {R4: 0x00000000L, R5: 0x00000001L, }) - self.assertEqual(compute('AND R4, R4, R5 LSL 1 ', {R4: 0x00000011L, R5: 0x00000008L, }), {R4: 0x00000010L, R5: 0x00000008L, }) - self.assertEqual(compute('AND R4, R4, R5 LSR 2 ', {R4: 0xFFFFFFFFL, R5: 0x80000041L, }), {R4: 0x20000010L, R5: 0x80000041L, }) - self.assertEqual(compute('AND R4, R4, R5 ASR 3 ', {R4: 0xF00000FFL, R5: 0x80000081L, }), {R4: 0xF0000010L, R5: 0x80000081L, }) - self.assertEqual(compute('AND R4, R4, R5 ROR 4 ', {R4: 0xFFFFFFFFL, R5: 0x000000FFL, }), {R4: 0xF000000FL, R5: 0x000000FFL, }) - self.assertEqual(compute('AND R4, R4, R5 RRX ', {R4: 0xFFFFFFFFL, R5: 0x00000101L, }), {R4: ExprCompose(ExprInt(0x80L, 31), cf_init), R5: 0x00000101L, }) + self.assertEqual(compute('AND R4, R4, R5 ', {R4: 0xFFFFFFFE, R5: 0x00000001, }), {R4: 0x00000000, R5: 0x00000001, }) + self.assertEqual(compute('AND R4, R4, R5 LSL 1 ', {R4: 0x00000011, R5: 0x00000008, }), {R4: 0x00000010, R5: 0x00000008, }) + self.assertEqual(compute('AND R4, R4, R5 LSR 2 ', {R4: 0xFFFFFFFF, R5: 0x80000041, }), {R4: 0x20000010, R5: 0x80000041, }) + self.assertEqual(compute('AND R4, R4, R5 ASR 3 ', {R4: 0xF00000FF, R5: 0x80000081, }), {R4: 0xF0000010, R5: 0x80000081, }) + self.assertEqual(compute('AND R4, R4, R5 ROR 4 ', {R4: 0xFFFFFFFF, R5: 0x000000FF, }), {R4: 0xF000000F, R5: 0x000000FF, }) + self.assertEqual(compute('AND R4, R4, R5 RRX ', {R4: 0xFFFFFFFF, R5: 0x00000101, }), {R4: ExprCompose(ExprInt(0x80, 31), cf_init), R5: 0x00000101, }) # §A8.8.15: AND{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <type> <Rs> - self.assertEqual(compute('AND R4, R6, R4 LSL R5', {R4: 0x00000001L, R5: 0x00000004L, R6: -1, }), {R4: 0x00000010L, R5: 0x00000004L, R6: 0xFFFFFFFFL, }) - self.assertEqual(compute('AND R4, R6, R4 LSR R5', {R4: 0x00000110L, R5: 0x80000004L, R6: -1, }), {R4: 0x00000011L, R5: 0x80000004L, R6: 0xFFFFFFFFL, }) - self.assertEqual(compute('AND R4, R6, R4 ASR R5', {R4: 0x80000010L, R5: 0xF0000001L, R6: -1, }), {R4: 0xC0000008L, R5: 0xF0000001L, R6: 0xFFFFFFFFL, }) - self.assertEqual(compute('AND R4, R6, R4 ROR R5', {R4: 0x000000FFL, R5: 0x00000F04L, R6: -1, }), {R4: 0xF000000FL, R5: 0x00000F04L, R6: 0xFFFFFFFFL, }) + self.assertEqual(compute('AND R4, R6, R4 LSL R5', {R4: 0x00000001, R5: 0x00000004, R6: -1, }), {R4: 0x00000010, R5: 0x00000004, R6: 0xFFFFFFFF, }) + self.assertEqual(compute('AND R4, R6, R4 LSR R5', {R4: 0x00000110, R5: 0x80000004, R6: -1, }), {R4: 0x00000011, R5: 0x80000004, R6: 0xFFFFFFFF, }) + self.assertEqual(compute('AND R4, R6, R4 ASR R5', {R4: 0x80000010, R5: 0xF0000001, R6: -1, }), {R4: 0xC0000008, R5: 0xF0000001, R6: 0xFFFFFFFF, }) + self.assertEqual(compute('AND R4, R6, R4 ROR R5', {R4: 0x000000FF, R5: 0x00000F04, R6: -1, }), {R4: 0xF000000F, R5: 0x00000F04, R6: 0xFFFFFFFF, }) def test_ASR(self): # §A8.8.16: ASR{S}{<c>}{<q>} {<Rd>,} <Rm>, #<imm> <==> MOV{S}{<c>}{<q>} {<Rd>,} <Rm>, ASR #<n> @@ -305,191 +308,191 @@ class TestARMSemantic(unittest.TestCase): def test_SUBS(self): # Test against qemu - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x2L, R3: 0x1L}), - { nf: 0L, zf: 0L, cf: 1L, of: 0L, R2: 0x00000002L, R3: 0x1L}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1L, R3: 0x2L}), - { nf: 1L, zf: 0L, cf: 0L, of: 0L, R2: 0x00000001L, R3: 0xFFFFFFFFL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x0L, R3: 0xFFFFFFFFL}), - { nf: 0L, zf: 0L, cf: 0L, of: 0L, R2: 0x00000000L, R3: 0x1L}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0xFFFFFFFFL, R3: 0x0L}), - { nf: 1L, zf: 0L, cf: 1L, of: 0L, R2: 0xFFFFFFFFL, R3: 0xFFFFFFFFL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1L, R3: 0x7FFFFFFFL}), - { nf: 1L, zf: 0L, cf: 0L, of: 0L, R2: 0x00000001L, R3: 0x80000002L}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x7FFFFFFFL, R3: 0x1L}), - { nf: 0L, zf: 0L, cf: 1L, of: 0L, R2: 0x7FFFFFFFL, R3: 0x7FFFFFFEL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000000L, R3: 0x80000001L}), - { nf: 1L, zf: 0L, cf: 0L, of: 0L, R2: 0x80000000L, R3: 0xFFFFFFFFL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000001L, R3: 0x80000000L}), - { nf: 0L, zf: 0L, cf: 1L, of: 0L, R2: 0x80000001L, R3: 0x1L}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x2, R3: 0x1}), + { nf: 0, zf: 0, cf: 1, of: 0, R2: 0x00000002, R3: 0x1}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1, R3: 0x2}), + { nf: 1, zf: 0, cf: 0, of: 0, R2: 0x00000001, R3: 0xFFFFFFFF}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x0, R3: 0xFFFFFFFF}), + { nf: 0, zf: 0, cf: 0, of: 0, R2: 0x00000000, R3: 0x1}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0xFFFFFFFF, R3: 0x0}), + { nf: 1, zf: 0, cf: 1, of: 0, R2: 0xFFFFFFFF, R3: 0xFFFFFFFF}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1, R3: 0x7FFFFFFF}), + { nf: 1, zf: 0, cf: 0, of: 0, R2: 0x00000001, R3: 0x80000002}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x7FFFFFFF, R3: 0x1}), + { nf: 0, zf: 0, cf: 1, of: 0, R2: 0x7FFFFFFF, R3: 0x7FFFFFFE}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000000, R3: 0x80000001}), + { nf: 1, zf: 0, cf: 0, of: 0, R2: 0x80000000, R3: 0xFFFFFFFF}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000001, R3: 0x80000000}), + { nf: 0, zf: 0, cf: 1, of: 0, R2: 0x80000001, R3: 0x1}) def test_CMP(self): # Test against qemu - self.assertEqual(compute('CMP R0, R1 ', {R0: 0x11223344L, R1: 0x88223344L}), - { nf: 1L, zf: 0L, cf: 0L, of: 1L, R0: 0x11223344L, R1: 0x88223344L}) - - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x2L, R3: 0x1L}), - { nf: 0L, zf: 0L, cf: 1L, of: 0L, R2: 0x00000002L, R3: 0x1L}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1L, R3: 0x2L}), - { nf: 1L, zf: 0L, cf: 0L, of: 0L, R2: 0x00000001L, R3: 0xFFFFFFFFL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x0L, R3: 0xFFFFFFFFL}), - { nf: 0L, zf: 0L, cf: 0L, of: 0L, R2: 0x00000000L, R3: 0x1L}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0xFFFFFFFFL, R3: 0x0L}), - { nf: 1L, zf: 0L, cf: 1L, of: 0L, R2: 0xFFFFFFFFL, R3: 0xFFFFFFFFL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1L, R3: 0x7FFFFFFFL}), - { nf: 1L, zf: 0L, cf: 0L, of: 0L, R2: 0x00000001L, R3: 0x80000002L}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x7FFFFFFFL, R3: 0x1L}), - { nf: 0L, zf: 0L, cf: 1L, of: 0L, R2: 0x7FFFFFFFL, R3: 0x7FFFFFFEL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000000L, R3: 0x80000001L}), - { nf: 1L, zf: 0L, cf: 0L, of: 0L, R2: 0x80000000L, R3: 0xFFFFFFFFL}) - self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000001L, R3: 0x80000000L}), - { nf: 0L, zf: 0L, cf: 1L, of: 0L, R2: 0x80000001L, R3: 0x1L}) + self.assertEqual(compute('CMP R0, R1 ', {R0: 0x11223344, R1: 0x88223344}), + { nf: 1, zf: 0, cf: 0, of: 1, R0: 0x11223344, R1: 0x88223344}) + + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x2, R3: 0x1}), + { nf: 0, zf: 0, cf: 1, of: 0, R2: 0x00000002, R3: 0x1}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1, R3: 0x2}), + { nf: 1, zf: 0, cf: 0, of: 0, R2: 0x00000001, R3: 0xFFFFFFFF}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x0, R3: 0xFFFFFFFF}), + { nf: 0, zf: 0, cf: 0, of: 0, R2: 0x00000000, R3: 0x1}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0xFFFFFFFF, R3: 0x0}), + { nf: 1, zf: 0, cf: 1, of: 0, R2: 0xFFFFFFFF, R3: 0xFFFFFFFF}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x1, R3: 0x7FFFFFFF}), + { nf: 1, zf: 0, cf: 0, of: 0, R2: 0x00000001, R3: 0x80000002}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x7FFFFFFF, R3: 0x1}), + { nf: 0, zf: 0, cf: 1, of: 0, R2: 0x7FFFFFFF, R3: 0x7FFFFFFE}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000000, R3: 0x80000001}), + { nf: 1, zf: 0, cf: 0, of: 0, R2: 0x80000000, R3: 0xFFFFFFFF}) + self.assertEqual(compute('SUBS R3, R2, R3 ', {R2: 0x80000001, R3: 0x80000000}), + { nf: 0, zf: 0, cf: 1, of: 0, R2: 0x80000001, R3: 0x1}) def test_ADDS(self): - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {R2: 0x3L, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x0L}) - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {R2: 0x3L, R3: 0x2L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x0L}) - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {R2: 0xffffffffL, R3: 0xffffffffL, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {R2: 0xffffffffL, R3: 0x0L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {R2: 0x80000000L, R3: 0x7fffffffL, of: 0x1L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {R2: 0x80000000L, R3: 0x1L, of: 0x1L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {R2: 0x1L, R3: 0x80000001L, of: 0x1L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {R2: 0x1L, R3: 0x80000000L, of: 0x1L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x2, R3: 0x1}), {R2: 0x3, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x0}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x1, R3: 0x2}), {R2: 0x3, R3: 0x2, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x0}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {R2: 0xffffffff, R3: 0xffffffff, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {R2: 0xffffffff, R3: 0x0, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {R2: 0x80000000, R3: 0x7fffffff, of: 0x1, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {R2: 0x80000000, R3: 0x1, of: 0x1, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {R2: 0x1, R3: 0x80000001, of: 0x1, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('ADDS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {R2: 0x1, R3: 0x80000000, of: 0x1, zf: 0x0, cf: 0x1, nf: 0x0}) def test_ANDS(self): - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0x2L}) - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0xffffffffL}) - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0x0L}) - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x7fffffffL}) - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {zf: 0x0L, R2: 0x80000000L, nf: 0x1L, R3: 0x80000001L}) - self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {zf: 0x0L, R2: 0x80000000L, nf: 0x1L, R3: 0x80000000L}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x2, R3: 0x1}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x1, R3: 0x2}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0x2}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0xffffffff}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0x0}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x7fffffff}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {zf: 0x0, R2: 0x80000000, nf: 0x1, R3: 0x80000001}) + self.assertEqual(compute('ANDS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {zf: 0x0, R2: 0x80000000, nf: 0x1, R3: 0x80000000}) def test_BICS(self): - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {zf: 0x0L, R2: 0x2L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x2L}) - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0xffffffffL}) - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {zf: 0x0L, R2: 0xffffffffL, nf: 0x1L, R3: 0x0L}) - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0x7fffffffL}) - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {zf: 0x0L, R2: 0x7ffffffeL, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0x80000001L}) - self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x80000000L}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x2, R3: 0x1}), {zf: 0x0, R2: 0x2, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x1, R3: 0x2}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x2}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0xffffffff}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {zf: 0x0, R2: 0xffffffff, nf: 0x1, R3: 0x0}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0x7fffffff}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {zf: 0x0, R2: 0x7ffffffe, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0x80000001}) + self.assertEqual(compute('BICS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x80000000}) def test_CMN(self): - self.assertEqual(compute('CMN R2, R3', {R2: 0x2L, R3: 0x1L}), {R2: 0x2L, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x0L}) - self.assertEqual(compute('CMN R2, R3', {R2: 0x1L, R3: 0x2L}), {R2: 0x1L, R3: 0x2L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x0L}) - self.assertEqual(compute('CMN R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {R2: 0x0L, R3: 0xffffffffL, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('CMN R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {R2: 0xffffffffL, R3: 0x0L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('CMN R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {R2: 0x1L, R3: 0x7fffffffL, of: 0x1L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('CMN R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {R2: 0x7fffffffL, R3: 0x1L, of: 0x1L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('CMN R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {R2: 0x80000000L, R3: 0x80000001L, of: 0x1L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('CMN R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {R2: 0x80000001L, R3: 0x80000000L, of: 0x1L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) + self.assertEqual(compute('CMN R2, R3', {R2: 0x2, R3: 0x1}), {R2: 0x2, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x0}) + self.assertEqual(compute('CMN R2, R3', {R2: 0x1, R3: 0x2}), {R2: 0x1, R3: 0x2, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x0}) + self.assertEqual(compute('CMN R2, R3', {R2: 0x0, R3: 0xffffffff}), {R2: 0x0, R3: 0xffffffff, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('CMN R2, R3', {R2: 0xffffffff, R3: 0x0}), {R2: 0xffffffff, R3: 0x0, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('CMN R2, R3', {R2: 0x1, R3: 0x7fffffff}), {R2: 0x1, R3: 0x7fffffff, of: 0x1, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('CMN R2, R3', {R2: 0x7fffffff, R3: 0x1}), {R2: 0x7fffffff, R3: 0x1, of: 0x1, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('CMN R2, R3', {R2: 0x80000000, R3: 0x80000001}), {R2: 0x80000000, R3: 0x80000001, of: 0x1, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('CMN R2, R3', {R2: 0x80000001, R3: 0x80000000}), {R2: 0x80000001, R3: 0x80000000, of: 0x1, zf: 0x0, cf: 0x1, nf: 0x0}) def test_CMP(self): - self.assertEqual(compute('CMP R2, R3', {R2: 0x2L, R3: 0x1L}), {R2: 0x2L, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('CMP R2, R3', {R2: 0x1L, R3: 0x2L}), {R2: 0x1L, R3: 0x2L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('CMP R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {R2: 0x0L, R3: 0xffffffffL, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x0L}) - self.assertEqual(compute('CMP R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {R2: 0xffffffffL, R3: 0x0L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x1L}) - self.assertEqual(compute('CMP R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {R2: 0x1L, R3: 0x7fffffffL, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('CMP R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {R2: 0x7fffffffL, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('CMP R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {R2: 0x80000000L, R3: 0x80000001L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('CMP R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {R2: 0x80000001L, R3: 0x80000000L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) + self.assertEqual(compute('CMP R2, R3', {R2: 0x2, R3: 0x1}), {R2: 0x2, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('CMP R2, R3', {R2: 0x1, R3: 0x2}), {R2: 0x1, R3: 0x2, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('CMP R2, R3', {R2: 0x0, R3: 0xffffffff}), {R2: 0x0, R3: 0xffffffff, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x0}) + self.assertEqual(compute('CMP R2, R3', {R2: 0xffffffff, R3: 0x0}), {R2: 0xffffffff, R3: 0x0, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x1}) + self.assertEqual(compute('CMP R2, R3', {R2: 0x1, R3: 0x7fffffff}), {R2: 0x1, R3: 0x7fffffff, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('CMP R2, R3', {R2: 0x7fffffff, R3: 0x1}), {R2: 0x7fffffff, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('CMP R2, R3', {R2: 0x80000000, R3: 0x80000001}), {R2: 0x80000000, R3: 0x80000001, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('CMP R2, R3', {R2: 0x80000001, R3: 0x80000000}), {R2: 0x80000001, R3: 0x80000000, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) def test_EORS(self): - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {zf: 0x0L, R2: 0x3L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {zf: 0x0L, R2: 0x3L, nf: 0x0L, R3: 0x2L}) - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {zf: 0x0L, R2: 0xffffffffL, nf: 0x1L, R3: 0xffffffffL}) - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {zf: 0x0L, R2: 0xffffffffL, nf: 0x1L, R3: 0x0L}) - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {zf: 0x0L, R2: 0x7ffffffeL, nf: 0x0L, R3: 0x7fffffffL}) - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {zf: 0x0L, R2: 0x7ffffffeL, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x80000001L}) - self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x80000000L}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x2, R3: 0x1}), {zf: 0x0, R2: 0x3, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x1, R3: 0x2}), {zf: 0x0, R2: 0x3, nf: 0x0, R3: 0x2}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {zf: 0x0, R2: 0xffffffff, nf: 0x1, R3: 0xffffffff}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {zf: 0x0, R2: 0xffffffff, nf: 0x1, R3: 0x0}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {zf: 0x0, R2: 0x7ffffffe, nf: 0x0, R3: 0x7fffffff}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {zf: 0x0, R2: 0x7ffffffe, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x80000001}) + self.assertEqual(compute('EORS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x80000000}) def test_MULS(self): - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {zf: 0x0L, R2: 0x2L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {zf: 0x0L, R2: 0x2L, nf: 0x0L, R3: 0x2L}) - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0xffffffffL}) - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0x0L}) - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {zf: 0x0L, R2: 0x7fffffffL, nf: 0x0L, R3: 0x7fffffffL}) - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {zf: 0x0L, R2: 0x7fffffffL, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {zf: 0x0L, R2: 0x80000000L, nf: 0x1L, R3: 0x80000001L}) - self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {zf: 0x0L, R2: 0x80000000L, nf: 0x1L, R3: 0x80000000L}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x2, R3: 0x1}), {zf: 0x0, R2: 0x2, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x1, R3: 0x2}), {zf: 0x0, R2: 0x2, nf: 0x0, R3: 0x2}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0xffffffff}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0x0}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {zf: 0x0, R2: 0x7fffffff, nf: 0x0, R3: 0x7fffffff}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {zf: 0x0, R2: 0x7fffffff, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {zf: 0x0, R2: 0x80000000, nf: 0x1, R3: 0x80000001}) + self.assertEqual(compute('MULS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {zf: 0x0, R2: 0x80000000, nf: 0x1, R3: 0x80000000}) def test_ORRS(self): - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {zf: 0x0L, R2: 0x3L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {zf: 0x0L, R2: 0x3L, nf: 0x0L, R3: 0x2L}) - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {zf: 0x0L, R2: 0xffffffffL, nf: 0x1L, R3: 0xffffffffL}) - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {zf: 0x0L, R2: 0xffffffffL, nf: 0x1L, R3: 0x0L}) - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {zf: 0x0L, R2: 0x7fffffffL, nf: 0x0L, R3: 0x7fffffffL}) - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {zf: 0x0L, R2: 0x7fffffffL, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {zf: 0x0L, R2: 0x80000001L, nf: 0x1L, R3: 0x80000001L}) - self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {zf: 0x0L, R2: 0x80000001L, nf: 0x1L, R3: 0x80000000L}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x2, R3: 0x1}), {zf: 0x0, R2: 0x3, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x1, R3: 0x2}), {zf: 0x0, R2: 0x3, nf: 0x0, R3: 0x2}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {zf: 0x0, R2: 0xffffffff, nf: 0x1, R3: 0xffffffff}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {zf: 0x0, R2: 0xffffffff, nf: 0x1, R3: 0x0}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {zf: 0x0, R2: 0x7fffffff, nf: 0x0, R3: 0x7fffffff}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {zf: 0x0, R2: 0x7fffffff, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {zf: 0x0, R2: 0x80000001, nf: 0x1, R3: 0x80000001}) + self.assertEqual(compute('ORRS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {zf: 0x0, R2: 0x80000001, nf: 0x1, R3: 0x80000000}) def test_RSBS(self): - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {R2: 0xffffffffL, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {R2: 0x1L, R3: 0x2L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {R2: 0xffffffffL, R3: 0xffffffffL, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x1L}) - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {R2: 0x1L, R3: 0x0L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x0L}) - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {R2: 0x7ffffffeL, R3: 0x7fffffffL, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {R2: 0x80000002L, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {R2: 0x1L, R3: 0x80000001L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {R2: 0xffffffffL, R3: 0x80000000L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x2, R3: 0x1}), {R2: 0xffffffff, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x1, R3: 0x2}), {R2: 0x1, R3: 0x2, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {R2: 0xffffffff, R3: 0xffffffff, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x1}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {R2: 0x1, R3: 0x0, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x0}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {R2: 0x7ffffffe, R3: 0x7fffffff, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {R2: 0x80000002, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {R2: 0x1, R3: 0x80000001, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('RSBS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {R2: 0xffffffff, R3: 0x80000000, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) def test_SUBS(self): - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x2L, R3: 0x1L}), {R2: 0x1L, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x1L, R3: 0x2L}), {R2: 0xffffffffL, R3: 0x2L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {R2: 0x1L, R3: 0xffffffffL, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x0L}) - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {R2: 0xffffffffL, R3: 0x0L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x1L}) - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {R2: 0x80000002L, R3: 0x7fffffffL, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {R2: 0x7ffffffeL, R3: 0x1L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {R2: 0xffffffffL, R3: 0x80000001L, of: 0x0L, zf: 0x0L, cf: 0x0L, nf: 0x1L}) - self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {R2: 0x1L, R3: 0x80000000L, of: 0x0L, zf: 0x0L, cf: 0x1L, nf: 0x0L}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x2, R3: 0x1}), {R2: 0x1, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x1, R3: 0x2}), {R2: 0xffffffff, R3: 0x2, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x0, R3: 0xffffffff}), {R2: 0x1, R3: 0xffffffff, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x0}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0xffffffff, R3: 0x0}), {R2: 0xffffffff, R3: 0x0, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x1}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x1, R3: 0x7fffffff}), {R2: 0x80000002, R3: 0x7fffffff, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x7fffffff, R3: 0x1}), {R2: 0x7ffffffe, R3: 0x1, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x80000000, R3: 0x80000001}), {R2: 0xffffffff, R3: 0x80000001, of: 0x0, zf: 0x0, cf: 0x0, nf: 0x1}) + self.assertEqual(compute('SUBS R2, R2, R3', {R2: 0x80000001, R3: 0x80000000}), {R2: 0x1, R3: 0x80000000, of: 0x0, zf: 0x0, cf: 0x1, nf: 0x0}) def test_TEQ(self): - self.assertEqual(compute('TEQ R2, R3', {R2: 0x2L, R3: 0x1L}), {zf: 0x0L, R2: 0x2L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('TEQ R2, R3', {R2: 0x1L, R3: 0x2L}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x2L}) - self.assertEqual(compute('TEQ R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {zf: 0x0L, R2: 0x0L, nf: 0x1L, R3: 0xffffffffL}) - self.assertEqual(compute('TEQ R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {zf: 0x0L, R2: 0xffffffffL, nf: 0x1L, R3: 0x0L}) - self.assertEqual(compute('TEQ R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x7fffffffL}) - self.assertEqual(compute('TEQ R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {zf: 0x0L, R2: 0x7fffffffL, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('TEQ R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {zf: 0x0L, R2: 0x80000000L, nf: 0x0L, R3: 0x80000001L}) - self.assertEqual(compute('TEQ R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {zf: 0x0L, R2: 0x80000001L, nf: 0x0L, R3: 0x80000000L}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0x2, R3: 0x1}), {zf: 0x0, R2: 0x2, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0x1, R3: 0x2}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x2}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0x0, R3: 0xffffffff}), {zf: 0x0, R2: 0x0, nf: 0x1, R3: 0xffffffff}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0xffffffff, R3: 0x0}), {zf: 0x0, R2: 0xffffffff, nf: 0x1, R3: 0x0}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0x1, R3: 0x7fffffff}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x7fffffff}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0x7fffffff, R3: 0x1}), {zf: 0x0, R2: 0x7fffffff, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0x80000000, R3: 0x80000001}), {zf: 0x0, R2: 0x80000000, nf: 0x0, R3: 0x80000001}) + self.assertEqual(compute('TEQ R2, R3', {R2: 0x80000001, R3: 0x80000000}), {zf: 0x0, R2: 0x80000001, nf: 0x0, R3: 0x80000000}) def test_TST(self): - self.assertEqual(compute('TST R2, R3', {R2: 0x2L, R3: 0x1L}), {zf: 0x1L, R2: 0x2L, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('TST R2, R3', {R2: 0x1L, R3: 0x2L}), {zf: 0x1L, R2: 0x1L, nf: 0x0L, R3: 0x2L}) - self.assertEqual(compute('TST R2, R3', {R2: 0x0L, R3: 0xffffffffL}), {zf: 0x1L, R2: 0x0L, nf: 0x0L, R3: 0xffffffffL}) - self.assertEqual(compute('TST R2, R3', {R2: 0xffffffffL, R3: 0x0L}), {zf: 0x1L, R2: 0xffffffffL, nf: 0x0L, R3: 0x0L}) - self.assertEqual(compute('TST R2, R3', {R2: 0x1L, R3: 0x7fffffffL}), {zf: 0x0L, R2: 0x1L, nf: 0x0L, R3: 0x7fffffffL}) - self.assertEqual(compute('TST R2, R3', {R2: 0x7fffffffL, R3: 0x1L}), {zf: 0x0L, R2: 0x7fffffffL, nf: 0x0L, R3: 0x1L}) - self.assertEqual(compute('TST R2, R3', {R2: 0x80000000L, R3: 0x80000001L}), {zf: 0x0L, R2: 0x80000000L, nf: 0x1L, R3: 0x80000001L}) - self.assertEqual(compute('TST R2, R3', {R2: 0x80000001L, R3: 0x80000000L}), {zf: 0x0L, R2: 0x80000001L, nf: 0x1L, R3: 0x80000000L}) + self.assertEqual(compute('TST R2, R3', {R2: 0x2, R3: 0x1}), {zf: 0x1, R2: 0x2, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('TST R2, R3', {R2: 0x1, R3: 0x2}), {zf: 0x1, R2: 0x1, nf: 0x0, R3: 0x2}) + self.assertEqual(compute('TST R2, R3', {R2: 0x0, R3: 0xffffffff}), {zf: 0x1, R2: 0x0, nf: 0x0, R3: 0xffffffff}) + self.assertEqual(compute('TST R2, R3', {R2: 0xffffffff, R3: 0x0}), {zf: 0x1, R2: 0xffffffff, nf: 0x0, R3: 0x0}) + self.assertEqual(compute('TST R2, R3', {R2: 0x1, R3: 0x7fffffff}), {zf: 0x0, R2: 0x1, nf: 0x0, R3: 0x7fffffff}) + self.assertEqual(compute('TST R2, R3', {R2: 0x7fffffff, R3: 0x1}), {zf: 0x0, R2: 0x7fffffff, nf: 0x0, R3: 0x1}) + self.assertEqual(compute('TST R2, R3', {R2: 0x80000000, R3: 0x80000001}), {zf: 0x0, R2: 0x80000000, nf: 0x1, R3: 0x80000001}) + self.assertEqual(compute('TST R2, R3', {R2: 0x80000001, R3: 0x80000000}), {zf: 0x0, R2: 0x80000001, nf: 0x1, R3: 0x80000000}) def test_UMUL(self): - self.assertEqual(compute('UMULL R1, R2, R4, R5', {R4: 0x0L, R5: 0x0L}), {R1: 0x0L, R2: 0x0L, R4: 0x0L, R5: 0x0L}) - self.assertEqual(compute('UMULL R0, R1, R2, R3', {R2: 0x1L, R3: 0x80808080L}), {R0: 0x80808080L, R1: 0x0L, R2: 0x1L, R3: 0x80808080L}) - self.assertEqual(compute('UMULL R2, R3, R4, R5', {R4: 0x12345678L, R5: 0x87654321L}), {R2: 0x70b88d78L, R3: 0x09a0cd05L, R4: 0x12345678L, R5: 0x87654321L}) - self.assertEqual(compute('UMULL R2, R3, R4, R5', {R4: 0xffffffffL, R5: 0x00000002L}), {R2: 0xfffffffeL, R3: 0x00000001L, R4: 0xffffffffL, R5: 0x00000002L}) + self.assertEqual(compute('UMULL R1, R2, R4, R5', {R4: 0x0, R5: 0x0}), {R1: 0x0, R2: 0x0, R4: 0x0, R5: 0x0}) + self.assertEqual(compute('UMULL R0, R1, R2, R3', {R2: 0x1, R3: 0x80808080}), {R0: 0x80808080, R1: 0x0, R2: 0x1, R3: 0x80808080}) + self.assertEqual(compute('UMULL R2, R3, R4, R5', {R4: 0x12345678, R5: 0x87654321}), {R2: 0x70b88d78, R3: 0x09a0cd05, R4: 0x12345678, R5: 0x87654321}) + self.assertEqual(compute('UMULL R2, R3, R4, R5', {R4: 0xffffffff, R5: 0x00000002}), {R2: 0xfffffffe, R3: 0x00000001, R4: 0xffffffff, R5: 0x00000002}) def test_UMLAL(self): - self.assertEqual(compute('UMLAL R1, R2, R4, R5', {R1: 0x0L, R2: 0x0L, R4: 0x1L, R5: 0x0L}), {R1: 0x0L, R2: 0x0L, R4: 0x1L, R5: 0x0L}) - self.assertEqual(compute('UMLAL R0, R1, R2, R3', {R0: 0x0L, R1: 0x0L, R2: 0x1L, R3: 0x80808080L}), {R0: 0x80808080L, R1: 0x0L, R2: 0x1L, R3: 0x80808080L}) - self.assertEqual(compute('UMLAL R2, R3, R4, R5', {R2: 0xffffffffL, R3: 0x0L, R4: 0x12345678L, R5: 0x87654321L}), {R2: 0x70b88d77L, R3: 0x09a0cd06L, R4: 0x12345678L, R5: 0x87654321L}) - self.assertEqual(compute('UMLAL R2, R3, R4, R5', {R2: 0xffffffffL, R3: 0x2L, R4: 0x12345678L, R5: 0x87654321L}), {R2: 0x70b88d77L, R3: 0x09a0cd08L, R4: 0x12345678L, R5: 0x87654321L}) + self.assertEqual(compute('UMLAL R1, R2, R4, R5', {R1: 0x0, R2: 0x0, R4: 0x1, R5: 0x0}), {R1: 0x0, R2: 0x0, R4: 0x1, R5: 0x0}) + self.assertEqual(compute('UMLAL R0, R1, R2, R3', {R0: 0x0, R1: 0x0, R2: 0x1, R3: 0x80808080}), {R0: 0x80808080, R1: 0x0, R2: 0x1, R3: 0x80808080}) + self.assertEqual(compute('UMLAL R2, R3, R4, R5', {R2: 0xffffffff, R3: 0x0, R4: 0x12345678, R5: 0x87654321}), {R2: 0x70b88d77, R3: 0x09a0cd06, R4: 0x12345678, R5: 0x87654321}) + self.assertEqual(compute('UMLAL R2, R3, R4, R5', {R2: 0xffffffff, R3: 0x2, R4: 0x12345678, R5: 0x87654321}), {R2: 0x70b88d77, R3: 0x09a0cd08, R4: 0x12345678, R5: 0x87654321}) def test_SMUL(self): - self.assertEqual(compute('SMULL R1, R2, R4, R5', {R4: 0x0L, R5: 0x0L}), {R1: 0x0L, R2: 0x0L, R4: 0x0L, R5: 0x0L}) - self.assertEqual(compute('SMULL R0, R1, R2, R3', {R2: 0x1L, R3: 0x80808080L}), {R0: 0x80808080L, R1: 0xffffffffL, R2: 0x1L, R3: 0x80808080L}) - self.assertEqual(compute('SMULL R0, R1, R2, R3', {R2: 0xffff0000L, R3: 0xffff0000L}), {R0: 0x0L, R1: 0x1L, R2: 0xffff0000L, R3: 0xffff0000L}) - self.assertEqual(compute('SMULL R2, R3, R4, R5', {R4: 0x12345678L, R5: 0x87654321L}), {R2: 0x70b88d78L, R3: 0xf76c768dL, R4: 0x12345678L, R5: 0x87654321L}) - self.assertEqual(compute('SMULL R2, R3, R4, R5', {R4: 0xffffffffL, R5: 0x00000002L}), {R2: 0xfffffffeL, R3: 0xffffffffL, R4: 0xffffffffL, R5: 0x00000002L}) + self.assertEqual(compute('SMULL R1, R2, R4, R5', {R4: 0x0, R5: 0x0}), {R1: 0x0, R2: 0x0, R4: 0x0, R5: 0x0}) + self.assertEqual(compute('SMULL R0, R1, R2, R3', {R2: 0x1, R3: 0x80808080}), {R0: 0x80808080, R1: 0xffffffff, R2: 0x1, R3: 0x80808080}) + self.assertEqual(compute('SMULL R0, R1, R2, R3', {R2: 0xffff0000, R3: 0xffff0000}), {R0: 0x0, R1: 0x1, R2: 0xffff0000, R3: 0xffff0000}) + self.assertEqual(compute('SMULL R2, R3, R4, R5', {R4: 0x12345678, R5: 0x87654321}), {R2: 0x70b88d78, R3: 0xf76c768d, R4: 0x12345678, R5: 0x87654321}) + self.assertEqual(compute('SMULL R2, R3, R4, R5', {R4: 0xffffffff, R5: 0x00000002}), {R2: 0xfffffffe, R3: 0xffffffff, R4: 0xffffffff, R5: 0x00000002}) def test_SMLAL(self): - self.assertEqual(compute('SMLAL R1, R2, R4, R5', {R1: 0x0L, R2: 0x0L, R4: 0x1L, R5: 0x0L}), {R1: 0x0L, R2: 0x0L, R4: 0x1L, R5: 0x0L}) - self.assertEqual(compute('SMLAL R0, R1, R2, R3', {R0: 0x0L, R1: 0x0L, R2: 0x1L, R3: 0x80808080L}), {R0: 0x80808080L, R1: 0xffffffffL, R2: 0x1L, R3: 0x80808080L}) - self.assertEqual(compute('SMLAL R2, R3, R4, R5', {R2: 0xffffffffL, R3: 0x0L, R4: 0x12345678L, R5: 0x87654321L}), {R2: 0x70b88d77L, R3: 0xf76c768eL, R4: 0x12345678L, R5: 0x87654321L}) - self.assertEqual(compute('SMLAL R2, R3, R4, R5', {R2: 0xffffffffL, R3: 0x00000002L, R4: 0x12345678L, R5: 0x87654321L}), {R2: 0x70b88d77L, R3: 0xf76c7690L, R4: 0x12345678L, R5: 0x87654321L}) + self.assertEqual(compute('SMLAL R1, R2, R4, R5', {R1: 0x0, R2: 0x0, R4: 0x1, R5: 0x0}), {R1: 0x0, R2: 0x0, R4: 0x1, R5: 0x0}) + self.assertEqual(compute('SMLAL R0, R1, R2, R3', {R0: 0x0, R1: 0x0, R2: 0x1, R3: 0x80808080}), {R0: 0x80808080, R1: 0xffffffff, R2: 0x1, R3: 0x80808080}) + self.assertEqual(compute('SMLAL R2, R3, R4, R5', {R2: 0xffffffff, R3: 0x0, R4: 0x12345678, R5: 0x87654321}), {R2: 0x70b88d77, R3: 0xf76c768e, R4: 0x12345678, R5: 0x87654321}) + self.assertEqual(compute('SMLAL R2, R3, R4, R5', {R2: 0xffffffff, R3: 0x00000002, R4: 0x12345678, R5: 0x87654321}), {R2: 0x70b88d77, R3: 0xf76c7690, R4: 0x12345678, R5: 0x87654321}) if __name__ == '__main__': testsuite = unittest.TestLoader().loadTestsFromTestCase(TestARMSemantic) diff --git a/test/arch/mep/asm/test_asm.py b/test/arch/mep/asm/test_asm.py index ddf91ed6..7762669a 100644 --- a/test/arch/mep/asm/test_asm.py +++ b/test/arch/mep/asm/test_asm.py @@ -1,9 +1,11 @@ # Toshiba MeP-c4 - Misc unit tests # Guillaume Valadon <guillaume@valadon.net> -from miasm2.arch.mep.arch import mn_mep +from __future__ import print_function +from miasm.core.utils import decode_hex, encode_hex +from miasm.arch.mep.arch import mn_mep -class TestMisc: +class TestMisc(object): def test(self): @@ -18,21 +20,23 @@ class TestMisc: unit_tests += [("SW R7, 0x50(SP)", "4752")] for mn_str, mn_hex in unit_tests: - print "-" * 49 # Tests separation + print("-" * 49) # Tests separation # Dissassemble - mn_bin = mn_hex.decode("hex") + mn_bin = decode_hex(mn_hex) mn = mn_mep.dis(mn_bin, "b") - print "dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20)) + print("dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20))) assert(str(mn) == mn_str) # dissassemble assertion # Assemble and return all possible candidates instr = mn_mep.fromstring(str(mn), "b") instr.mode = "b" - asm_list = [i.encode("hex") for i in mn_mep.asm(instr)] + asm_list = [encode_hex(i).decode() for i in mn_mep.asm(instr)] # Print the results - print "asm: %s -> %s" % (mn_str.rjust(20), - ", ".join(asm_list).rjust(20)) + print("asm: %s -> %s" % ( + mn_str.rjust(20), + ", ".join(asm_list).rjust(20)) + ) assert(mn_hex in asm_list) # assemble assertion diff --git a/test/arch/mep/asm/test_major_opcode_0.py b/test/arch/mep/asm/test_major_opcode_0.py index 69a9685c..db288e47 100644 --- a/test/arch/mep/asm/test_major_opcode_0.py +++ b/test/arch/mep/asm/test_major_opcode_0.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor0: +class TestMajor0(object): def test_MOV(self): """Test the MOV instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_1.py b/test/arch/mep/asm/test_major_opcode_1.py index c401bfd2..3a3c6538 100644 --- a/test/arch/mep/asm/test_major_opcode_1.py +++ b/test/arch/mep/asm/test_major_opcode_1.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor1: +class TestMajor1(object): def test_OR(self): """Test the OR instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_10.py b/test/arch/mep/asm/test_major_opcode_10.py index f1089c61..e10992c8 100644 --- a/test/arch/mep/asm/test_major_opcode_10.py +++ b/test/arch/mep/asm/test_major_opcode_10.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor10: +class TestMajor10(object): def test_BEQZ(self): """Test the BEQZ instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_11.py b/test/arch/mep/asm/test_major_opcode_11.py index b5d8a278..38f93e8b 100644 --- a/test/arch/mep/asm/test_major_opcode_11.py +++ b/test/arch/mep/asm/test_major_opcode_11.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor11: +class TestMajor11(object): def test_BRA(self): """Test the BRA instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_12.py b/test/arch/mep/asm/test_major_opcode_12.py index e721d287..c353861e 100644 --- a/test/arch/mep/asm/test_major_opcode_12.py +++ b/test/arch/mep/asm/test_major_opcode_12.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor12: +class TestMajor12(object): def test_ADD3(self): """Test the ADD3 instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_13.py b/test/arch/mep/asm/test_major_opcode_13.py index 996b47e3..bf95572c 100644 --- a/test/arch/mep/asm/test_major_opcode_13.py +++ b/test/arch/mep/asm/test_major_opcode_13.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor13: +class TestMajor13(object): def test_MOVU(self): """Test the MOVU instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_14.py b/test/arch/mep/asm/test_major_opcode_14.py index 6ad3c757..9ec99550 100644 --- a/test/arch/mep/asm/test_major_opcode_14.py +++ b/test/arch/mep/asm/test_major_opcode_14.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor14: +class TestMajor14(object): def test_BEQI(self): """Test the BEQI instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_15.py b/test/arch/mep/asm/test_major_opcode_15.py index ecad8b3f..891626e8 100644 --- a/test/arch/mep/asm/test_major_opcode_15.py +++ b/test/arch/mep/asm/test_major_opcode_15.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor15: +class TestMajor15(object): def test_DSP(self): """Test the DSP instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_2.py b/test/arch/mep/asm/test_major_opcode_2.py index 07743813..4cbe36ca 100644 --- a/test/arch/mep/asm/test_major_opcode_2.py +++ b/test/arch/mep/asm/test_major_opcode_2.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor2: +class TestMajor2(object): def test_BSETM(self): """Test the BSETM instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_3.py b/test/arch/mep/asm/test_major_opcode_3.py index 3e0c5864..793a4e87 100644 --- a/test/arch/mep/asm/test_major_opcode_3.py +++ b/test/arch/mep/asm/test_major_opcode_3.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor3: +class TestMajor3(object): def test_SWCPI(self): """Test the SWCPI instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_4.py b/test/arch/mep/asm/test_major_opcode_4.py index e52acf3f..a6f57ac2 100644 --- a/test/arch/mep/asm/test_major_opcode_4.py +++ b/test/arch/mep/asm/test_major_opcode_4.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor4: +class TestMajor4(object): def test_ADD3(self): """Test the ADD3 instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_5.py b/test/arch/mep/asm/test_major_opcode_5.py index e39230f4..2250c123 100644 --- a/test/arch/mep/asm/test_major_opcode_5.py +++ b/test/arch/mep/asm/test_major_opcode_5.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor5: +class TestMajor5(object): def test_MOV(self): """Test the MOV instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_6.py b/test/arch/mep/asm/test_major_opcode_6.py index 5eda1ea6..e10d1064 100644 --- a/test/arch/mep/asm/test_major_opcode_6.py +++ b/test/arch/mep/asm/test_major_opcode_6.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor6: +class TestMajor6(object): def test_ADD(self): """Test the ADD instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_7.py b/test/arch/mep/asm/test_major_opcode_7.py index 15a045da..1b1fba78 100644 --- a/test/arch/mep/asm/test_major_opcode_7.py +++ b/test/arch/mep/asm/test_major_opcode_7.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor7: +class TestMajor7(object): def test_DI(self): """Test the DI instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_8.py b/test/arch/mep/asm/test_major_opcode_8.py index 7f15f9e8..900cf004 100644 --- a/test/arch/mep/asm/test_major_opcode_8.py +++ b/test/arch/mep/asm/test_major_opcode_8.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor8: +class TestMajor8(object): def test_SB(self): """Test the SB instruction""" diff --git a/test/arch/mep/asm/test_major_opcode_9.py b/test/arch/mep/asm/test_major_opcode_9.py index b8949887..9e59a863 100644 --- a/test/arch/mep/asm/test_major_opcode_9.py +++ b/test/arch/mep/asm/test_major_opcode_9.py @@ -4,7 +4,7 @@ from ut_helpers_asm import check_instruction -class TestMajor9: +class TestMajor9(object): def test_ADD3(self): """Test the ADD3 instruction""" diff --git a/test/arch/mep/asm/ut_helpers_asm.py b/test/arch/mep/asm/ut_helpers_asm.py index af010afc..9f6dc5c2 100644 --- a/test/arch/mep/asm/ut_helpers_asm.py +++ b/test/arch/mep/asm/ut_helpers_asm.py @@ -1,17 +1,22 @@ # Toshiba MeP-c4 - unit tests helpers # Guillaume Valadon <guillaume@valadon.net> -from miasm2.arch.mep.arch import mn_mep -from miasm2.core.cpu import Disasm_Exception -from miasm2.core.locationdb import LocationDB -from miasm2.expression.expression import ExprId, ExprInt, ExprLoc +from __future__ import print_function + +from builtins import range + +from miasm.core.utils import decode_hex, encode_hex +from miasm.arch.mep.arch import mn_mep +from miasm.core.cpu import Disasm_Exception +from miasm.core.locationdb import LocationDB +from miasm.expression.expression import ExprId, ExprInt, ExprLoc import re def dis(mn_hex): """Disassembly helper""" - mn_bin = mn_hex.decode("hex") + mn_bin = decode_hex(mn_hex) try: return mn_mep.dis(mn_bin, "b") except Disasm_Exception: @@ -50,7 +55,7 @@ def check_instruction(mn_str, mn_hex, multi=None, offset=0): addr = loc_db.get_location_offset(mn.args[i].loc_key) mn.args[i] = ExprInt(addr, args_size[i]) - print "dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20)) + print("dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20))) assert(str(mn) == mn_str) # disassemble assertion # Assemble and return all possible candidates @@ -59,21 +64,25 @@ def check_instruction(mn_str, mn_hex, multi=None, offset=0): instr.mode = "b" if instr.offset: instr.fixDstOffset() - asm_list = [i.encode("hex") for i in mn_mep.asm(instr)] + asm_list = [encode_hex(i).decode() for i in mn_mep.asm(instr)] # Check instructions variants if multi: - print "Instructions count:", len(asm_list) + print("Instructions count:", len(asm_list)) assert(len(asm_list) == multi) # Ensure that variants correspond to the same disassembled instruction - for mn_hex in asm_list: - mn = dis(mn_hex) - print "dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20)) + for mn_hex_tmp in asm_list: + mn = dis(mn_hex_tmp) + print("dis: %s -> %s" % (mn_hex_tmp.rjust(20), str(mn).rjust(20))) # Check the assembly result - print "asm: %s -> %s" % (mn_str.rjust(20), - ", ".join(asm_list).rjust(20)) + print( + "asm: %s -> %s" % ( + mn_str.rjust(20), + ", ".join(asm_list).rjust(20) + ) + ) assert(mn_hex in asm_list) # assemble assertion @@ -83,10 +92,10 @@ def launch_tests(obj): test_methods = [name for name in dir(obj) if name.startswith("test")] for method in test_methods: - print method + print(method) try: getattr(obj, method)() except AttributeError as e: - print "Method not found: %s" % method + print("Method not found: %s" % method) assert(False) - print '-' * 42 + print('-' * 42) diff --git a/test/arch/mep/ir/test_arithmetic.py b/test/arch/mep/ir/test_arithmetic.py index 6da938e9..d404f51c 100644 --- a/test/arch/mep/ir/test_arithmetic.py +++ b/test/arch/mep/ir/test_arithmetic.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -class TestArithmetic: +class TestArithmetic(object): def test_add3(self): """Test ADD3 execution""" diff --git a/test/arch/mep/ir/test_bitmanipulation.py b/test/arch/mep/ir/test_bitmanipulation.py index 06466f9d..6ec200c5 100644 --- a/test/arch/mep/ir/test_bitmanipulation.py +++ b/test/arch/mep/ir/test_bitmanipulation.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprMem +from miasm.expression.expression import ExprId, ExprInt, ExprMem -class TestBitManipulation: +class TestBitManipulation(object): def test_bsetm(self): """Test BSETM execution""" diff --git a/test/arch/mep/ir/test_branchjump.py b/test/arch/mep/ir/test_branchjump.py index 3f78558b..828b172f 100644 --- a/test/arch/mep/ir/test_branchjump.py +++ b/test/arch/mep/ir/test_branchjump.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt +from miasm.expression.expression import ExprId, ExprInt -class TestBranchJump: +class TestBranchJump(object): def test_bra(self): """Test BRA execution""" diff --git a/test/arch/mep/ir/test_control.py b/test/arch/mep/ir/test_control.py index a1b3c7c7..04c8b4d0 100644 --- a/test/arch/mep/ir/test_control.py +++ b/test/arch/mep/ir/test_control.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -class TestControl: +class TestControl(object): def test_stc(self): """Test STC execution""" diff --git a/test/arch/mep/ir/test_coprocessor.py b/test/arch/mep/ir/test_coprocessor.py index e9b745ff..bd8fd39c 100644 --- a/test/arch/mep/ir/test_coprocessor.py +++ b/test/arch/mep/ir/test_coprocessor.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprMem, ExprInt +from miasm.expression.expression import ExprId, ExprMem, ExprInt -class TestCoprocessor: +class TestCoprocessor(object): def test_swcp(self): """Test SWCP execution""" diff --git a/test/arch/mep/ir/test_datacache.py b/test/arch/mep/ir/test_datacache.py index a462315d..7d92f9c7 100644 --- a/test/arch/mep/ir/test_datacache.py +++ b/test/arch/mep/ir/test_datacache.py @@ -4,7 +4,7 @@ from ut_helpers_ir import exec_instruction -class TestDataCache: +class TestDataCache(object): def test_cache(self): """Test CACHE execution""" diff --git a/test/arch/mep/ir/test_debug.py b/test/arch/mep/ir/test_debug.py index 53f4064d..0c1026de 100644 --- a/test/arch/mep/ir/test_debug.py +++ b/test/arch/mep/ir/test_debug.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -class TestDebug: +class TestDebug(object): def test_dret(self): """Test DRET execution""" diff --git a/test/arch/mep/ir/test_divide.py b/test/arch/mep/ir/test_divide.py index a63d0c5e..424a9876 100644 --- a/test/arch/mep/ir/test_divide.py +++ b/test/arch/mep/ir/test_divide.py @@ -3,11 +3,11 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.jitter.csts import EXCEPT_DIV_BY_ZERO -class TestDivide: +class TestDivide(object): def test_div(self): """Test DIV execution""" diff --git a/test/arch/mep/ir/test_extension.py b/test/arch/mep/ir/test_extension.py index 72423220..72ad8c22 100644 --- a/test/arch/mep/ir/test_extension.py +++ b/test/arch/mep/ir/test_extension.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprMem, ExprInt +from miasm.expression.expression import ExprId, ExprMem, ExprInt -class TestExtension: +class TestExtension(object): def test_extb(self): """Test EXTB execution""" diff --git a/test/arch/mep/ir/test_ir.py b/test/arch/mep/ir/test_ir.py index 3fec9ec9..be8e24e1 100644 --- a/test/arch/mep/ir/test_ir.py +++ b/test/arch/mep/ir/test_ir.py @@ -1,15 +1,18 @@ # Toshiba MeP-c4 - Misc unit tests # Guillaume Valadon <guillaume@valadon.net> -from miasm2.arch.mep.arch import mn_mep -from miasm2.arch.mep.regs import regs_init -from miasm2.arch.mep.ira import ir_mepb, ir_a_mepb -from miasm2.expression.expression import ExprId, ExprInt, ExprMem -from miasm2.ir.symbexec import SymbolicExecutionEngine -from miasm2.core.locationdb import LocationDB +from __future__ import print_function +from miasm.core.utils import decode_hex +from miasm.arch.mep.arch import mn_mep +from miasm.arch.mep.regs import regs_init +from miasm.arch.mep.ira import ir_mepb, ir_a_mepb +from miasm.expression.expression import ExprId, ExprInt, ExprMem +from miasm.ir.symbexec import SymbolicExecutionEngine +from miasm.core.locationdb import LocationDB -class TestMisc: + +class TestMisc(object): def test(self): @@ -18,16 +21,16 @@ class TestMisc: def exec_instruction(hex_asm, init_values): """Symbolically execute an instruction""" - print "Hex:", hex_asm + print("Hex:", hex_asm) # Disassemble an instruction - mn = mn_mep.dis(hex_asm.decode("hex"), "b") - print "Dis:", mn + mn = mn_mep.dis(decode_hex(hex_asm), "b") + print("Dis:", mn) # Get the IR im = ir_mepb() iir, eiir, = im.get_ir(mn) - print "\nInternal representation:", iir + print("\nInternal representation:", iir) # Symbolic execution loc_db = LocationDB() @@ -37,13 +40,13 @@ class TestMisc: for reg_expr_id, reg_expr_value in init_values: sb.symbols[reg_expr_id] = reg_expr_value - print "\nModified registers:", [reg for reg in sb.modified(mems=False)] - print "Modified memories:", [mem for mem in sb.modified()] + print("\nModified registers:", [reg for reg in sb.modified(mems=False)]) + print("Modified memories:", [mem for mem in sb.modified()]) - print "\nFinal registers:" + print("\nFinal registers:") sb.dump(mems=False) - print "\nFinal mems:" + print("\nFinal mems:") sb.dump() for hex_asm, init_values in [("6108", [(ExprId("R1", 32), ExprInt(0x40, 32))]), @@ -52,5 +55,5 @@ class TestMisc: ("0948", [(ExprId("R4", 32), ExprInt(0x41, 32)), (ExprId("R9", 32), ExprInt(0x28, 32)), (ExprMem(ExprInt(0x41, 32), 8), ExprInt(0, 8))])]: - print "-" * 49 # Tests separation + print("-" * 49) # Tests separation exec_instruction(hex_asm, init_values) diff --git a/test/arch/mep/ir/test_ldz.py b/test/arch/mep/ir/test_ldz.py index 02960b60..f14172b2 100644 --- a/test/arch/mep/ir/test_ldz.py +++ b/test/arch/mep/ir/test_ldz.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -class TestLdz: +class TestLdz(object): def test_ldz(self): """Test LDZ execution""" diff --git a/test/arch/mep/ir/test_loadstore.py b/test/arch/mep/ir/test_loadstore.py index c6b40d55..87343fcb 100644 --- a/test/arch/mep/ir/test_loadstore.py +++ b/test/arch/mep/ir/test_loadstore.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprMem, ExprInt +from miasm.expression.expression import ExprId, ExprMem, ExprInt -class TestLoadStore: +class TestLoadStore(object): def test_sb(self): """Test SB execution""" diff --git a/test/arch/mep/ir/test_logical.py b/test/arch/mep/ir/test_logical.py index 61cbbf0a..0e5aef76 100644 --- a/test/arch/mep/ir/test_logical.py +++ b/test/arch/mep/ir/test_logical.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -class TestLogical: +class TestLogical(object): def test_or(self): """Test OR execution""" diff --git a/test/arch/mep/ir/test_move.py b/test/arch/mep/ir/test_move.py index 56a4225e..30af1a74 100644 --- a/test/arch/mep/ir/test_move.py +++ b/test/arch/mep/ir/test_move.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprMem, ExprInt +from miasm.expression.expression import ExprId, ExprMem, ExprInt -class TestMove: +class TestMove(object): def test_mov(self): """Test MOV execution""" diff --git a/test/arch/mep/ir/test_multiply.py b/test/arch/mep/ir/test_multiply.py index 0618f69f..065f1a59 100644 --- a/test/arch/mep/ir/test_multiply.py +++ b/test/arch/mep/ir/test_multiply.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -class TestMultiply: +class TestMultiply(object): def test_mul(self): """Test MUL execution""" diff --git a/test/arch/mep/ir/test_repeat.py b/test/arch/mep/ir/test_repeat.py index 252764b1..e684ef87 100644 --- a/test/arch/mep/ir/test_repeat.py +++ b/test/arch/mep/ir/test_repeat.py @@ -3,10 +3,10 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -class TestRepeat: +class TestRepeat(object): def test_repeat(self): """Test REPEAT execution""" diff --git a/test/arch/mep/ir/test_shift.py b/test/arch/mep/ir/test_shift.py index b63f9ed7..cac48660 100644 --- a/test/arch/mep/ir/test_shift.py +++ b/test/arch/mep/ir/test_shift.py @@ -3,11 +3,11 @@ from ut_helpers_ir import exec_instruction -from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp -from miasm2.core.cpu import sign_ext +from miasm.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm.core.cpu import sign_ext -class TestShift: +class TestShift(object): def test_sra(self): """Test SRA execution""" diff --git a/test/arch/mep/ir/ut_helpers_ir.py b/test/arch/mep/ir/ut_helpers_ir.py index 9c9efdfa..c5bf36b9 100644 --- a/test/arch/mep/ir/ut_helpers_ir.py +++ b/test/arch/mep/ir/ut_helpers_ir.py @@ -1,16 +1,19 @@ # Toshiba MeP-c4 - unit tests helpers # Guillaume Valadon <guillaume@valadon.net> -from miasm2.arch.mep.arch import mn_mep -from miasm2.arch.mep.sem import ir_mepb -from miasm2.arch.mep.regs import regs_init +from __future__ import print_function -from miasm2.ir.symbexec import SymbolicExecutionEngine -from miasm2.core.locationdb import LocationDB -from miasm2.core.utils import Disasm_Exception -from miasm2.ir.ir import AssignBlock -from miasm2.arch.mep.ira import ir_a_mepb -from miasm2.expression.expression import ExprId, ExprInt, ExprOp, ExprMem, ExprAssign, ExprLoc +from miasm.arch.mep.arch import mn_mep +from miasm.arch.mep.sem import ir_mepb +from miasm.arch.mep.regs import regs_init + +from miasm.ir.symbexec import SymbolicExecutionEngine +from miasm.core.locationdb import LocationDB +from miasm.core.utils import Disasm_Exception +from miasm.ir.ir import AssignBlock +from miasm.arch.mep.ira import ir_a_mepb +from miasm.expression.expression import ExprId, ExprInt, ExprOp, ExprMem, \ + ExprAssign, ExprLoc def exec_instruction(mn_str, init_values, results, index=0, offset=0): @@ -67,8 +70,8 @@ def exec_instruction(mn_str, init_values, results, index=0, offset=0): # Ensure that all expected results were verified if len(results) is not matched_results: - print "Expected:", results - print "Modified:", [r for r in sb.modified(mems=False)] + print("Expected:", results) + print("Modified:", [r for r in sb.modified(mems=False)]) assert(False) @@ -78,10 +81,10 @@ def launch_tests(obj): test_methods = [name for name in dir(obj) if name.startswith("test")] for method in test_methods: - print method + print(method) try: getattr(obj, method)() except AttributeError as e: - print "Method not found: %s" % method + print("Method not found: %s" % method) assert(False) - print '-' * 42 + print('-' * 42) diff --git a/test/arch/mep/jit/test_jit_branchjump.py b/test/arch/mep/jit/test_jit_branchjump.py index baf602d8..1f932aa9 100644 --- a/test/arch/mep/jit/test_jit_branchjump.py +++ b/test/arch/mep/jit/test_jit_branchjump.py @@ -4,7 +4,7 @@ from ut_helpers_jit import jit_instructions -class TestBranchJump: +class TestBranchJump(object): def test_blti(self): """Test BLTI jit""" diff --git a/test/arch/mep/jit/test_jit_repeat.py b/test/arch/mep/jit/test_jit_repeat.py index 9fa64fa5..eaac1a1d 100644 --- a/test/arch/mep/jit/test_jit_repeat.py +++ b/test/arch/mep/jit/test_jit_repeat.py @@ -4,7 +4,7 @@ from ut_helpers_jit import jit_instructions -class TestRepeat: +class TestRepeat(object): def test_repeat(self): """Test REPEAT jit""" diff --git a/test/arch/mep/jit/ut_helpers_jit.py b/test/arch/mep/jit/ut_helpers_jit.py index 590c534f..0c756e39 100644 --- a/test/arch/mep/jit/ut_helpers_jit.py +++ b/test/arch/mep/jit/ut_helpers_jit.py @@ -1,19 +1,21 @@ # Toshiba MeP-c4 - unit tests helpers # Guillaume Valadon <guillaume@valadon.net> -from miasm2.analysis.machine import Machine -from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE +from __future__ import print_function + +from miasm.analysis.machine import Machine +from miasm.jitter.csts import PAGE_READ, PAGE_WRITE def jit_instructions(mn_str): """JIT instructions and return the jitter object.""" - # Get the miasm2 Machine + # Get the miasm Machine machine = Machine("mepb") mn_mep = machine.mn() # Assemble the instructions - asm = "" + asm = b"" for instr_str in mn_str.split("\n"): instr = mn_mep.fromstring(instr_str, "b") instr.mode = "b" @@ -40,10 +42,10 @@ def launch_tests(obj): test_methods = [name for name in dir(obj) if name.startswith("test")] for method in test_methods: - print method + print(method) try: getattr(obj, method)() except AttributeError as e: - print "Method not found: %s" % method + print("Method not found: %s" % method) assert(False) - print '-' * 42 + print('-' * 42) diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py index 1cbb554d..e5e8cff6 100644 --- a/test/arch/mips32/arch.py +++ b/test/arch/mips32/arch.py @@ -1,8 +1,10 @@ +from __future__ import print_function import time from pdb import pm -from miasm2.core.locationdb import LocationDB -from miasm2.arch.mips32.arch import * +from miasm.core.utils import decode_hex, encode_hex +from miasm.core.locationdb import LocationDB +from miasm.arch.mips32.arch import * loc_db = LocationDB() @@ -217,20 +219,20 @@ reg_tests_mips32 = [ ts = time.time() def h2i(s): - return s.replace(' ', '').decode('hex') + return decode_hex(s.replace(' ', '')) for s, l in reg_tests_mips32: - print "-" * 80 + print("-" * 80) s = s[12:] b = h2i((l)) mn = mn_mips32.dis(b, 'b') - print [str(x) for x in mn.args] - print s - print mn + print([str(x) for x in mn.args]) + print(s) + print(mn) assert(str(mn) == s) l = mn_mips32.fromstring(s, loc_db, 'b') assert(str(l) == s) a = mn_mips32.asm(l, 'b') - print [x for x in a] - print repr(b) + print([x for x in a]) + print(repr(b)) assert(b in a) diff --git a/test/arch/mips32/unit/asm_test.py b/test/arch/mips32/unit/asm_test.py index da792874..2dcaf6fc 100644 --- a/test/arch/mips32/unit/asm_test.py +++ b/test/arch/mips32/unit/asm_test.py @@ -1,13 +1,15 @@ import sys import os -from miasm2.arch.mips32.arch import mn_mips32 -from miasm2.core import parse_asm -from miasm2.expression.expression import * -from miasm2.core import asmblock -from elfesteem.strpatchwork import StrPatchwork -from miasm2.analysis.machine import Machine -from miasm2.jitter.csts import * +from future.utils import viewitems + +from miasm.arch.mips32.arch import mn_mips32 +from miasm.core import parse_asm +from miasm.expression.expression import * +from miasm.core import asmblock +from miasm.loader.strpatchwork import StrPatchwork +from miasm.analysis.machine import Machine +from miasm.jitter.csts import * reg_and_id = dict(mn_mips32.regs.all_regs_ids_byname) @@ -30,10 +32,10 @@ class Asm_Test(object): loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) s = StrPatchwork() patches = asmblock.asm_resolve_final(mn_mips32, blocks, loc_db) - for offset, raw in patches.items(): + for offset, raw in viewitems(patches): s[offset] = raw - s = str(s) + s = bytes(s) self.assembly = s def run(self): diff --git a/test/arch/msp430/arch.py b/test/arch/msp430/arch.py index 91de95b3..bc38c363 100644 --- a/test/arch/msp430/arch.py +++ b/test/arch/msp430/arch.py @@ -1,12 +1,15 @@ +from __future__ import print_function + import time from pdb import pm -from miasm2.arch.msp430.arch import * -from miasm2.core.locationdb import LocationDB +from miasm.core.utils import decode_hex, encode_hex +from miasm.arch.msp430.arch import * +from miasm.core.locationdb import LocationDB loc_db = LocationDB() def h2i(s): - return s.replace(' ', '').decode('hex') + return decode_hex(s.replace(' ', '')) def u16swap(i): @@ -86,18 +89,18 @@ reg_tests_msp = [ ts = time.time() for s, l in reg_tests_msp: - print "-" * 80 + print("-" * 80) s = s[8:] b = h2i((l)) - print repr(b) + print(repr(b)) mn = mn_msp430.dis(b, None) - print [str(x) for x in mn.args] - print s - print mn + print([str(x) for x in mn.args]) + print(s) + print(mn) assert(str(mn) == s) l = mn_msp430.fromstring(s, loc_db, None) assert(str(l) == s) a = mn_msp430.asm(l) - print [x for x in a] - print repr(b) + print([x for x in a]) + print(repr(b)) assert(b in a) diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py index 10e57e36..2aca66ed 100755 --- a/test/arch/msp430/sem.py +++ b/test/arch/msp430/sem.py @@ -1,15 +1,18 @@ #! /usr/bin/env python2 #-*- coding:utf-8 -*- +from __future__ import print_function import unittest import logging -from miasm2.ir.symbexec import SymbolicExecutionEngine -from miasm2.arch.msp430.arch import mn_msp430 as mn, mode_msp430 as mode -from miasm2.arch.msp430.sem import ir_msp430 as ir_arch -from miasm2.arch.msp430.regs import * -from miasm2.expression.expression import * -from miasm2.core.locationdb import LocationDB +from future.utils import viewitems + +from miasm.ir.symbexec import SymbolicExecutionEngine +from miasm.arch.msp430.arch import mn_msp430 as mn, mode_msp430 as mode +from miasm.arch.msp430.sem import ir_msp430 as ir_arch +from miasm.arch.msp430.regs import * +from miasm.expression.expression import * +from miasm.core.locationdb import LocationDB logging.getLogger('cpuhelper').setLevel(logging.ERROR) EXCLUDE_REGS = set([res, ir_arch().IRDst]) @@ -22,7 +25,7 @@ def M(addr): def compute(asm, inputstate={}, debug=False): loc_db = LocationDB() sympool = dict(regs_init) - sympool.update({k: ExprInt(v, k.size) for k, v in inputstate.iteritems()}) + sympool.update({k: ExprInt(v, k.size) for k, v in viewitems(inputstate)}) ir_tmp = ir_arch(loc_db) ircfg = ir_tmp.new_ircfg() symexec = SymbolicExecutionEngine(ir_tmp, sympool) @@ -33,11 +36,13 @@ def compute(asm, inputstate={}, debug=False): loc_key = ir_tmp.add_instr_to_ircfg(instr, ircfg) symexec.run_at(ircfg, loc_key) if debug: - for k, v in symexec.symbols.items(): + for k, v in viewitems(symexec.symbols): if regs_init.get(k, None) != v: - print k, v - return {k: v.arg.arg for k, v in symexec.symbols.items() - if k not in EXCLUDE_REGS and regs_init.get(k, None) != v} + print(k, v) + return { + k: v.arg.arg for k, v in viewitems(symexec.symbols) + if k not in EXCLUDE_REGS and regs_init.get(k, None) != v + } class TestMSP430Semantic(unittest.TestCase): diff --git a/test/arch/sh4/arch.py b/test/arch/sh4/arch.py index f744b215..0fbc6ba2 100644 --- a/test/arch/sh4/arch.py +++ b/test/arch/sh4/arch.py @@ -1,13 +1,15 @@ +from __future__ import print_function import time from pdb import pm from sys import stderr -from miasm2.arch.sh4.arch import * -from miasm2.core.locationdb import LocationDB +from miasm.core.utils import decode_hex, encode_hex +from miasm.arch.sh4.arch import * +from miasm.core.locationdb import LocationDB loc_db = LocationDB() def h2i(s): - return s.replace(' ', '').decode('hex') + return decode_hex(s.replace(' ', '')) reg_tests_sh4 = [ # vxworks @@ -389,25 +391,25 @@ reg_tests_sh4 = [ ] for s, l in reg_tests_sh4: - print "-" * 80 + print("-" * 80) s = s[12:] b = h2i((l)) - print b.encode('hex') + print(encode_hex(b)) mn = mn_sh4.dis(b, None) - print [str(x) for x in mn.args] - print s - print mn + print([str(x) for x in mn.args]) + print(s) + print(mn) assert(str(mn) == s) l = mn_sh4.fromstring(s, loc_db, None) assert(str(l) == s) a = mn_sh4.asm(l) - print [x for x in a] - print repr(b) + print([x for x in a]) + print(repr(b)) assert(b in a) # speed test -o = "" +o = b"" for s, l, in reg_tests_sh4: s = s[12:] b = h2i((l)) @@ -421,10 +423,10 @@ instr_num = 0 ts = time.time() while off < bs.getlen(): mn = mn_sh4.dis(bs, None, off) - print instr_num, off, mn.l, str(mn) + print(instr_num, off, mn.l, str(mn)) instr_num += 1 off += mn.l -print 'instr per sec:', instr_num / (time.time() - ts) +print('instr per sec:', instr_num // (time.time() - ts)) import cProfile -cProfile.run(r'mn_sh4.dis("\x17\xfe", None)') +cProfile.run(r'mn_sh4.dis(b"\x17\xfe", None)') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index d2204d77..202ecac5 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -1,11 +1,14 @@ +from __future__ import print_function import time from pdb import pm -import miasm2.expression.expression as m2_expr -from miasm2.arch.x86.arch import mn_x86, deref_mem_ad, \ + +from miasm.core.utils import decode_hex, encode_hex +import miasm.expression.expression as m2_expr +from miasm.arch.x86.arch import mn_x86, deref_mem_ad, \ base_expr, rmarg, print_size -from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 -from miasm2.core.bin_stream import bin_stream_str -from miasm2.core.locationdb import LocationDB +from miasm.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 +from miasm.core.bin_stream import bin_stream_str +from miasm.core.locationdb import LocationDB loc_db = LocationDB() @@ -22,7 +25,7 @@ reg_and_id.update({'mylabel16': mylabel16, def h2i(s): - return int(s.replace(' ', '').decode('hex')[::].encode('hex'), 16) + return int(encode_hex(decode_hex(s.replace(' ', ''))[::]), 16) m16 = 16 # (16, 16) @@ -3101,56 +3104,58 @@ reg_tests = [ ] -test_file = {16: open('regression_test16_ia32.bin', 'w'), - 32: open('regression_test32_ia32.bin', 'w'), - 64: open('regression_test64_ia32.bin', 'w')} +test_file = { + 16: open('regression_test16_ia32.bin', 'wb'), + 32: open('regression_test32_ia32.bin', 'wb'), + 64: open('regression_test64_ia32.bin', 'wb') +} ts = time.time() for mode, s, l, in reg_tests: - print "-" * 80 + print("-" * 80) s = s[12:] - b = l.decode('hex') - print mode, repr(b) + b = decode_hex(l) + print(mode, repr(b)) mn = mn_x86.dis(b, mode) - print "dis args", [(str(x), x.size) for x in mn.args] - print s - print mn + print("dis args", [(str(x), x.size) for x in mn.args]) + print(s) + print(mn) assert(str(mn).strip() == s) - print 'fromstring', repr(s) + print('fromstring', repr(s)) l = mn_x86.fromstring(s, loc_db, mode) - print 'str args', [(str(x), x.size) for x in l.args] + print('str args', [(str(x), x.size) for x in l.args]) assert(str(l).strip(' ') == s) a = mn_x86.asm(l) - print 'asm result', [x for x in a] - print repr(b) + print('asm result', [x for x in a]) + print(repr(b)) for x in a: - print "BYTES", repr(x) + print("BYTES", repr(x)) test_file[mode].write(x) - test_file[mode].write("\x90" * 2) + test_file[mode].write(b"\x90" * 2) - print 'test re dis' + print('test re dis') for x in a: - print repr(x) + print(repr(x)) rl = mn_x86.dis(x, mode) assert(str(rl).strip(' ') == s) - print repr(b), a + print(repr(b), a) assert(b in a) -print 'TEST time', time.time() - ts +print('TEST time', time.time() - ts) # speed test thumb -o = "" +o = b"" mode_x = m32 for mode, s, l, in reg_tests: if mode != mode_x: continue s = s[12:] - b = l.decode('hex') + b = decode_hex(l) o += b while len(o) < 1000: o += o -open('x86_speed_reg_test.bin', 'w').write(o) +open('x86_speed_reg_test.bin', 'wb').write(o) def profile_dis(o): @@ -3163,12 +3168,12 @@ def profile_dis(o): # print instr_num, off, mn.l, str(mn) instr_num += 1 off += mn.l - print 'instr per sec:', instr_num / (time.time() - ts) + print('instr per sec:', instr_num // (time.time() - ts)) import cProfile cProfile.run('profile_dis(o)') # Test instruction representation with prefix -instr_bytes = '\x65\xc7\x00\x09\x00\x00\x00' +instr_bytes = b'\x65\xc7\x00\x09\x00\x00\x00' inst = mn_x86.dis(instr_bytes, 32, 0) assert(inst.b == instr_bytes) diff --git a/test/arch/x86/qemu/testqemu.py b/test/arch/x86/qemu/testqemu.py index dccd9c83..99d6e6c1 100644 --- a/test/arch/x86/qemu/testqemu.py +++ b/test/arch/x86/qemu/testqemu.py @@ -1,36 +1,42 @@ +from __future__ import print_function import os -import sys import struct import logging +from sys import stdout from pdb import pm -from miasm2.analysis.sandbox import Sandbox_Linux_x86_32 -from miasm2.jitter.jitload import log_func -from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE +try: + stdout = stdout.buffer +except AttributeError: + pass + +from miasm.analysis.sandbox import Sandbox_Linux_x86_32 +from miasm.jitter.jitload import log_func +from miasm.jitter.csts import PAGE_READ, PAGE_WRITE # Utils def parse_fmt(s): - fmt = s[:]+"\x00" + fmt = s[:]+b"\x00" out = [] i = 0 while i < len(fmt): - c = fmt[i] - if c != "%": + c = fmt[i:i+1] + if c != b"%": i+=1 continue - if fmt[i+1] == "%": + if fmt[i+1:i+2] == b"%": i+=2 continue j = 0 i+=1 - while fmt[i+j] in "0123456789$.-": + while fmt[i+j:i+j+1] in b"0123456789$.-": j+=1 - if fmt[i+j] in ['l']: + if fmt[i+j:i+j+1] in [b'l']: j +=1 - if fmt[i+j] == "h": + if fmt[i+j:i+j+1] == b"h": x = fmt[i+j:i+j+2] else: - x = fmt[i+j] + x = fmt[i+j:i+j+1] i+=j out.append(x) return out @@ -44,25 +50,24 @@ def xxx___printf_chk(jitter): raise RuntimeError("Not implemented") fmt = jitter.get_str_ansi(args.format) # Manage llx - fmt = fmt.replace("llx", "lx") - fmt = fmt.replace("%016lx", "%016z") + fmt = fmt.replace(b"llx", b"lx") + fmt = fmt.replace(b"%016lx", b"%016z") fmt_a = parse_fmt(fmt) esp = jitter.cpu.ESP args = [] i = 0 - for x in fmt_a: a = jitter.vm.get_u32(esp + 8 + 4*i) - if x == "s": + if x == b"s": a = jitter.get_str_ansi(a) - elif x.lower() in ("x", 'd'): + elif x in (b"x", b'X', b"d"): pass - elif x.lower() in ("f", "l"): + elif x.lower() in (b"f", b"l"): a2 = jitter.vm.get_u32(esp + 8 + 4*(i+1)) a = struct.unpack("d", struct.pack("Q", a2 << 32 | a))[0] i += 1 - elif x.lower() == 'z': + elif x.lower() == b'z': a2 = jitter.vm.get_u32(esp + 8 + 4*(i+1)) a = a2 << 32 | a i += 1 @@ -70,23 +75,22 @@ def xxx___printf_chk(jitter): raise RuntimeError("Not implemented format") args.append(a) i += 1 - - fmt = fmt.replace("%016z", "%016lx") + fmt = fmt.replace(b"%016z", b"%016lx") output = fmt%(tuple(args)) # NaN bad repr in Python - output = output.replace("nan", "-nan") + output = output.replace(b"nan", b"-nan") - if "\n" not in output: + if b"\n" not in output: raise RuntimeError("Format must end with a \\n") # Check with expected result - line = expected.next() - if output != line: - print "Expected:", line - print "Obtained:", output + line = next(expected) + if output != line.encode(): + print("Expected:", line) + print("Obtained:", output) raise RuntimeError("Bad semantic") - sys.stdout.write("[%d] %s" % (nb_tests, output)) + stdout.write(b"[%d] %s" % (nb_tests, output)) nb_tests += 1 jitter.func_ret_systemv(ret_ad, 0) @@ -100,10 +104,10 @@ def xxx_puts(jitter): ret_addr, args = jitter.func_args_systemv(['target']) output = jitter.get_str_ansi(args.target) # Check with expected result - line = expected.next() - if output != line.rstrip(): - print "Expected:", line - print "Obtained:", output + line = next(expected) + if output != line.rstrip().encode(): + print("Expected:", line) + print("Obtained:", output) raise RuntimeError("Bad semantic") return jitter.func_ret_systemv(ret_addr, 1) @@ -120,7 +124,7 @@ expected = open(options.expected) # Create sandbox sb = Sandbox_Linux_x86_32(options.filename, options, globals()) try: - addr = sb.elf.getsectionbyname(".symtab").symbols[options.funcname].value + addr = sb.elf.getsectionbyname(".symtab")[options.funcname].value except AttributeError: raise RuntimeError("The target binary must have a symtab section") @@ -129,7 +133,7 @@ log_func.setLevel(logging.ERROR) # Segmentation sb.jitter.cpu.set_segm_base(8, 0x7fff0000) sb.jitter.cpu.GS = 8 -sb.jitter.vm.add_memory_page(0x7fff0000 + 0x14, PAGE_READ | PAGE_WRITE, "AAAA") +sb.jitter.vm.add_memory_page(0x7fff0000 + 0x14, PAGE_READ | PAGE_WRITE, b"AAAA") # Run diff --git a/test/arch/x86/qemu/testqemu64.py b/test/arch/x86/qemu/testqemu64.py index bd82d414..24193d40 100644 --- a/test/arch/x86/qemu/testqemu64.py +++ b/test/arch/x86/qemu/testqemu64.py @@ -1,36 +1,42 @@ +from __future__ import print_function import os -import sys import struct import logging +from sys import stdout from pdb import pm -from miasm2.analysis.sandbox import Sandbox_Linux_x86_64 -from miasm2.jitter.jitload import log_func -from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE +try: + stdout = stdout.buffer +except AttributeError: + pass + +from miasm.analysis.sandbox import Sandbox_Linux_x86_64 +from miasm.jitter.jitload import log_func +from miasm.jitter.csts import PAGE_READ, PAGE_WRITE # Utils def parse_fmt(s): - fmt = s[:]+"\x00" + fmt = s[:]+b"\x00" out = [] i = 0 while i < len(fmt): - c = fmt[i] - if c != "%": + c = fmt[i:i+1] + if c != b"%": i+=1 continue - if fmt[i+1] == "%": + if fmt[i+1:i+2] == b"%": i+=2 continue j = 0 i+=1 - while fmt[i+j] in "0123456789$.-": + while fmt[i+j:i+j+1] in b"0123456789$.-": j+=1 - if fmt[i+j] in ['l']: + if fmt[i+j:i+j+1] in [b'l']: j +=1 - if fmt[i+j] == "h": + if fmt[i+j:i+j+1] == b"h": x = fmt[i+j:i+j+2] else: - x = fmt[i+j] + x = fmt[i+j:i+j+1] i+=j out.append(x) return out @@ -44,8 +50,8 @@ def xxx___printf_chk(jitter): raise RuntimeError("Not implemented") fmt = jitter.get_str_ansi(args.format) # Manage llx - fmt = fmt.replace("llx", "lx") - fmt = fmt.replace("%016lx", "%016z") + fmt = fmt.replace(b"llx", b"lx") + fmt = fmt.replace(b"%016lx", b"%016z") fmt_a = parse_fmt(fmt) args = [] @@ -53,11 +59,11 @@ def xxx___printf_chk(jitter): for x in fmt_a: a = jitter.get_arg_n_systemv(2 + i) - if x == "s": + if x == b"s": a = jitter.get_str_ansi(a) - elif x.lower() in ("x", 'd', 'z'): + elif x in (b"x", b'X', b'd', b'z', b'Z'): pass - elif x.lower() in ("f", "l"): + elif x.lower() in (b"f","l"): a = struct.unpack("d", struct.pack("Q", a))[0] i += 1 else: @@ -65,22 +71,22 @@ def xxx___printf_chk(jitter): args.append(a) i += 1 - fmt = fmt.replace("%016z", "%016lx") + fmt = fmt.replace(b"%016z", b"%016lx") output = fmt%(tuple(args)) # NaN bad repr in Python - output = output.replace("nan", "-nan") + output = output.replace(b"nan", b"-nan") - if "\n" not in output: + if b"\n" not in output: raise RuntimeError("Format must end with a \\n") # Check with expected result - line = expected.next() - if output != line: - print "Expected:", line - print "Obtained:", output + line = next(expected) + if output != line.encode(): + print("Expected:", line) + print("Obtained:", output) raise RuntimeError("Bad semantic") - sys.stdout.write("[%d] %s" % (nb_tests, output)) + stdout.write(b"[%d] %s" % (nb_tests, output)) nb_tests += 1 jitter.func_ret_systemv(ret_ad, 0) @@ -94,10 +100,10 @@ def xxx_puts(jitter): ret_addr, args = jitter.func_args_systemv(['target']) output = jitter.get_str_ansi(args.target) # Check with expected result - line = expected.next() + line = next(expected) if output != line.rstrip(): - print "Expected:", line - print "Obtained:", output + print("Expected:", line) + print("Obtained:", output) raise RuntimeError("Bad semantic") return jitter.func_ret_systemv(ret_addr, 1) @@ -114,7 +120,7 @@ expected = open(options.expected) # Create sandbox sb = Sandbox_Linux_x86_64(options.filename, options, globals()) try: - addr = sb.elf.getsectionbyname(".symtab").symbols[options.funcname].value + addr = sb.elf.getsectionbyname(".symtab")[options.funcname].value except AttributeError: raise RuntimeError("The target binary must have a symtab section") @@ -123,7 +129,7 @@ log_func.setLevel(logging.ERROR) # Segmentation sb.jitter.cpu.set_segm_base(8, 0x7fff0000) sb.jitter.cpu.FS = 8 -sb.jitter.vm.add_memory_page(0x7fff0000 + 0x28, PAGE_READ | PAGE_WRITE, "AAAAAAAA") +sb.jitter.vm.add_memory_page(0x7fff0000 + 0x28, PAGE_READ | PAGE_WRITE, b"AAAAAAAA") # Run diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index 0783089d..5109d2b4 100755 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -3,18 +3,23 @@ # Loosely based on ARM's sem.py +from __future__ import print_function +from builtins import range + +from future.utils import viewitems + import unittest import logging import copy -from miasm2.ir.symbexec import SymbolicExecutionEngine -from miasm2.arch.x86.arch import mn_x86 as mn -from miasm2.arch.x86.sem import ir_x86_32 as ir_32, ir_x86_64 as ir_64 -from miasm2.arch.x86.regs import * -from miasm2.expression.expression import * -from miasm2.expression.simplifications import expr_simp -from miasm2.core import parse_asm, asmblock -from miasm2.core.locationdb import LocationDB +from miasm.ir.symbexec import SymbolicExecutionEngine +from miasm.arch.x86.arch import mn_x86 as mn +from miasm.arch.x86.sem import ir_x86_32 as ir_32, ir_x86_64 as ir_64 +from miasm.arch.x86.regs import * +from miasm.expression.expression import * +from miasm.expression.simplifications import expr_simp +from miasm.core import parse_asm, asmblock +from miasm.core.locationdb import LocationDB logging.getLogger('cpuhelper').setLevel(logging.ERROR) @@ -30,11 +35,13 @@ def symb_exec(lbl, ir_arch, ircfg, inputstate, debug): symexec = SymbolicExecutionEngine(ir_arch, sympool) symexec.run_at(ircfg, lbl) if debug: - for k, v in symexec.symbols.items(): + for k, v in viewitems(symexec.symbols): if regs_init.get(k, None) != v: - print k, v - return {k: v for k, v in symexec.symbols.items() - if k not in EXCLUDE_REGS and regs_init.get(k, None) != v} + print(k, v) + return { + k: v for k, v in viewitems(symexec.symbols) + if k not in EXCLUDE_REGS and regs_init.get(k, None) != v + } def compute(ir, mode, asm, inputstate={}, debug=False): loc_db = LocationDB() @@ -60,7 +67,7 @@ def compute_txt(ir, mode, txt, inputstate={}, debug=False): op_add = lambda a, b: a+b op_sub = lambda a, b: a-b op_mul = lambda a, b: a*b -op_div = lambda a, b: a/b +op_div = lambda a, b: a //b op_and = lambda a, b: a&b op_or = lambda a, b: a|b @@ -72,8 +79,8 @@ def int_vec_op(op, elt_size, reg_size, arg1, arg2): assert(reg_size % elt_size == 0) ret = 0 mask = (1<<elt_size)-1 - nelts = reg_size/elt_size - for i in xrange(0, nelts): + nelts = reg_size // elt_size + for i in range(0, nelts): ret |= (op(arg1 & mask, arg2 & mask) & mask) << (i*elt_size) arg1 >>= elt_size arg2 >>= elt_size diff --git a/test/arch/x86/unit/access_xmm.py b/test/arch/x86/unit/access_xmm.py index 950c8b56..65248b2e 100644 --- a/test/arch/x86/unit/access_xmm.py +++ b/test/arch/x86/unit/access_xmm.py @@ -1,7 +1,7 @@ #! /usr/bin/env python2 """Test getter and setter for XMM registers (128 bits)""" -from miasm2.analysis.machine import Machine +from miasm.analysis.machine import Machine # Jitter engine doesn't matter, use the always available 'python' one myjit = Machine("x86_32").jitter("python") @@ -10,7 +10,7 @@ myjit = Machine("x86_32").jitter("python") assert myjit.cpu.XMM0 == 0 # Test set -myjit.cpu.XMM1 = 0x00112233445566778899aabbccddeeffL +myjit.cpu.XMM1 = 0x00112233445566778899aabbccddeeff # Ensure set has been correctly handled -assert myjit.cpu.XMM1 == 0x00112233445566778899aabbccddeeffL +assert myjit.cpu.XMM1 == 0x00112233445566778899aabbccddeeff diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index 91da1942..6e7c55e2 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -1,13 +1,17 @@ +from builtins import str +from builtins import object import sys import os -from miasm2.arch.x86.arch import mn_x86, base_expr, variable -from miasm2.core import parse_asm -from miasm2.expression.expression import * -from miasm2.core import asmblock -from elfesteem.strpatchwork import StrPatchwork -from miasm2.analysis.machine import Machine -from miasm2.jitter.csts import * +from future.utils import viewitems + +from miasm.arch.x86.arch import mn_x86, base_expr, variable +from miasm.core import parse_asm +from miasm.expression.expression import * +from miasm.core import asmblock +from miasm.loader.strpatchwork import StrPatchwork +from miasm.analysis.machine import Machine +from miasm.jitter.csts import * reg_and_id = dict(mn_x86.regs.all_regs_ids_byname) @@ -46,10 +50,10 @@ class Asm_Test(object): loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) s = StrPatchwork() patches = asmblock.asm_resolve_final(mn_x86, blocks, loc_db) - for offset, raw in patches.items(): + for offset, raw in viewitems(patches): s[offset] = raw - s = str(s) + s = bytes(s) self.assembly = s def check(self): diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py index 947b40bb..d015ede9 100644 --- a/test/arch/x86/unit/mn_cdq.py +++ b/test/arch/x86/unit/mn_cdq.py @@ -3,7 +3,7 @@ import sys from asm_test import Asm_Test_16, Asm_Test_32, Asm_Test_64 -from miasm2.core.utils import pck16, pck32 +from miasm.core.utils import pck16, pck32 class Test_CBW_16(Asm_Test_16): diff --git a/test/arch/x86/unit/mn_getset128.py b/test/arch/x86/unit/mn_getset128.py index a084d663..f20f452e 100644 --- a/test/arch/x86/unit/mn_getset128.py +++ b/test/arch/x86/unit/mn_getset128.py @@ -35,15 +35,15 @@ class Test_get_set_128(Asm_Test_32): assert self.myjit.cpu.get_gpreg()['XMM0'] == val def check(self): - assert self.myjit.cpu.XMM0 == 0xffffffffffffffff0000000000000000L + assert self.myjit.cpu.XMM0 == 0xffffffffffffffff0000000000000000 assert self.myjit.cpu.XMM1 == 0x11223345 # Check 128 get / set - assert self.myjit.cpu.get_gpreg()['XMM0'] == 0xffffffffffffffff0000000000000000L + assert self.myjit.cpu.get_gpreg()['XMM0'] == 0xffffffffffffffff0000000000000000 assert self.myjit.cpu.get_gpreg()['XMM1'] == 0x11223345 - assert self.myjit.cpu.get_gpreg()['XMM2'] == 0x11112222333344445555666677778888L - assert self.myjit.cpu.get_gpreg()['XMM2'] == 0x11112222333344445555666677778888L + assert self.myjit.cpu.get_gpreg()['XMM2'] == 0x11112222333344445555666677778888 + assert self.myjit.cpu.get_gpreg()['XMM2'] == 0x11112222333344445555666677778888 if __name__ == "__main__": diff --git a/test/arch/x86/unit/mn_int.py b/test/arch/x86/unit/mn_int.py index efacb105..8cb8080f 100755 --- a/test/arch/x86/unit/mn_int.py +++ b/test/arch/x86/unit/mn_int.py @@ -1,7 +1,7 @@ #! /usr/bin/env python2 import sys -from miasm2.jitter.csts import EXCEPT_INT_XX +from miasm.jitter.csts import EXCEPT_INT_XX from asm_test import Asm_Test_32 diff --git a/test/arch/x86/unit/mn_pcmpeq.py b/test/arch/x86/unit/mn_pcmpeq.py index e934d6b5..b8eeafba 100755 --- a/test/arch/x86/unit/mn_pcmpeq.py +++ b/test/arch/x86/unit/mn_pcmpeq.py @@ -81,7 +81,7 @@ class Test_PCMPEQQ(Asm_Test_32): self.myjit.cpu.XMM0 = val def check(self): - assert self.myjit.cpu.XMM0 == 0xffffffffffffffff0000000000000000L + assert self.myjit.cpu.XMM0 == 0xffffffffffffffff0000000000000000 assert self.myjit.cpu.XMM1 == 0x11223345 diff --git a/test/arch/x86/unit/mn_pshufb.py b/test/arch/x86/unit/mn_pshufb.py index d10c18e3..9167b0c1 100755 --- a/test/arch/x86/unit/mn_pshufb.py +++ b/test/arch/x86/unit/mn_pshufb.py @@ -18,8 +18,8 @@ class Test_PSHUFB(Asm_Test_32): ''' def check(self): - assert self.myjit.cpu.MM0 == 0x1122334455667788L - assert self.myjit.cpu.MM1 == 0x8877665544332211L + assert self.myjit.cpu.MM0 == 0x1122334455667788 + assert self.myjit.cpu.MM1 == 0x8877665544332211 if __name__ == "__main__": diff --git a/test/arch/x86/unit/mn_psrl_psll.py b/test/arch/x86/unit/mn_psrl_psll.py index a5428dab..7d9572b0 100755 --- a/test/arch/x86/unit/mn_psrl_psll.py +++ b/test/arch/x86/unit/mn_psrl_psll.py @@ -22,10 +22,10 @@ class Test_PSRL(Asm_Test_32): ''' def check(self): - assert self.myjit.cpu.MM0 == 0x1122334455667788L - assert self.myjit.cpu.MM1 == 0x0112033405560778L - assert self.myjit.cpu.MM2 == 0x0112233405566778L - assert self.myjit.cpu.MM3 == 0x0112233445566778L + assert self.myjit.cpu.MM0 == 0x1122334455667788 + assert self.myjit.cpu.MM1 == 0x0112033405560778 + assert self.myjit.cpu.MM2 == 0x0112233405566778 + assert self.myjit.cpu.MM3 == 0x0112233445566778 class Test_PSLL(Asm_Test_32): TXT = ''' @@ -46,10 +46,10 @@ class Test_PSLL(Asm_Test_32): ''' def check(self): - assert self.myjit.cpu.MM0 == 0x1122334455667788L - assert self.myjit.cpu.MM1 == 0x1220344056607880L - assert self.myjit.cpu.MM2 == 0x1223344056677880L - assert self.myjit.cpu.MM3 == 0x1223344556677880L + assert self.myjit.cpu.MM0 == 0x1122334455667788 + assert self.myjit.cpu.MM1 == 0x1220344056607880 + assert self.myjit.cpu.MM2 == 0x1223344056677880 + assert self.myjit.cpu.MM3 == 0x1223344556677880 if __name__ == "__main__": diff --git a/test/arch/x86/unit/mn_pushpop.py b/test/arch/x86/unit/mn_pushpop.py index 6e9005ca..6dc37b74 100755 --- a/test/arch/x86/unit/mn_pushpop.py +++ b/test/arch/x86/unit/mn_pushpop.py @@ -3,7 +3,7 @@ import sys from asm_test import Asm_Test_16, Asm_Test_32 -from miasm2.core.utils import pck16, pck32 +from miasm.core.utils import pck16, pck32 def init_regs(test): @@ -25,7 +25,7 @@ class Test_PUSHAD_32(Asm_Test_32): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" for reg_name in reversed(["EAX", "ECX", "EDX", "EBX", "ESP", "EBP", @@ -52,7 +52,7 @@ class Test_PUSHA_32(Asm_Test_32): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" for reg_name in reversed(["AX", "CX", "DX", "BX", "SP", "BP", @@ -79,7 +79,7 @@ class Test_PUSHA_16(Asm_Test_16): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" for reg_name in reversed(["AX", "CX", "DX", "BX", "SP", "BP", @@ -106,7 +106,7 @@ class Test_PUSHAD_16(Asm_Test_16): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" for reg_name in reversed(["EAX", "ECX", "EDX", "EBX", "ESP", "EBP", @@ -133,7 +133,7 @@ class Test_PUSH_mode32_32(Asm_Test_32): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" self.buf += pck32(0x11223344) TXT = ''' @@ -156,7 +156,7 @@ class Test_PUSH_mode32_16(Asm_Test_32): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" self.buf += pck16(0x1122) TXT = ''' @@ -179,7 +179,7 @@ class Test_PUSH_mode16_16(Asm_Test_16): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" self.buf += pck16(0x1122) TXT = ''' @@ -202,7 +202,7 @@ class Test_PUSH_mode16_32(Asm_Test_16): def test_init(self): init_regs(self) - self.buf = "" + self.buf = b"" self.buf += pck32(0x11223344) TXT = ''' diff --git a/test/arch/x86/unit/mn_seh.py b/test/arch/x86/unit/mn_seh.py index dd3fd4ef..8575cc46 100755 --- a/test/arch/x86/unit/mn_seh.py +++ b/test/arch/x86/unit/mn_seh.py @@ -1,10 +1,11 @@ #! /usr/bin/env python2 +from __future__ import print_function import sys -from miasm2.os_dep.win_api_x86_32_seh import fake_seh_handler, build_teb, \ +from miasm.os_dep.win_api_x86_32_seh import fake_seh_handler, build_teb, \ set_win_fs_0, return_from_exception, EXCEPTION_PRIV_INSTRUCTION, \ return_from_seh, DEFAULT_SEH -from miasm2.os_dep.win_32_structs import ContextException +from miasm.os_dep.win_32_structs import ContextException from asm_test import Asm_Test_32 @@ -15,7 +16,7 @@ class Test_SEH(Asm_Test_32): @staticmethod def deal_exception_priv(jitter): - print 'Exception Priv', hex(jitter.cpu.ESP) + print('Exception Priv', hex(jitter.cpu.ESP)) pc = fake_seh_handler(jitter, EXCEPTION_PRIV_INSTRUCTION) jitter.pc = pc jitter.cpu.EIP = pc diff --git a/test/arch/x86/unit/test_asm_x86_64.py b/test/arch/x86/unit/test_asm_x86_64.py index 4e600846..e23f9a19 100644 --- a/test/arch/x86/unit/test_asm_x86_64.py +++ b/test/arch/x86/unit/test_asm_x86_64.py @@ -1,7 +1,7 @@ -from miasm2.core import asmblock -from miasm2.arch.x86 import arch -from miasm2.core import parse_asm -from miasm2.core.interval import interval +from miasm.core import asmblock +from miasm.arch.x86 import arch +from miasm.core import parse_asm +from miasm.core.interval import interval my_mn = arch.mn_x86 |