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-rw-r--r--test/arch/x86/arch.py115
-rw-r--r--test/arch/x86/unit/mn_cdq.py445
2 files changed, 556 insertions, 4 deletions
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py
index d3b2964c..2af90c8a 100644
--- a/test/arch/x86/arch.py
+++ b/test/arch/x86/arch.py
@@ -2902,11 +2902,11 @@ reg_tests = [
     (m32, "00000000    PEXTRW     WORD PTR [EDX], XMM2, 0x5",
     "660F3A151205"),
 
+    (m32, "00000000    PEXTRW     EAX, MM2, 0x5",
+    "0fc5c205"),
+    (m32, "00000000    PEXTRW     EAX, XMM2, 0x5",
+    "660fc5c205"),
 
-    (m32, "00000000    PEXTRW     WORD PTR [EDX], MM2, 0x5",
-    "0FC51205"),
-    (m32, "00000000    PEXTRW     WORD PTR [EDX], XMM2, 0x5",
-    "660FC51205"),
 
     (m32, "00000000    PEXTRD     DWORD PTR [EDX], XMM2, 0x5",
     "660F3A161205"),
@@ -2970,6 +2970,113 @@ reg_tests = [
     (m64, "00000000    BNDMOV     BND3, XMMWORD PTR [RSP + 0xB0]",
      "660f1a9c24b0000000"),
 
+    (m32, "00000000    PACKSSWB   MM7, MM0",
+     "0f63f8"),
+    (m32, "00000000    PACKSSWB   XMM0, XMM5",
+     "660f63c5"),
+
+    (m32, "00000000    PACKSSDW   MM2, MM0",
+     "0f6bd0"),
+    (m32, "00000000    PACKSSDW   XMM0, XMM7",
+     "660f6bc7"),
+
+    (m32, "00000000    PACKUSWB   MM1, MM7",
+     "0f67cf"),
+    (m32, "00000000    PACKUSWB   XMM0, XMM6",
+     "660f67c6"),
+
+    (m32, "00000000    PMULLW     MM4, MM2",
+     "0fd5e2"),
+    (m32, "00000000    PMULLW     XMM0, XMM3",
+     "660fd5c3"),
+
+    (m32, "00000000    PSUBUSB    MM5, MM3",
+     "0fd8eb"),
+    (m32, "00000000    PSUBUSB    XMM0, XMM5",
+     "660fd8c5"),
+
+    (m32, "00000000    PSUBUSW    MM5, MM3",
+     "0fd9eb"),
+    (m32, "00000000    PSUBUSW    XMM0, XMM5",
+     "660fd9c5"),
+
+    (m32, "00000000    PADDUSB    MM5, MM3",
+     "0fdceb"),
+    (m32, "00000000    PADDUSB    XMM0, XMM6",
+     "660fdcc6"),
+
+    (m32, "00000000    PADDUSW    MM7, MM5",
+     "0fddfd"),
+    (m32, "00000000    PADDUSW    XMM0, XMM1",
+     "660fddc1"),
+
+    (m32, "00000000    PMULHUW    MM6, MM4",
+     "0fe4f4"),
+    (m32, "00000000    PMULHUW    XMM0, XMM7",
+     "660fe4c7"),
+
+    (m32, "00000000    PMULHW     MM6, MM4",
+     "0fe5f4"),
+    (m32, "00000000    PMULHW     XMM0, XMM7",
+     "660fe5c7"),
+
+    (m32, "00000000    PSUBSB     MM2, MM0",
+     "0fe8d0"),
+    (m32, "00000000    PSUBSB     XMM0, XMM4",
+     "660fe8c4"),
+
+    (m32, "00000000    PSUBSW     MM3, MM1",
+     "0fe9d9"),
+    (m32, "00000000    PSUBSW     XMM0, XMM6",
+     "660fe9c6"),
+
+    (m32, "00000000    PADDSB     MM2, MM0",
+     "0fecd0"),
+    (m32, "00000000    PADDSB     XMM0, XMM4",
+     "660fecc4"),
+
+    (m32, "00000000    PADDSW     MM3, MM1",
+     "0fedd9"),
+    (m32, "00000000    PADDSW     XMM0, XMM6",
+     "660fedc6"),
+
+    (m32, "00000000    PMAXSW     MM3, MM1",
+     "0feed9"),
+    (m32, "00000000    PMAXSW     XMM0, XMM6",
+     "660feec6"),
+
+    (m32, "00000000    PMULUDQ    MM3, MM1",
+     "0ff4d9"),
+    (m32, "00000000    PMULUDQ    XMM0, XMM6",
+     "660ff4c6"),
+
+    (m32, "00000000    PMADDWD    MM3, MM1",
+     "0ff5d9"),
+    (m32, "00000000    PMADDWD    XMM0, XMM6",
+     "660ff5c6"),
+
+    (m32, "00000000    PSADBW     MM3, MM1",
+     "0ff6d9"),
+    (m32, "00000000    PSADBW     XMM0, XMM6",
+     "660ff6c6"),
+
+    (m32, "00000000    PAVGB      MM3, MM1",
+     "0fe0d9"),
+    (m32, "00000000    PAVGB      XMM0, XMM6",
+     "660fe0c6"),
+
+    (m32, "00000000    PAVGW      MM3, MM1",
+     "0fe3d9"),
+    (m32, "00000000    PAVGW      XMM0, XMM6",
+     "660fe3c6"),
+
+    (m32, "00000000    MASKMOVQ   MM2, MM3",
+     "0ff7d3"),
+    (m32, "00000000    MASKMOVDQU XMM4, XMM5",
+     "660ff7e5"),
+
+    (m32, "00000000    EMMS",
+     "0f77"),
 ]
 
 
diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py
new file mode 100644
index 00000000..f4e4d6e7
--- /dev/null
+++ b/test/arch/x86/unit/mn_cdq.py
@@ -0,0 +1,445 @@
+#! /usr/bin/env python2
+
+import sys
+
+from asm_test import Asm_Test_16, Asm_Test_32, Asm_Test_64
+from miasm2.core.utils import pck16, pck32
+
+
+class Test_CBW_16(Asm_Test_16):
+    MYSTRING = "test CBW 16"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87650021
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_16_signed(Asm_Test_16):
+    MYSTRING = "test CBW 16 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654381
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x8765FF81
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_32(Asm_Test_32):
+    MYSTRING = "test CBW 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87650021
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_32_signed(Asm_Test_32):
+    MYSTRING = "test CBW 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654381
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x8765FF81
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CDQ_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x77654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x77654321
+        assert self.myjit.cpu.EDX == 0x0
+
+
+class Test_CDQ_32_signed(Asm_Test_32):
+    MYSTRING = "test cdq 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87654321
+        assert self.myjit.cpu.EDX == 0xFFFFFFFF
+
+
+class Test_CDQ_64(Asm_Test_64):
+    MYSTRING = "test cdq 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567877654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567877654321
+        assert self.myjit.cpu.RDX == 0x0
+
+
+class Test_CDQ_64_signed(Asm_Test_64):
+    MYSTRING = "test cdq 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567887654321
+        assert self.myjit.cpu.RDX == 0x00000000FFFFFFFF
+
+
+class Test_CDQE_64(Asm_Test_64):
+    MYSTRING = "test cdq 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567877654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x77654321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CDQE_64_signed(Asm_Test_64):
+    MYSTRING = "test cdq 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0xFFFFFFFF87654321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CWD_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87654321
+        assert self.myjit.cpu.RDX == 0x12340000
+
+
+class Test_CWD_32_signed(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87658321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87658321
+        assert self.myjit.cpu.RDX == 0x1234FFFF
+
+
+class Test_CWD_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87654321
+        assert self.myjit.cpu.RDX == 0x12340000
+
+
+class Test_CWDE_32(Asm_Test_32):
+    MYSTRING = "test cwde 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x4321
+        assert self.myjit.cpu.RDX == 0x11223344
+
+
+class Test_CWDE_32_signed(Asm_Test_32):
+    MYSTRING = "test cwde 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x87658321
+        self.myjit.cpu.RDX = 0x11223344
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0xFFFF8321
+        assert self.myjit.cpu.RDX == 0x11223344
+
+
+class Test_CWDE_64(Asm_Test_64):
+    MYSTRING = "test cwde 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x4321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CWDE_64_signed(Asm_Test_64):
+    MYSTRING = "test cwde 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887658321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0xFFFF8321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CQO_64(Asm_Test_64):
+    MYSTRING = "test cwde 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CQO
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567887654321
+        assert self.myjit.cpu.RDX == 0x0
+
+
+class Test_CQO_64_signed(Asm_Test_64):
+    MYSTRING = "test cwde 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x8234567887658321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CQO
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x8234567887658321
+        assert self.myjit.cpu.RDX == 0xFFFFFFFFFFFFFFFF
+
+
+
+
+if __name__ == "__main__":
+    tests = [
+        Test_CBW_16,
+        Test_CBW_16_signed,
+
+        Test_CBW_32,
+        Test_CBW_32_signed,
+
+        Test_CWD_32,
+        Test_CWD_32_signed,
+
+        Test_CWDE_32,
+        Test_CWDE_32_signed,
+
+        Test_CWDE_64,
+        Test_CWDE_64_signed,
+
+        Test_CDQ_32,
+        Test_CDQ_32_signed,
+
+        Test_CDQ_64,
+        Test_CDQ_64_signed,
+
+        Test_CDQE_64,
+        Test_CDQE_64_signed,
+    ]
+    if sys.argv[1] not in ["gcc", "tcc"]:
+        # TODO XXX CQO use 128 bit not supported in gcc yet!
+        tests += [
+            Test_CQO_64,
+            Test_CQO_64_signed,
+        ]
+
+    [
+        test(*sys.argv[1:])() for test in tests
+    ]