diff options
Diffstat (limited to 'test/arch')
| -rw-r--r-- | test/arch/arm/arch.py | 9 | ||||
| -rw-r--r-- | test/arch/mips32/arch.py | 38 | ||||
| -rwxr-xr-x | test/arch/msp430/sem.py | 6 | ||||
| -rw-r--r-- | test/arch/ppc32/arch.py | 8 | ||||
| -rwxr-xr-x | test/arch/x86/sem.py | 6 |
5 files changed, 62 insertions, 5 deletions
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 5aa619ea..740655da 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -233,6 +233,15 @@ reg_tests_arm = [ ('XXXXXXXX PKHTB R1, R2, R3 ASR 0x20', '531082e6'), + ('XXXXXXXX MRC p15, 0x0, R0, c1, c1, 0x0', + '110f11ee'), + ('XXXXXXXX MCR p15, 0x0, R8, c2, c0, 0x0', + '108f02ee'), + ('XXXXXXXX MRCNE p15, 0x0, R0, c1, c1, 0x0', + '110f111e'), + ('XXXXXXXX MCRCC p15, 0x0, R8, c2, c0, 0x1', + '308f023e'), + ] ts = time.time() diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py index e5e8cff6..de6d4547 100644 --- a/test/arch/mips32/arch.py +++ b/test/arch/mips32/arch.py @@ -214,6 +214,44 @@ reg_tests_mips32 = [ ("XXXXXXXX LDC1 F22, 0xFFFF9148(V0)", "D4569148"), + + ("XXXXXXXX BEQL S0, V0, 0x124", + "52020048"), + ("XXXXXXXX BGEZL T3, 0x24", + "05630008"), + ("XXXXXXXX BNEL A0, ZERO, 0x2C", + "5480000A"), + ("XXXXXXXX BLTZL S6, 0x5C", + "06C20016"), + ("XXXXXXXX BLEZL V1, 0x80", + "5860001F"), + ("XXXXXXXX BGTZL S4, 0x14", + "5E800004"), + ("XXXXXXXX BC1FL FCC0, 0x24", + "45020008"), + ("XXXXXXXX BC1TL FCC0, 0xB8", + "4503002D"), + + ("XXXXXXXX CLZ K0, K1", + "737AD020"), + + ("XXXXXXXX LL A0, 0x123(A1)", + "C0A40123"), + ("XXXXXXXX SC A1, 0x123(A0)", + "E0850123"), + + ("XXXXXXXX SYNC 0x19", + "0000064F"), + ("XXXXXXXX TLBR ", + "42000001"), + + ("XXXXXXXX ERET ", + "42000018"), + + ("XXXXXXXX MTHI A0", + "00800011"), + ("XXXXXXXX MTLO A1", + "00A00013") ] diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py index 2aca66ed..cb101937 100755 --- a/test/arch/msp430/sem.py +++ b/test/arch/msp430/sem.py @@ -39,10 +39,12 @@ def compute(asm, inputstate={}, debug=False): for k, v in viewitems(symexec.symbols): if regs_init.get(k, None) != v: print(k, v) - return { - k: v.arg.arg for k, v in viewitems(symexec.symbols) + + result = { + k: int(v) for k, v in viewitems(symexec.symbols) if k not in EXCLUDE_REGS and regs_init.get(k, None) != v } + return result class TestMSP430Semantic(unittest.TestCase): diff --git a/test/arch/ppc32/arch.py b/test/arch/ppc32/arch.py index c10a046e..13c69c73 100644 --- a/test/arch/ppc32/arch.py +++ b/test/arch/ppc32/arch.py @@ -42,6 +42,7 @@ reg_tests = [ ('b', "XXXXXXXX LBZU R0, 0x1(R31)", "8c1f0001"), ('b', "XXXXXXXX LBZUX R0, R31, R3", "7c1f18ee"), ('b', "XXXXXXXX LBZX R0, R30, R31", "7c1ef8ae"), + ('b', "XXXXXXXX LFS FPR6, 0x1(R1)", "c0c10001"), ('b', "XXXXXXXX LHA R9, 0x8(R31)", "a93f0008"), ('b', "XXXXXXXX LHAU R0, 0xFFFFFFFE(R9)", "ac09fffe"), ('b', "XXXXXXXX LHAX R0, R11, R9", "7c0b4aae"), @@ -49,10 +50,16 @@ reg_tests = [ ('b', "XXXXXXXX LHZX R0, R9, R10", "7c09522e"), ('b', "XXXXXXXX LMW R14, 0x8(R1)", "b9c10008"), ('b', "XXXXXXXX LSWI R5, R4, 0xC", "7ca464aa"), + ('b', "XXXXXXXX LVEWX VR0, R1, R2", "7c01108e"), + ('b', "XXXXXXXX LVSL VR0, R1, R2", "7c01100c"), + ('b', "XXXXXXXX LVSR VR0, R1, R2", "7c01104c"), ('b', "XXXXXXXX LWZ R0, 0x24(R1)", "80010024"), ('b', "XXXXXXXX LWZU R0, 0x4(R7)", "84070004"), ('b', "XXXXXXXX LWZX R29, R25, R0", "7fb9002e"), ('b', "XXXXXXXX MCRF CR1, CR2", "4c880000"), + ('b', "XXXXXXXX MFFS FPR23", "fee0048e"), + ('b', "XXXXXXXX MTFSF 0x88, FPR6", "fd10358e"), + ('b', "XXXXXXXX MTVSCR VR0", "10000644"), ('b', "XXXXXXXX MULLI R0, R2, 0xFFFFFFE7", "1c02ffe7"), ('b', "XXXXXXXX MULLI R3, R30, 0xC", "1c7e000c"), ('b', "XXXXXXXX NAND R0, R0, R0", "7c0003b8"), @@ -72,6 +79,7 @@ reg_tests = [ ('b', "XXXXXXXX SRW R0, R23, R10", "7ee05430"), ('b', "XXXXXXXX STB R0, 0x1020(R30)", "981e1020"), ('b', "XXXXXXXX STBU R0, 0x1(R11)", "9c0b0001"), + ('b', "XXXXXXXX STFS FPR6, 0x1(R1)", "d0c10001"), ('b', "XXXXXXXX STH R6, (R3)", "b0c30000"), ('b', "XXXXXXXX STMW R14, 0x8(R1)", "bdc10008"), ('b', "XXXXXXXX STW R0, 0x24(R1)", "90010024"), diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index 5109d2b4..10980b05 100755 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -104,7 +104,7 @@ class TestX86Semantic(unittest.TestCase): sem = compute(ir_32, m32, '%s XMM0, XMM1' % name, {XMM0: arg1, XMM1: arg2}, False) - ref = ExprInt(int_vec_op(op, elt_size, reg_size, arg1.arg, arg2.arg), XMM0.size) + ref = ExprInt(int_vec_op(op, elt_size, reg_size, int(arg1), int(arg2)), XMM0.size) self.assertEqual(sem, {XMM0: ref, XMM1: arg2}) def symb_sse_ops(self, names, a, b, ref): @@ -121,7 +121,7 @@ class TestX86Semantic(unittest.TestCase): sem = compute(ir_32, m32, '%s MM0, MM1' % name, {mm0: arg1, mm1: arg2}, False) - ref = ExprInt(op(arg1.arg, arg2.arg), mm0.size) + ref = ExprInt(op(int(arg1), int(arg2)), mm0.size) self.assertEqual(sem, {mm0: ref, mm1: arg2}) def sse_logical_op(self, name, op, arg1, arg2): @@ -130,7 +130,7 @@ class TestX86Semantic(unittest.TestCase): sem = compute(ir_32, m32, '%s XMM0, XMM1' % name, {XMM0: arg1, XMM1: arg2}, False) - ref = ExprInt(op(arg1.arg, arg2.arg), XMM0.size) + ref = ExprInt(op(int(arg1), int(arg2)), XMM0.size) self.assertEqual(sem, {XMM0: ref, XMM1: arg2}) def test_SSE_ADD(self): |