diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/arch/arm/arch.py | 18 | ||||
| -rw-r--r-- | test/arch/mips32/arch.py | 20 | ||||
| -rw-r--r-- | test/arch/msp430/arch.py | 4 | ||||
| -rw-r--r-- | test/arch/x86/arch.py | 31 | ||||
| -rw-r--r-- | test/arch/x86/sem.py | 5 | ||||
| -rw-r--r-- | test/arch/x86/unit/asm_test.py | 15 | ||||
| -rw-r--r-- | test/core/interval.py | 1 |
7 files changed, 42 insertions, 52 deletions
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 19b1236e..701c45af 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -66,13 +66,13 @@ reg_tests_arm = [ "002094e0"), ("0003EA9C MVN R7, R2", "0270e0e1"), - ("C00CD4DC BL 0x7C", + ("C00CD4DC BL 0x84", "1F0000EB"), - ("C00CF110 BL 0xFFFFFDEC", + ("C00CF110 BL 0xFFFFFDF4", "7BFFFFEB"), - ("000829b0 BLNE 0xFFF87110", + ("000829b0 BLNE 0xFFF87118", "441cfe1b"), ("C00EC608 TEQ R4, R5", @@ -205,7 +205,7 @@ reg_tests_arm = [ ("C00CFA40 BLX R12", "3CFF2FE1"), - ("C010DE1C BLX 0x1ECCEA", + ("C010DE1C BLX 0x1ECCF2", "3AB307FB"), ("00013028 MOV R9, 0x6E75", @@ -217,7 +217,7 @@ reg_tests_arm = [ ("0004A38C CLZ R3, R2", "123F6FE1"), - ("C0132564 BLX 0xFFFCF06C", + ("C0132564 BLX 0xFFFCF074", "1B3CFFFA"), ("C0297028 QADD R7, R6, R6", @@ -414,15 +414,15 @@ reg_tests_armt = [ ("000a1c16 STMIA R6!, {R0-R3}", "0fc6"), - ("0006af78 BEQ 0x6", + ("0006af78 BEQ 0xA", "03d0"), - ("000747b4 BCC 0xFFFFFFE6", + ("000747b4 BCC 0xFFFFFFEA", "f3d3"), # swi - ("0007479c B 0xE", + ("0007479c B 0x12", "07e0"), - ("0006b946 B 0xFFFFFFE4", + ("0006b946 B 0xFFFFFFE8", "f2e7"), ("C010163C BLX 0x1F916C", "F9F1B6E8"), diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py index 899748ce..0fb12e1b 100644 --- a/test/arch/mips32/arch.py +++ b/test/arch/mips32/arch.py @@ -46,9 +46,9 @@ reg_tests_mips32 = [ "44097000"), ("00400324 MOV.D F0, F12", "46206006"), - ("00400334 BNE A0, ZERO, 0x28", + ("00400334 BNE A0, ZERO, 0x2C", "1480000A"), - ("00400360 B 0x338", + ("00400360 B 0x33C", "100000CE"), ("00400378 LW T9, 0xFFFF9C90(GP)", "8F999C90"), @@ -58,11 +58,11 @@ reg_tests_mips32 = [ "30420002"), ("00400364 ADD.D F0, F0, F14", "462E0000"), - ("004003A4 BEQ S0, V0, 0x120", + ("004003A4 BEQ S0, V0, 0x124", "12020048"), ("004003A8 SLTI V0, S0, 0x3", "2A020003"), - ("004005A4 BGEZ T3, 0x20", + ("004005A4 BGEZ T3, 0x24", "05610008"), ("00400428 LWC1 F0, 0x4344(V0)", "C4404344"), @@ -80,13 +80,13 @@ reg_tests_mips32 = [ "92228880"), ("004001C4 SB V0, 0xFFFF8880(S1)", "A2228880"), - ("00400274 BAL 0x4", + ("00400274 BAL 0x8", "04110001"), ("0040073C C.LT.D FCC0, F0, F12", "462C003C"), - ("00400744 BC1F FCC0, 0x20", + ("00400744 BC1F FCC0, 0x24", "45000008"), - ("00403A80 BC1T FCC0, 0xB4", + ("00403A80 BC1T FCC0, 0xB8", "4501002D"), ("00400764 MUL.D F12, F0, F0", "46200302"), @@ -104,11 +104,11 @@ reg_tests_mips32 = [ "00431004"), ("00400F60 SRAV V1, S3, V0", "00531807"), - ("00401040 BLTZ S6, 0x58", + ("00401040 BLTZ S6, 0x5C", "06C00016"), - ("00400D18 BLEZ V1, 0x7C", + ("00400D18 BLEZ V1, 0x80", "1860001F"), - ("00401200 BGTZ S4, 0x10", + ("00401200 BGTZ S4, 0x14", "1E800004"), ("004014A4 CVT.D.W F8, F0", "46800221"), diff --git a/test/arch/msp430/arch.py b/test/arch/msp430/arch.py index f3e82955..613af385 100644 --- a/test/arch/msp430/arch.py +++ b/test/arch/msp430/arch.py @@ -72,9 +72,9 @@ reg_tests_msp = [ ("443a call 0x4B66", "b012664b"), - ("4442 jmp 0xFFFA", + ("4442 jmp 0xFFFC", "fd3f"), - ("4422 jnz 0xFFF2", + ("4422 jnz 0xFFF4", "f923"), ("xxxx mov.b @R13+, 0x0(R14)", diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 884d545b..9d4e464d 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -232,10 +232,10 @@ reg_tests = [ "0fba2842"), - (m32, "00000000 CALL 0x112233", - "e833221100"), - (m64, "00000000 CALL 0x112233", - "e833221100"), + (m32, "00000000 CALL 0x112235", + "e830221100"), + (m64, "00000000 CALL 0x112235", + "e830221100"), (m32, "00000000 CALL DWORD PTR [EAX]", "ff10"), (m64, "00000000 CALL QWORD PTR [RAX]", @@ -761,11 +761,11 @@ reg_tests = [ "48CF"), (m32, "00000000 JA 0x12", - "7712"), + "7710"), (m32, "00000000 JA 0xFFFFFFEE", - "77EE"), + "77EC"), (m64, "00000000 JA 0xFFFFFFFFFFFFFFEE", - "77EE"), + "77EC"), #(m32, "00000000 JA 0xFFEE", # "6677EE"), @@ -774,19 +774,19 @@ reg_tests = [ (m16, "00000000 JCXZ 0xFFEE", - "E3EE"), + "E3EC"), (m16, "00000000 JECXZ 0xFFEE", - "67E3EE"), + "67E3EB"), (m32, "00000000 JECXZ 0xFFFFFFEE", - "E3EE"), + "E3EC"), (m32, "00000000 JCXZ 0xFFFFFFEE", - "67E3EE"), + "67E3EB"), (m32, "00000000 JCXZ 0xFFEE", - "6667E3EE"), + "6667E3EA"), (m64, "00000000 JRCXZ 0xFFFFFFFFFFFFFFEE", - "E3EE"), + "E3EC"), (m64, "00000000 JECXZ 0xFFFFFFFFFFFFFFEE", - "67E3EE"), + "67E3EB"), (m32, "00000000 MOV BYTE PTR [EAX], AL", @@ -1161,6 +1161,9 @@ reg_tests = [ (m64, "00000000 PUSH 0x11223344", "6844332211"), + (m32, "00000000 PUSH 0xFFFFFF80", + "6a80"), + (m32, "00000000 PUSH CS", "0e"), (m32, "00000000 PUSH SS", diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index d2c998c8..b80ab33d 100644 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -47,10 +47,9 @@ def compute(ir, mode, asm, inputstate={}, debug=False): def compute_txt(ir, mode, txt, inputstate={}, debug=False): blocs, symbol_pool = parse_asm.parse_txt(mn, mode, txt) symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) - resolved_b, patches = asmbloc.asm_resolve_final( - mn, blocs[0], symbol_pool) + patches = asmbloc.asm_resolve_final(mn, blocs[0], symbol_pool) interm = ir(symbol_pool) - for bbl in resolved_b: + for bbl in blocs[0]: interm.add_bloc(bbl) return symb_exec(interm, inputstate, debug) diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index f28c4d2f..c6381d9e 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -20,18 +20,6 @@ if filename and os.path.isfile(filename): reg_and_id = dict(mn_x86.regs.all_regs_ids_byname) - -def my_ast_int2expr(a): - return ExprInt32(a) - - -def my_ast_id2expr(t): - return reg_and_id.get(t, ExprId(t, size=32)) - -my_var_parser = parse_ast(my_ast_id2expr, my_ast_int2expr) -base_expr.setParseAction(my_var_parser) - - class Asm_Test(object): def __init__(self): self.myjit = Machine("x86_32").jitter() @@ -53,8 +41,7 @@ class Asm_Test(object): # fix shellcode addr symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) s = StrPatchwork() - resolved_b, patches = asmbloc.asm_resolve_final( - mn_x86, blocs[0], symbol_pool) + patches = asmbloc.asm_resolve_final(mn_x86, blocs[0], symbol_pool) for offset, raw in patches.items(): s[offset] = raw diff --git a/test/core/interval.py b/test/core/interval.py index 34537d25..4572ac50 100644 --- a/test/core/interval.py +++ b/test/core/interval.py @@ -49,6 +49,7 @@ assert((i2 in i3) is False) assert((i3 in i2)) assert((i2 in i3) is False) +assert((i3 in i14)) assert(interval.cannon_list(i1.intervals) == i1.intervals) |