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-rw-r--r--test/arch/arm/sem.py8
-rw-r--r--test/arch/msp430/sem.py9
-rw-r--r--test/arch/x86/sem.py4
-rw-r--r--test/ir/symbexec.py4
-rw-r--r--test/test_all.py4
5 files changed, 14 insertions, 15 deletions
diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py
index be36e90b..7fcf9e85 100644
--- a/test/arch/arm/sem.py
+++ b/test/arch/arm/sem.py
@@ -6,12 +6,12 @@ import logging
 
 from miasm2.ir.symbexec import symbexec
 from miasm2.arch.arm.arch import mn_arm as mn, mode_arm as mode
-from miasm2.arch.arm.sem import ir_arm as ir
+from miasm2.arch.arm.sem import ir_arm as ir_arch
 from miasm2.arch.arm.regs import *
 from miasm2.expression.expression import *
 
 logging.getLogger('cpuhelper').setLevel(logging.ERROR)
-EXCLUDE_REGS = set()
+EXCLUDE_REGS = set([ir_arch().IRDst])
 
 
 def M(addr):
@@ -21,12 +21,12 @@ def M(addr):
 def compute(asm, inputstate={}, debug=False):
     sympool = dict(regs_init)
     sympool.update({k: ExprInt_from(k, v) for k, v in inputstate.iteritems()})
-    symexec = symbexec(mn, sympool)
+    interm = ir_arch()
+    symexec = symbexec(interm, sympool)
     instr = mn.fromstring(asm, mode)
     code = mn.asm(instr)[0]
     instr = mn.dis(code, mode)
     instr.offset = inputstate.get(PC, 0)
-    interm = ir()
     interm.add_instr(instr)
     symexec.emul_ir_blocs(interm, instr.offset)
     if debug:
diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py
index 55da5d56..5340a4d2 100644
--- a/test/arch/msp430/sem.py
+++ b/test/arch/msp430/sem.py
@@ -6,13 +6,12 @@ import logging
 
 from miasm2.ir.symbexec import symbexec
 from miasm2.arch.msp430.arch import mn_msp430 as mn, mode_msp430 as mode
-from miasm2.arch.msp430.sem import ir_msp430 as ir
+from miasm2.arch.msp430.sem import ir_msp430 as ir_arch
 from miasm2.arch.msp430.regs import *
 from miasm2.expression.expression import *
 
 logging.getLogger('cpuhelper').setLevel(logging.ERROR)
-EXCLUDE_REGS = set([res])
-
+EXCLUDE_REGS = set([res, ir_arch().IRDst])
 
 def M(addr):
     return ExprMem(ExprInt_fromsize(16, addr), 16)
@@ -21,12 +20,12 @@ def M(addr):
 def compute(asm, inputstate={}, debug=False):
     sympool = dict(regs_init)
     sympool.update({k: ExprInt_from(k, v) for k, v in inputstate.iteritems()})
-    symexec = symbexec(mn, sympool)
+    interm = ir_arch()
+    symexec = symbexec(interm, sympool)
     instr = mn.fromstring(asm, mode)
     code = mn.asm(instr)[0]
     instr = mn.dis(code, mode)
     instr.offset = inputstate.get(PC, 0)
-    interm = ir()
     interm.add_instr(instr)
     symexec.emul_ir_blocs(interm, instr.offset)
     if debug:
diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py
index 64447e13..bd28bd45 100644
--- a/test/arch/x86/sem.py
+++ b/test/arch/x86/sem.py
@@ -17,7 +17,7 @@ from miasm2.core import parse_asm, asmbloc
 
 
 logging.getLogger('cpuhelper').setLevel(logging.ERROR)
-EXCLUDE_REGS = set()
+EXCLUDE_REGS = set([ir_32().IRDst, ir_64().IRDst])
 
 m32 = 32
 m64 = 64
@@ -25,7 +25,7 @@ m64 = 64
 def symb_exec(interm, inputstate, debug):
     sympool = dict(regs_init)
     sympool.update(inputstate)
-    symexec = symbexec(mn, sympool)
+    symexec = symbexec(interm, sympool)
     symexec.emul_ir_blocs(interm, 0)
     if debug:
         for k, v in symexec.symbols.items():
diff --git a/test/ir/symbexec.py b/test/ir/symbexec.py
index 0d3db7e8..1d87b470 100644
--- a/test/ir/symbexec.py
+++ b/test/ir/symbexec.py
@@ -8,7 +8,7 @@ class TestSymbExec(unittest.TestCase):
 
     def test_ClassDef(self):
         from miasm2.expression.expression import ExprInt32, ExprId, ExprMem, ExprCompose
-        from miasm2.arch.x86.arch import mn_x86
+        from miasm2.arch.x86.sem import ir_x86_32
         from miasm2.ir.symbexec import symbexec
 
         addrX = ExprInt32(-1)
@@ -34,7 +34,7 @@ class TestSymbExec(unittest.TestCase):
         id_eax = ExprId('eax_init')
 
         e = symbexec(
-            mn_x86, {mem0: id_x, mem1: id_y, mem9: id_x, mem40w: id_x, mem50v: id_y, id_a: addr0, id_eax: addr0})
+            ir_x86_32(), {mem0: id_x, mem1: id_y, mem9: id_x, mem40w: id_x, mem50v: id_y, id_a: addr0, id_eax: addr0})
         self.assertEqual(e.find_mem_by_addr(addr0), mem0)
         self.assertEqual(e.find_mem_by_addr(addrX), None)
         self.assertEqual(e.eval_ExprMem(ExprMem(addr1 - addr1)), id_x)
diff --git a/test/test_all.py b/test/test_all.py
index 4967ed3d..9bdfa425 100644
--- a/test/test_all.py
+++ b/test/test_all.py
@@ -414,8 +414,8 @@ try:
 except ImportError:
     llvm = False
 
-# if llvm.version != (3,2):
-#    llvm = False
+# TODO XXX: fix llvm jitter (deactivated for the moment)
+llvm = False
 
 if llvm is False:
     print "%(red)s[LLVM]%(end)s Python 'py-llvm 3.2' module is required for llvm tests" % colors