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-rw-r--r--test/analysis/data_flow.py28
-rw-r--r--test/analysis/depgraph.py72
-rw-r--r--test/arch/x86/arch.py115
-rw-r--r--test/arch/x86/unit/mn_cdq.py445
-rw-r--r--test/core/sembuilder.py12
-rw-r--r--test/expression/expression.py2
-rwxr-xr-xtest/expression/expression_helper.py4
-rw-r--r--test/expression/simplifications.py28
-rw-r--r--test/ir/ir.py4
-rwxr-xr-xtest/ir/symbexec.py6
-rwxr-xr-xtest/test_all.py1
11 files changed, 635 insertions, 82 deletions
diff --git a/test/analysis/data_flow.py b/test/analysis/data_flow.py
index 2c24773a..dff88470 100644
--- a/test/analysis/data_flow.py
+++ b/test/analysis/data_flow.py
@@ -5,20 +5,20 @@ from miasm2.analysis.data_flow import *
 from miasm2.ir.analysis import ira
 from miasm2.ir.ir import IRBlock, AssignBlock
 
-a = ExprId("a")
-b = ExprId("b")
-c = ExprId("c")
-d = ExprId("d")
-r = ExprId("r")
+a = ExprId("a", 32)
+b = ExprId("b", 32)
+c = ExprId("c", 32)
+d = ExprId("d", 32)
+r = ExprId("r", 32)
 
-a_init = ExprId("a_init")
-b_init = ExprId("b_init")
-c_init = ExprId("c_init")
-d_init = ExprId("d_init")
-r_init = ExprId("r_init") # Return register
+a_init = ExprId("a_init", 32)
+b_init = ExprId("b_init", 32)
+c_init = ExprId("c_init", 32)
+d_init = ExprId("d_init", 32)
+r_init = ExprId("r_init", 32) # Return register
 
-pc = ExprId("pc")
-sp = ExprId("sp")
+pc = ExprId("pc", 32)
+sp = ExprId("sp", 32)
 
 CST1 = ExprInt(0x11, 32)
 CST2 = ExprInt(0x12, 32)
@@ -635,7 +635,7 @@ G17_EXP_IRB0 = gen_irblock(LBL0, [[],
                                    ExprAff(b, a),
                                    ExprAff(c, b)],
 
-                                  G17_IRB0.irs[14]
+                                  G17_IRB0[14]
                                   # Trick because a+b+c != ((a+b)+c)
                                  ])
 
@@ -684,4 +684,4 @@ for test_nb, test in enumerate([(G1_IRA, G1_EXP_IRA),
     # Check that each expr in the blocks are the same
     for lbl, irb in g_ira.blocks.iteritems():
         exp_irb = g_exp_ira.blocks[lbl]
-        assert exp_irb.irs == irb.irs
+        assert exp_irb.assignblks == irb.assignblks
diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py
index 63313861..9fb046d0 100644
--- a/test/analysis/depgraph.py
+++ b/test/analysis/depgraph.py
@@ -16,19 +16,19 @@ except ImportError:
     EMULATION = False
 
 STEP_COUNTER = count()
-A = ExprId("a")
-B = ExprId("b")
-C = ExprId("c")
-D = ExprId("d")
-R = ExprId("r")
+A = ExprId("a", 32)
+B = ExprId("b", 32)
+C = ExprId("c", 32)
+D = ExprId("d", 32)
+R = ExprId("r", 32)
 
-A_INIT = ExprId("a_init")
-B_INIT = ExprId("b_init")
-C_INIT = ExprId("c_init")
-D_INIT = ExprId("d_init")
+A_INIT = ExprId("a_init", 32)
+B_INIT = ExprId("b_init", 32)
+C_INIT = ExprId("c_init", 32)
+D_INIT = ExprId("d_init", 32)
 
-PC = ExprId("pc")
-SP = ExprId("sp")
+PC = ExprId("pc", 32)
+SP = ExprId("sp", 32)
 
 CST0 = ExprInt(0x0, 32)
 CST1 = ExprInt(0x1, 32)
@@ -132,7 +132,7 @@ def bloc2graph(irgraph, label=False, lines=True):
             label_attr, label_name)
         block_html_lines = []
         if lines and irblock is not None:
-            for assignblk in irblock.irs:
+            for assignblk in irblock:
                 for dst, src in assignblk.iteritems():
                     if False:
                         out_render = "%.8X</td><td %s> " % (0, td_attr)
@@ -277,8 +277,8 @@ G4_IRA = IRATest()
 G4_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1)]])
 G4_IRB1 = gen_irblock(LBL1, [[ExprAff(C, C + CST2)],
                              [ExprAff(G4_IRA.IRDst,
-                                      ExprCond(C, ExprId(LBL2),
-                                               ExprId(LBL1)))]])
+                                      ExprCond(C, ExprId(LBL2, 32),
+                                               ExprId(LBL1, 32)))]])
 
 G4_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B)]])
 
@@ -296,8 +296,8 @@ G5_IRA = IRATest()
 G5_IRB0 = gen_irblock(LBL0, [[ExprAff(B, CST1)]])
 G5_IRB1 = gen_irblock(LBL1, [[ExprAff(B, B + CST2)],
                              [ExprAff(G5_IRA.IRDst,
-                                      ExprCond(B, ExprId(LBL2),
-                                               ExprId(LBL1)))]])
+                                      ExprCond(B, ExprId(LBL2, 32),
+                                               ExprId(LBL1, 32)))]])
 
 G5_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B)]])
 
@@ -400,16 +400,16 @@ G13_IRA = IRATest()
 G13_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1)],
                               #[ExprAff(B, A)],
                               [ExprAff(G13_IRA.IRDst,
-                                       ExprId(LBL1))]])
+                                       ExprId(LBL1, 32))]])
 G13_IRB1 = gen_irblock(LBL1, [[ExprAff(C, A)],
                               #[ExprAff(A, A + CST1)],
                               [ExprAff(G13_IRA.IRDst,
-                                       ExprCond(R, ExprId(LBL2),
-                                                ExprId(LBL1)))]])
+                                       ExprCond(R, ExprId(LBL2, 32),
+                                                ExprId(LBL1, 32)))]])
 
 G13_IRB2 = gen_irblock(LBL2, [[ExprAff(B, A + CST3)], [ExprAff(A, B + CST3)],
                               [ExprAff(G13_IRA.IRDst,
-                                       ExprId(LBL1))]])
+                                       ExprId(LBL1, 32))]])
 
 G13_IRB3 = gen_irblock(LBL3, [[ExprAff(R, C)]])
 
@@ -427,18 +427,18 @@ G14_IRA = IRATest()
 
 G14_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1)],
                               [ExprAff(G14_IRA.IRDst,
-                                       ExprId(LBL1))]
+                                       ExprId(LBL1, 32))]
                              ])
 G14_IRB1 = gen_irblock(LBL1, [[ExprAff(B, A)],
                               [ExprAff(G14_IRA.IRDst,
-                                       ExprCond(C, ExprId(LBL2),
-                                                ExprId(LBL3)))]
+                                       ExprCond(C, ExprId(LBL2, 32),
+                                                ExprId(LBL3, 32)))]
                              ])
 
 G14_IRB2 = gen_irblock(LBL2, [[ExprAff(D, A)],
                               [ExprAff(A, D + CST1)],
                               [ExprAff(G14_IRA.IRDst,
-                                       ExprId(LBL1))]
+                                       ExprId(LBL1, 32))]
                              ])
 
 G14_IRB3 = gen_irblock(LBL3, [[ExprAff(R, D + B)]])
@@ -510,72 +510,72 @@ G17_IRA.blocks = dict([(irb.label, irb) for irb in [G17_IRB0, G17_IRB1,
 
 # Test graph 1
 G1_TEST1_DN1 = DependencyNode(
-    G1_IRB2.label, A, len(G1_IRB2.irs))
+    G1_IRB2.label, A, len(G1_IRB2))
 
 G1_INPUT = (set([G1_TEST1_DN1]), set([G1_IRB0.label]))
 
 # Test graph 2
 
 G2_TEST1_DN1 = DependencyNode(
-    G2_IRB2.label, A, len(G2_IRB2.irs))
+    G2_IRB2.label, A, len(G2_IRB2))
 
 G2_INPUT = (set([G2_TEST1_DN1]), set([G2_IRB0.label]))
 
 # Test graph 3
 
 G3_TEST1_0_DN1 = DependencyNode(
-    G3_IRB3.label, A, len(G3_IRB3.irs))
+    G3_IRB3.label, A, len(G3_IRB3))
 
 G3_INPUT = (set([G3_TEST1_0_DN1]), set([G3_IRB0.label]))
 
 # Test graph 4
 
 G4_TEST1_DN1 = DependencyNode(
-    G4_IRB2.label, A, len(G2_IRB0.irs))
+    G4_IRB2.label, A, len(G2_IRB0))
 
 G4_INPUT = (set([G4_TEST1_DN1]), set([G4_IRB0.label]))
 
 # Test graph 5
 
 G5_TEST1_0_DN1 = DependencyNode(
-    G5_IRB2.label, A, len(G5_IRB2.irs))
+    G5_IRB2.label, A, len(G5_IRB2))
 
 G5_INPUT = (set([G5_TEST1_0_DN1]), set([G5_IRB0.label]))
 
 # Test graph 6
 
 G6_TEST1_0_DN1 = DependencyNode(
-    G6_IRB1.label, A, len(G6_IRB1.irs))
+    G6_IRB1.label, A, len(G6_IRB1))
 
 G6_INPUT = (set([G6_TEST1_0_DN1]), set([G6_IRB0.label]))
 
 # Test graph 7
 
 G7_TEST1_0_DN1 = DependencyNode(
-    G7_IRB2.label, D, len(G7_IRB2.irs))
+    G7_IRB2.label, D, len(G7_IRB2))
 
 G7_INPUT = (set([G7_TEST1_0_DN1]), set([G7_IRB0.label]))
 
 # Test graph 8
 
 G8_TEST1_0_DN1 = DependencyNode(
-    G8_IRB2.label, A, len(G8_IRB2.irs))
+    G8_IRB2.label, A, len(G8_IRB2))
 
 G8_INPUT = (set([G8_TEST1_0_DN1]), set([G3_IRB0.label]))
 
 # Test 9: Multi elements
 
 G9_TEST1_0_DN1 = DependencyNode(
-    G8_IRB2.label, A, len(G8_IRB2.irs))
+    G8_IRB2.label, A, len(G8_IRB2))
 G9_TEST1_0_DN5 = DependencyNode(
-    G8_IRB2.label, C, len(G8_IRB2.irs))
+    G8_IRB2.label, C, len(G8_IRB2))
 
 G9_INPUT = (set([G9_TEST1_0_DN1, G9_TEST1_0_DN5]), set([G8_IRB0.label]))
 
 # Test 10: loop at beginning
 
 G10_TEST1_0_DN1 = DependencyNode(
-    G10_IRB2.label, A, len(G10_IRB2.irs))
+    G10_IRB2.label, A, len(G10_IRB2))
 
 G10_INPUT = (set([G10_TEST1_0_DN1]), set([G10_IRB1.label]))
 
@@ -583,7 +583,7 @@ G10_INPUT = (set([G10_TEST1_0_DN1]), set([G10_IRB1.label]))
 # Test 11: no dual bloc emulation
 
 G11_TEST1_DN1 = DependencyNode(
-    G11_IRB2.label, A, len(G11_IRB2.irs))
+    G11_IRB2.label, A, len(G11_IRB2))
 
 G11_INPUT = (set([G11_TEST1_DN1]), set([G11_IRB0.label]))
 
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py
index d3b2964c..2af90c8a 100644
--- a/test/arch/x86/arch.py
+++ b/test/arch/x86/arch.py
@@ -2902,11 +2902,11 @@ reg_tests = [
     (m32, "00000000    PEXTRW     WORD PTR [EDX], XMM2, 0x5",
     "660F3A151205"),
 
+    (m32, "00000000    PEXTRW     EAX, MM2, 0x5",
+    "0fc5c205"),
+    (m32, "00000000    PEXTRW     EAX, XMM2, 0x5",
+    "660fc5c205"),
 
-    (m32, "00000000    PEXTRW     WORD PTR [EDX], MM2, 0x5",
-    "0FC51205"),
-    (m32, "00000000    PEXTRW     WORD PTR [EDX], XMM2, 0x5",
-    "660FC51205"),
 
     (m32, "00000000    PEXTRD     DWORD PTR [EDX], XMM2, 0x5",
     "660F3A161205"),
@@ -2970,6 +2970,113 @@ reg_tests = [
     (m64, "00000000    BNDMOV     BND3, XMMWORD PTR [RSP + 0xB0]",
      "660f1a9c24b0000000"),
 
+    (m32, "00000000    PACKSSWB   MM7, MM0",
+     "0f63f8"),
+    (m32, "00000000    PACKSSWB   XMM0, XMM5",
+     "660f63c5"),
+
+    (m32, "00000000    PACKSSDW   MM2, MM0",
+     "0f6bd0"),
+    (m32, "00000000    PACKSSDW   XMM0, XMM7",
+     "660f6bc7"),
+
+    (m32, "00000000    PACKUSWB   MM1, MM7",
+     "0f67cf"),
+    (m32, "00000000    PACKUSWB   XMM0, XMM6",
+     "660f67c6"),
+
+    (m32, "00000000    PMULLW     MM4, MM2",
+     "0fd5e2"),
+    (m32, "00000000    PMULLW     XMM0, XMM3",
+     "660fd5c3"),
+
+    (m32, "00000000    PSUBUSB    MM5, MM3",
+     "0fd8eb"),
+    (m32, "00000000    PSUBUSB    XMM0, XMM5",
+     "660fd8c5"),
+
+    (m32, "00000000    PSUBUSW    MM5, MM3",
+     "0fd9eb"),
+    (m32, "00000000    PSUBUSW    XMM0, XMM5",
+     "660fd9c5"),
+
+    (m32, "00000000    PADDUSB    MM5, MM3",
+     "0fdceb"),
+    (m32, "00000000    PADDUSB    XMM0, XMM6",
+     "660fdcc6"),
+
+    (m32, "00000000    PADDUSW    MM7, MM5",
+     "0fddfd"),
+    (m32, "00000000    PADDUSW    XMM0, XMM1",
+     "660fddc1"),
+
+    (m32, "00000000    PMULHUW    MM6, MM4",
+     "0fe4f4"),
+    (m32, "00000000    PMULHUW    XMM0, XMM7",
+     "660fe4c7"),
+
+    (m32, "00000000    PMULHW     MM6, MM4",
+     "0fe5f4"),
+    (m32, "00000000    PMULHW     XMM0, XMM7",
+     "660fe5c7"),
+
+    (m32, "00000000    PSUBSB     MM2, MM0",
+     "0fe8d0"),
+    (m32, "00000000    PSUBSB     XMM0, XMM4",
+     "660fe8c4"),
+
+    (m32, "00000000    PSUBSW     MM3, MM1",
+     "0fe9d9"),
+    (m32, "00000000    PSUBSW     XMM0, XMM6",
+     "660fe9c6"),
+
+    (m32, "00000000    PADDSB     MM2, MM0",
+     "0fecd0"),
+    (m32, "00000000    PADDSB     XMM0, XMM4",
+     "660fecc4"),
+
+    (m32, "00000000    PADDSW     MM3, MM1",
+     "0fedd9"),
+    (m32, "00000000    PADDSW     XMM0, XMM6",
+     "660fedc6"),
+
+    (m32, "00000000    PMAXSW     MM3, MM1",
+     "0feed9"),
+    (m32, "00000000    PMAXSW     XMM0, XMM6",
+     "660feec6"),
+
+    (m32, "00000000    PMULUDQ    MM3, MM1",
+     "0ff4d9"),
+    (m32, "00000000    PMULUDQ    XMM0, XMM6",
+     "660ff4c6"),
+
+    (m32, "00000000    PMADDWD    MM3, MM1",
+     "0ff5d9"),
+    (m32, "00000000    PMADDWD    XMM0, XMM6",
+     "660ff5c6"),
+
+    (m32, "00000000    PSADBW     MM3, MM1",
+     "0ff6d9"),
+    (m32, "00000000    PSADBW     XMM0, XMM6",
+     "660ff6c6"),
+
+    (m32, "00000000    PAVGB      MM3, MM1",
+     "0fe0d9"),
+    (m32, "00000000    PAVGB      XMM0, XMM6",
+     "660fe0c6"),
+
+    (m32, "00000000    PAVGW      MM3, MM1",
+     "0fe3d9"),
+    (m32, "00000000    PAVGW      XMM0, XMM6",
+     "660fe3c6"),
+
+    (m32, "00000000    MASKMOVQ   MM2, MM3",
+     "0ff7d3"),
+    (m32, "00000000    MASKMOVDQU XMM4, XMM5",
+     "660ff7e5"),
+
+    (m32, "00000000    EMMS",
+     "0f77"),
 ]
 
 
diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py
new file mode 100644
index 00000000..f4e4d6e7
--- /dev/null
+++ b/test/arch/x86/unit/mn_cdq.py
@@ -0,0 +1,445 @@
+#! /usr/bin/env python2
+
+import sys
+
+from asm_test import Asm_Test_16, Asm_Test_32, Asm_Test_64
+from miasm2.core.utils import pck16, pck32
+
+
+class Test_CBW_16(Asm_Test_16):
+    MYSTRING = "test CBW 16"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87650021
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_16_signed(Asm_Test_16):
+    MYSTRING = "test CBW 16 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654381
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x8765FF81
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_32(Asm_Test_32):
+    MYSTRING = "test CBW 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87650021
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CBW_32_signed(Asm_Test_32):
+    MYSTRING = "test CBW 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654381
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CBW
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x8765FF81
+        assert self.myjit.cpu.EDX == 0x11223344
+
+
+class Test_CDQ_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x77654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x77654321
+        assert self.myjit.cpu.EDX == 0x0
+
+
+class Test_CDQ_32_signed(Asm_Test_32):
+    MYSTRING = "test cdq 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0x87654321
+        assert self.myjit.cpu.EDX == 0xFFFFFFFF
+
+
+class Test_CDQ_64(Asm_Test_64):
+    MYSTRING = "test cdq 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567877654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567877654321
+        assert self.myjit.cpu.RDX == 0x0
+
+
+class Test_CDQ_64_signed(Asm_Test_64):
+    MYSTRING = "test cdq 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQ
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567887654321
+        assert self.myjit.cpu.RDX == 0x00000000FFFFFFFF
+
+
+class Test_CDQE_64(Asm_Test_64):
+    MYSTRING = "test cdq 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567877654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x77654321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CDQE_64_signed(Asm_Test_64):
+    MYSTRING = "test cdq 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CDQE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0xFFFFFFFF87654321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CWD_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87654321
+        assert self.myjit.cpu.RDX == 0x12340000
+
+
+class Test_CWD_32_signed(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87658321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87658321
+        assert self.myjit.cpu.RDX == 0x1234FFFF
+
+
+class Test_CWD_32(Asm_Test_32):
+    MYSTRING = "test cdq 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x12345678
+
+    TXT = '''
+    main:
+       CWD
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x87654321
+        assert self.myjit.cpu.RDX == 0x12340000
+
+
+class Test_CWDE_32(Asm_Test_32):
+    MYSTRING = "test cwde 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.EAX = 0x87654321
+        self.myjit.cpu.EDX = 0x11223344
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x4321
+        assert self.myjit.cpu.RDX == 0x11223344
+
+
+class Test_CWDE_32_signed(Asm_Test_32):
+    MYSTRING = "test cwde 32 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x87658321
+        self.myjit.cpu.RDX = 0x11223344
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.EAX == 0xFFFF8321
+        assert self.myjit.cpu.RDX == 0x11223344
+
+
+class Test_CWDE_64(Asm_Test_64):
+    MYSTRING = "test cwde 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x4321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CWDE_64_signed(Asm_Test_64):
+    MYSTRING = "test cwde 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887658321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CWDE
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0xFFFF8321
+        assert self.myjit.cpu.RDX == 0x1122334455667788
+
+
+class Test_CQO_64(Asm_Test_64):
+    MYSTRING = "test cwde 64"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x1234567887654321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CQO
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x1234567887654321
+        assert self.myjit.cpu.RDX == 0x0
+
+
+class Test_CQO_64_signed(Asm_Test_64):
+    MYSTRING = "test cwde 64 signed"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.myjit.cpu.RAX = 0x8234567887658321
+        self.myjit.cpu.RDX = 0x1122334455667788
+
+    TXT = '''
+    main:
+       CQO
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.RAX == 0x8234567887658321
+        assert self.myjit.cpu.RDX == 0xFFFFFFFFFFFFFFFF
+
+
+
+
+if __name__ == "__main__":
+    tests = [
+        Test_CBW_16,
+        Test_CBW_16_signed,
+
+        Test_CBW_32,
+        Test_CBW_32_signed,
+
+        Test_CWD_32,
+        Test_CWD_32_signed,
+
+        Test_CWDE_32,
+        Test_CWDE_32_signed,
+
+        Test_CWDE_64,
+        Test_CWDE_64_signed,
+
+        Test_CDQ_32,
+        Test_CDQ_32_signed,
+
+        Test_CDQ_64,
+        Test_CDQ_64_signed,
+
+        Test_CDQE_64,
+        Test_CDQE_64_signed,
+    ]
+    if sys.argv[1] not in ["gcc", "tcc"]:
+        # TODO XXX CQO use 128 bit not supported in gcc yet!
+        tests += [
+            Test_CQO_64,
+            Test_CQO_64_signed,
+        ]
+
+    [
+        test(*sys.argv[1:])() for test in tests
+    ]
diff --git a/test/core/sembuilder.py b/test/core/sembuilder.py
index d8fdb6c4..ebf9f385 100644
--- a/test/core/sembuilder.py
+++ b/test/core/sembuilder.py
@@ -8,7 +8,7 @@ from miasm2.core.asmblock import AsmLabel
 # Test classes
 class IR(object):
 
-    IRDst = m2_expr.ExprId("IRDst")
+    IRDst = m2_expr.ExprId("IRDst", 32)
 
     def get_next_instr(self, _):
         return AsmLabel("NEXT")
@@ -41,9 +41,9 @@ def test(Arg1, Arg2, Arg3):
     else:
         alias = {i16(4), i8(5)}
 
-a = m2_expr.ExprId('A')
-b = m2_expr.ExprId('B')
-c = m2_expr.ExprId('C')
+a = m2_expr.ExprId('A', 32)
+b = m2_expr.ExprId('B', 32)
+c = m2_expr.ExprId('C', 32)
 ir = IR()
 instr = Instr()
 res = test(ir, instr, a, b, c)
@@ -59,7 +59,7 @@ for statement in res[0]:
 print "[+] Blocks:"
 for irb in res[1]:
     print irb.label
-    for exprs in irb.irs:
-        for expr in exprs:
+    for assignblk in irb:
+        for expr in assignblk:
             print expr
         print
diff --git a/test/expression/expression.py b/test/expression/expression.py
index ac145a04..6bb6d94c 100644
--- a/test/expression/expression.py
+++ b/test/expression/expression.py
@@ -15,7 +15,7 @@ assert big_cst.size == 0x1000
 
 # Possible values
 #- Common constants
-A = ExprId("A")
+A = ExprId("A", 32)
 cond1 = ExprId("cond1", 1)
 cond2 = ExprId("cond2", 16)
 cst1 = ExprInt(1, 32)
diff --git a/test/expression/expression_helper.py b/test/expression/expression_helper.py
index a4c221e9..35873ca4 100755
--- a/test/expression/expression_helper.py
+++ b/test/expression/expression_helper.py
@@ -12,8 +12,8 @@ class TestExpressionExpressionHelper(unittest.TestCase):
 
         # Build a complex expression
         cst = m2_expr.ExprInt(0x100, 16)
-        eax = m2_expr.ExprId("EAX")
-        ebx = m2_expr.ExprId("EBX")
+        eax = m2_expr.ExprId("EAX", 32)
+        ebx = m2_expr.ExprId("EBX", 32)
         ax = eax[0:16]
         expr = eax + ebx
         expr = m2_expr.ExprCompose(ax, expr[16:32])
diff --git a/test/expression/simplifications.py b/test/expression/simplifications.py
index 6d17db10..b4f5b783 100644
--- a/test/expression/simplifications.py
+++ b/test/expression/simplifications.py
@@ -8,11 +8,11 @@ from miasm2.expression.simplifications import expr_simp, ExpressionSimplifier
 from miasm2.expression.simplifications_cond import ExprOp_inf_signed, ExprOp_inf_unsigned, ExprOp_equal
 
 # Define example objects
-a = ExprId('a')
-b = ExprId('b')
-c = ExprId('c')
-d = ExprId('d')
-e = ExprId('e')
+a = ExprId('a', 32)
+b = ExprId('b', 32)
+c = ExprId('c', 32)
+d = ExprId('d', 32)
+e = ExprId('e', 32)
 f = ExprId('f', size=64)
 
 m = ExprMem(a)
@@ -382,17 +382,17 @@ for e, e_check in to_test[:]:
 
 
 
-x = ExprId('x')
-y = ExprId('y')
-z = ExprId('z')
-a = ExprId('a')
-b = ExprId('b')
-c = ExprId('c')
+x = ExprId('x', 32)
+y = ExprId('y', 32)
+z = ExprId('z', 32)
+a = ExprId('a', 32)
+b = ExprId('b', 32)
+c = ExprId('c', 32)
 
 
-jra = ExprId('jra')
-jrb = ExprId('jrb')
-jrint1 = ExprId('jrint1')
+jra = ExprId('jra', 32)
+jrb = ExprId('jrb', 32)
+jrint1 = ExprId('jrint1', 32)
 
 
 e1 = ExprMem((a & ExprInt(0xFFFFFFFC, 32)) + ExprInt(0x10, 32), 32)
diff --git a/test/ir/ir.py b/test/ir/ir.py
index 05936d75..3774e4e9 100644
--- a/test/ir/ir.py
+++ b/test/ir/ir.py
@@ -2,8 +2,8 @@ from miasm2.expression.expression import *
 from miasm2.ir.ir import AssignBlock
 from miasm2.expression.simplifications import expr_simp
 
-id_a = ExprId("a")
-id_b = ExprId("b")
+id_a = ExprId("a", 32)
+id_b = ExprId("b", 32)
 int0 = ExprInt(0, id_a.size)
 
 # Test AssignBlock
diff --git a/test/ir/symbexec.py b/test/ir/symbexec.py
index f8d8c7bf..492dcfec 100755
--- a/test/ir/symbexec.py
+++ b/test/ir/symbexec.py
@@ -30,10 +30,10 @@ class TestSymbExec(unittest.TestCase):
         mem40w = ExprMem(addr40, 16)
         mem50v = ExprMem(addr50,  8)
         mem50w = ExprMem(addr50, 16)
-        id_x = ExprId('x')
+        id_x = ExprId('x', 32)
         id_y = ExprId('y', 8)
-        id_a = ExprId('a')
-        id_eax = ExprId('eax_init')
+        id_a = ExprId('a', 32)
+        id_eax = ExprId('eax_init', 32)
 
         e = SymbolicExecutionEngine(ir_x86_32(),
                                     {mem0: id_x, mem1: id_y, mem9: id_x,
diff --git a/test/test_all.py b/test/test_all.py
index 23937366..04aca62e 100755
--- a/test/test_all.py
+++ b/test/test_all.py
@@ -79,6 +79,7 @@ for script in ["x86/sem.py",
                "x86/unit/mn_pextr.py",
                "x86/unit/mn_pmovmskb.py",
                "x86/unit/mn_pushpop.py",
+               "x86/unit/mn_cdq.py",
                "x86/unit/mn_seh.py",
                "x86/unit/mn_cpuid.py",
                "x86/unit/mn_div.py",