diff options
Diffstat (limited to 'test')
39 files changed, 1152 insertions, 849 deletions
diff --git a/test/analysis/data_flow.py b/test/analysis/data_flow.py index d0a85e13..d0dbbd8d 100644 --- a/test/analysis/data_flow.py +++ b/test/analysis/data_flow.py @@ -1,10 +1,12 @@ """ Test cases for dead code elimination""" from miasm2.expression.expression import ExprId, ExprInt, ExprAff, ExprMem -from miasm2.core.asmblock import AsmLabel +from miasm2.core.locationdb import LocationDB from miasm2.analysis.data_flow import * from miasm2.ir.analysis import ira from miasm2.ir.ir import IRBlock, AssignBlock +loc_db = LocationDB() + a = ExprId("a", 32) b = ExprId("b", 32) c = ExprId("c", 32) @@ -24,13 +26,13 @@ CST1 = ExprInt(0x11, 32) CST2 = ExprInt(0x12, 32) CST3 = ExprInt(0x13, 32) -LBL0 = AsmLabel("lbl0") -LBL1 = AsmLabel("lbl1") -LBL2 = AsmLabel("lbl2") -LBL3 = AsmLabel("lbl3") -LBL4 = AsmLabel("lbl4") -LBL5 = AsmLabel("lbl5") -LBL6 = AsmLabel("lbl6") +LBL0 = loc_db.add_location("lbl0", 0) +LBL1 = loc_db.add_location("lbl1", 1) +LBL2 = loc_db.add_location("lbl2", 2) +LBL3 = loc_db.add_location("lbl3", 3) +LBL4 = loc_db.add_location("lbl4", 4) +LBL5 = loc_db.add_location("lbl5", 5) +LBL6 = loc_db.add_location("lbl6", 6) IRDst = ExprId('IRDst', 32) dummy = ExprId('dummy', 32) @@ -66,117 +68,122 @@ class IRATest(ira): """Fake IRA class for tests""" - def __init__(self, symbol_pool=None): + def __init__(self, loc_db=None): arch = Arch() - super(IRATest, self).__init__(arch, 32, symbol_pool) + super(IRATest, self).__init__(arch, 32, loc_db) self.IRDst = IRDst self.ret_reg = r def get_out_regs(self, _): return set([self.ret_reg, self.sp]) +IRA = IRATest(loc_db) + # graph 1 : Simple graph with dead and alive variables -G1_IRA = IRATest() +G1_IRA = IRA.new_ircfg() G1_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(b, CST2)]]) G1_IRB1 = gen_irblock(LBL1, [[ExprAff(a, b)]]) G1_IRB2 = gen_irblock(LBL2, [[ExprAff(r, a)]]) -G1_IRA.blocks = {irb.label : irb for irb in [G1_IRB0, G1_IRB1, G1_IRB2]} +for irb in [G1_IRB0, G1_IRB1, G1_IRB2]: + G1_IRA.add_irblock(irb) -G1_IRA.graph.add_uniq_edge(G1_IRB0.label, G1_IRB1.label) -G1_IRA.graph.add_uniq_edge(G1_IRB1.label, G1_IRB2.label) +G1_IRA.add_uniq_edge(G1_IRB0.loc_key, G1_IRB1.loc_key) +G1_IRA.add_uniq_edge(G1_IRB1.loc_key, G1_IRB2.loc_key) # Expected output for graph 1 -G1_EXP_IRA = IRATest() +G1_EXP_IRA = IRA.new_ircfg() G1_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAff(b, CST2)]]) G1_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(a, b)]]) G1_EXP_IRB2 = gen_irblock(LBL2, [[ExprAff(r, a)]]) -G1_EXP_IRA.blocks = {irb.label : irb for irb in [G1_EXP_IRB0, G1_EXP_IRB1, - G1_EXP_IRB2]} +for irb in [G1_EXP_IRB0, G1_EXP_IRB1, G1_EXP_IRB2]: + G1_EXP_IRA.add_irblock(irb) # graph 2 : Natural loop with dead variable -G2_IRA = IRATest() +G2_IRA = IRA.new_ircfg() G2_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(r, CST1)]]) G2_IRB1 = gen_irblock(LBL1, [[ExprAff(a, a+CST1)]]) G2_IRB2 = gen_irblock(LBL2, [[ExprAff(a, r)]]) -G2_IRA.blocks = {irb.label : irb for irb in [G2_IRB0, G2_IRB1, G2_IRB2]} +for irb in [G2_IRB0, G2_IRB1, G2_IRB2]: + G2_IRA.add_irblock(irb) -G2_IRA.graph.add_uniq_edge(G2_IRB0.label, G2_IRB1.label) -G2_IRA.graph.add_uniq_edge(G2_IRB1.label, G2_IRB2.label) -G2_IRA.graph.add_uniq_edge(G2_IRB1.label, G2_IRB1.label) +G2_IRA.add_uniq_edge(G2_IRB0.loc_key, G2_IRB1.loc_key) +G2_IRA.add_uniq_edge(G2_IRB1.loc_key, G2_IRB2.loc_key) +G2_IRA.add_uniq_edge(G2_IRB1.loc_key, G2_IRB1.loc_key) # Expected output for graph 2 -G2_EXP_IRA = IRATest() +G2_EXP_IRA = IRA.new_ircfg() G2_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAff(r, CST1)]]) G2_EXP_IRB1 = gen_irblock(LBL1, [[]]) G2_EXP_IRB2 = gen_irblock(LBL2, [[]]) -G2_EXP_IRA.blocks = {irb.label : irb for irb in [G2_EXP_IRB0, G2_EXP_IRB1, - G2_EXP_IRB2]} +for irb in [G2_EXP_IRB0, G2_EXP_IRB1, G2_EXP_IRB2]: + G2_EXP_IRA.add_irblock(irb) # graph 3 : Natural loop with alive variables -G3_IRA = IRATest() +G3_IRA = IRA.new_ircfg() G3_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)]]) G3_IRB1 = gen_irblock(LBL1, [[ExprAff(a, a+CST1)]]) G3_IRB2 = gen_irblock(LBL2, [[ExprAff(r, a)]]) -G3_IRA.blocks = {irb.label : irb for irb in [G3_IRB0, G3_IRB1, G3_IRB2]} +for irb in [G3_IRB0, G3_IRB1, G3_IRB2]: + G3_IRA.add_irblock(irb) -G3_IRA.graph.add_uniq_edge(G3_IRB0.label, G3_IRB1.label) -G3_IRA.graph.add_uniq_edge(G3_IRB1.label, G3_IRB2.label) -G3_IRA.graph.add_uniq_edge(G3_IRB1.label, G3_IRB1.label) +G3_IRA.add_uniq_edge(G3_IRB0.loc_key, G3_IRB1.loc_key) +G3_IRA.add_uniq_edge(G3_IRB1.loc_key, G3_IRB2.loc_key) +G3_IRA.add_uniq_edge(G3_IRB1.loc_key, G3_IRB1.loc_key) # Expected output for graph 3 -G3_EXP_IRA = IRATest() +G3_EXP_IRA = IRA.new_ircfg() G3_EXP_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)]]) G3_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(a, a+CST1)]]) G3_EXP_IRB2 = gen_irblock(LBL2, [[ExprAff(r, a)]]) -G3_EXP_IRA.blocks = {irb.label : irb for irb in [G3_EXP_IRB0, G3_EXP_IRB1, - G3_EXP_IRB2]} +for irb in [G3_EXP_IRB0, G3_EXP_IRB1, G3_EXP_IRB2]: + G3_EXP_IRA.add_irblock(irb) # graph 4 : If/else with dead variables -G4_IRA = IRATest() +G4_IRA = IRA.new_ircfg() G4_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)]]) G4_IRB1 = gen_irblock(LBL1, [[ExprAff(a, a+CST1)]]) G4_IRB2 = gen_irblock(LBL2, [[ExprAff(a, a+CST2)]]) G4_IRB3 = gen_irblock(LBL3, [[ExprAff(a, CST3)], [ExprAff(r, a)]]) -G4_IRA.blocks = {irb.label : irb for irb in [G4_IRB0, G4_IRB1, G4_IRB2, - G4_IRB3]} +for irb in [G4_IRB0, G4_IRB1, G4_IRB2, G4_IRB3]: + G4_IRA.add_irblock(irb) -G4_IRA.graph.add_uniq_edge(G4_IRB0.label, G4_IRB1.label) -G4_IRA.graph.add_uniq_edge(G4_IRB0.label, G4_IRB2.label) -G4_IRA.graph.add_uniq_edge(G4_IRB1.label, G4_IRB3.label) -G4_IRA.graph.add_uniq_edge(G4_IRB2.label, G4_IRB3.label) +G4_IRA.add_uniq_edge(G4_IRB0.loc_key, G4_IRB1.loc_key) +G4_IRA.add_uniq_edge(G4_IRB0.loc_key, G4_IRB2.loc_key) +G4_IRA.add_uniq_edge(G4_IRB1.loc_key, G4_IRB3.loc_key) +G4_IRA.add_uniq_edge(G4_IRB2.loc_key, G4_IRB3.loc_key) # Expected output for graph 4 -G4_EXP_IRA = IRATest() +G4_EXP_IRA = IRA.new_ircfg() G4_EXP_IRB0 = gen_irblock(LBL0, [[]]) G4_EXP_IRB1 = gen_irblock(LBL1, [[]]) G4_EXP_IRB2 = gen_irblock(LBL2, [[]]) G4_EXP_IRB3 = gen_irblock(LBL3, [[ExprAff(a, CST3)], [ExprAff(r, a)]]) -G4_EXP_IRA.blocks = {irb.label : irb for irb in [G4_EXP_IRB0, G4_EXP_IRB1, - G4_EXP_IRB2, G4_EXP_IRB3]} +for irb in [G4_EXP_IRB0, G4_EXP_IRB1, G4_EXP_IRB2, G4_EXP_IRB3]: + G4_EXP_IRA.add_irblock(irb) # graph 5 : Loop and If/else with dead variables -G5_IRA = IRATest() +G5_IRA = IRA.new_ircfg() G5_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)]]) G5_IRB1 = gen_irblock(LBL1, [[ExprAff(r, CST2)]]) @@ -185,19 +192,19 @@ G5_IRB3 = gen_irblock(LBL3, [[ExprAff(a, a+CST3)]]) G5_IRB4 = gen_irblock(LBL4, [[ExprAff(a, a+CST1)]]) G5_IRB5 = gen_irblock(LBL5, [[ExprAff(a, r)]]) -G5_IRA.blocks = {irb.label : irb for irb in [G5_IRB0, G5_IRB1, G5_IRB2, G5_IRB3, - G5_IRB4, G5_IRB5]} +for irb in [G5_IRB0, G5_IRB1, G5_IRB2, G5_IRB3, G5_IRB4, G5_IRB5]: + G5_IRA.add_irblock(irb) -G5_IRA.graph.add_uniq_edge(G5_IRB0.label, G5_IRB1.label) -G5_IRA.graph.add_uniq_edge(G5_IRB1.label, G5_IRB2.label) -G5_IRA.graph.add_uniq_edge(G5_IRB1.label, G5_IRB3.label) -G5_IRA.graph.add_uniq_edge(G5_IRB2.label, G5_IRB4.label) -G5_IRA.graph.add_uniq_edge(G5_IRB3.label, G5_IRB4.label) -G5_IRA.graph.add_uniq_edge(G5_IRB4.label, G5_IRB5.label) -G5_IRA.graph.add_uniq_edge(G5_IRB4.label, G5_IRB1.label) +G5_IRA.add_uniq_edge(G5_IRB0.loc_key, G5_IRB1.loc_key) +G5_IRA.add_uniq_edge(G5_IRB1.loc_key, G5_IRB2.loc_key) +G5_IRA.add_uniq_edge(G5_IRB1.loc_key, G5_IRB3.loc_key) +G5_IRA.add_uniq_edge(G5_IRB2.loc_key, G5_IRB4.loc_key) +G5_IRA.add_uniq_edge(G5_IRB3.loc_key, G5_IRB4.loc_key) +G5_IRA.add_uniq_edge(G5_IRB4.loc_key, G5_IRB5.loc_key) +G5_IRA.add_uniq_edge(G5_IRB4.loc_key, G5_IRB1.loc_key) # Expected output for graph 5 -G5_EXP_IRA = IRATest() +G5_EXP_IRA = IRA.new_ircfg() G5_EXP_IRB0 = gen_irblock(LBL0, [[]]) G5_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(r, CST2)]]) @@ -206,72 +213,72 @@ G5_EXP_IRB3 = gen_irblock(LBL3, [[]]) G5_EXP_IRB4 = gen_irblock(LBL4, [[]]) G5_EXP_IRB5 = gen_irblock(LBL5, [[]]) -G5_EXP_IRA.blocks = {irb.label : irb for irb in [G5_EXP_IRB0, G5_EXP_IRB1, - G5_EXP_IRB2, G5_EXP_IRB3, - G5_EXP_IRB4, G5_EXP_IRB5]} +for irb in [G5_EXP_IRB0, G5_EXP_IRB1, G5_EXP_IRB2, + G5_EXP_IRB3, G5_EXP_IRB4, G5_EXP_IRB5]: + G5_EXP_IRA.add_irblock(irb) # graph 6 : Natural loop with dead variables symetric affectation # (a = b <-> b = a ) -G6_IRA = IRATest() +G6_IRA = IRA.new_ircfg() G6_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)]]) G6_IRB1 = gen_irblock(LBL1, [[ExprAff(b, a)]]) G6_IRB2 = gen_irblock(LBL2, [[ExprAff(a, b)]]) G6_IRB3 = gen_irblock(LBL3, [[ExprAff(r, CST2)]]) -G6_IRA.blocks = {irb.label : irb for irb in [G6_IRB0, G6_IRB1, G6_IRB2, - G6_IRB3]} +for irb in [G6_IRB0, G6_IRB1, G6_IRB2, G6_IRB3]: + G6_IRA.add_irblock(irb) -G6_IRA.graph.add_uniq_edge(G6_IRB0.label, G6_IRB1.label) -G6_IRA.graph.add_uniq_edge(G6_IRB1.label, G6_IRB2.label) -G6_IRA.graph.add_uniq_edge(G6_IRB2.label, G6_IRB1.label) -G6_IRA.graph.add_uniq_edge(G6_IRB2.label, G6_IRB3.label) +G6_IRA.add_uniq_edge(G6_IRB0.loc_key, G6_IRB1.loc_key) +G6_IRA.add_uniq_edge(G6_IRB1.loc_key, G6_IRB2.loc_key) +G6_IRA.add_uniq_edge(G6_IRB2.loc_key, G6_IRB1.loc_key) +G6_IRA.add_uniq_edge(G6_IRB2.loc_key, G6_IRB3.loc_key) # Expected output for graph 6 -G6_EXP_IRA = IRATest() +G6_EXP_IRA = IRA.new_ircfg() G6_EXP_IRB0 = gen_irblock(LBL0, [[]]) G6_EXP_IRB1 = gen_irblock(LBL1, [[]]) G6_EXP_IRB2 = gen_irblock(LBL2, [[]]) G6_EXP_IRB3 = gen_irblock(LBL3, [[ExprAff(r, CST2)]]) -G6_EXP_IRA.blocks = {irb.label : irb for irb in [G6_EXP_IRB0, G6_EXP_IRB1, - G6_EXP_IRB2, G6_EXP_IRB3]} +for irb in [G6_EXP_IRB0, G6_EXP_IRB1, G6_EXP_IRB2, G6_EXP_IRB3]: + G6_EXP_IRA.add_irblock(irb) # graph 7 : Double entry loop with dead variables -G7_IRA = IRATest() +G7_IRA = IRA.new_ircfg() G7_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(r, CST1)]]) G7_IRB1 = gen_irblock(LBL1, [[ExprAff(a, a+CST1)]]) G7_IRB2 = gen_irblock(LBL2, [[ExprAff(a, a+CST2)]]) G7_IRB3 = gen_irblock(LBL3, [[ExprAff(a, r)]]) -G7_IRA.blocks = {irb.label : irb for irb in [G7_IRB0, G7_IRB1, G7_IRB2, - G7_IRB3]} +for irb in [G7_IRB0, G7_IRB1, G7_IRB2, G7_IRB3]: + G7_IRA.add_irblock(irb) -G7_IRA.graph.add_uniq_edge(G7_IRB0.label, G7_IRB1.label) -G7_IRA.graph.add_uniq_edge(G7_IRB1.label, G7_IRB2.label) -G7_IRA.graph.add_uniq_edge(G7_IRB2.label, G7_IRB1.label) -G7_IRA.graph.add_uniq_edge(G7_IRB2.label, G7_IRB3.label) -G7_IRA.graph.add_uniq_edge(G7_IRB0.label, G7_IRB2.label) +G7_IRA.add_uniq_edge(G7_IRB0.loc_key, G7_IRB1.loc_key) +G7_IRA.add_uniq_edge(G7_IRB1.loc_key, G7_IRB2.loc_key) +G7_IRA.add_uniq_edge(G7_IRB2.loc_key, G7_IRB1.loc_key) +G7_IRA.add_uniq_edge(G7_IRB2.loc_key, G7_IRB3.loc_key) +G7_IRA.add_uniq_edge(G7_IRB0.loc_key, G7_IRB2.loc_key) # Expected output for graph 7 -G7_EXP_IRA = IRATest() +G7_EXP_IRA = IRA.new_ircfg() G7_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAff(r, CST1)]]) G7_EXP_IRB1 = gen_irblock(LBL1, [[]]) G7_EXP_IRB2 = gen_irblock(LBL2, [[]]) G7_EXP_IRB3 = gen_irblock(LBL3, [[]]) -G7_EXP_IRA.blocks = {irb.label : irb for irb in [G7_EXP_IRB0, G7_EXP_IRB1, - G7_EXP_IRB2, G7_EXP_IRB3]} +for irb in [G7_EXP_IRB0, G7_EXP_IRB1, G7_EXP_IRB2, G7_EXP_IRB3]: + G7_EXP_IRA.add_irblock(irb) # graph 8 : Nested loops with dead variables -G8_IRA = IRATest() +G8_IRA = IRA.new_ircfg() G8_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(b, CST1)]]) G8_IRB1 = gen_irblock(LBL1, [[ExprAff(a, a+CST1)]]) @@ -279,31 +286,31 @@ G8_IRB2 = gen_irblock(LBL2, [[ExprAff(b, b+CST2)]]) G8_IRB3 = gen_irblock(LBL3, [[ExprAff(a, b)]]) -G8_IRA.blocks = {irb.label : irb for irb in [G8_IRB0, G8_IRB1, G8_IRB2, - G8_IRB3]} +for irb in [G8_IRB0, G8_IRB1, G8_IRB2, G8_IRB3]: + G8_IRA.add_irblock(irb) -G8_IRA.graph.add_uniq_edge(G8_IRB0.label, G8_IRB1.label) -G8_IRA.graph.add_uniq_edge(G8_IRB1.label, G8_IRB2.label) -G8_IRA.graph.add_uniq_edge(G8_IRB2.label, G8_IRB1.label) -G8_IRA.graph.add_uniq_edge(G8_IRB2.label, G8_IRB3.label) -G8_IRA.graph.add_uniq_edge(G8_IRB3.label, G8_IRB2.label) +G8_IRA.add_uniq_edge(G8_IRB0.loc_key, G8_IRB1.loc_key) +G8_IRA.add_uniq_edge(G8_IRB1.loc_key, G8_IRB2.loc_key) +G8_IRA.add_uniq_edge(G8_IRB2.loc_key, G8_IRB1.loc_key) +G8_IRA.add_uniq_edge(G8_IRB2.loc_key, G8_IRB3.loc_key) +G8_IRA.add_uniq_edge(G8_IRB3.loc_key, G8_IRB2.loc_key) # Expected output for graph 8 -G8_EXP_IRA = IRATest() +G8_EXP_IRA = IRA.new_ircfg() G8_EXP_IRB0 = gen_irblock(LBL0, [[], []]) G8_EXP_IRB1 = gen_irblock(LBL1, [[]]) G8_EXP_IRB2 = gen_irblock(LBL2, [[]]) G8_EXP_IRB3 = gen_irblock(LBL3, [[]]) -G8_EXP_IRA.blocks = {irb.label : irb for irb in [G8_EXP_IRB0, G8_EXP_IRB1, - G8_EXP_IRB2, G8_EXP_IRB3]} +for irb in [G8_EXP_IRB0, G8_EXP_IRB1, G8_EXP_IRB2, G8_EXP_IRB3]: + G8_EXP_IRA.add_irblock(irb) # graph 9 : Miultiple-exits loops with dead variables -G9_IRA = IRATest() +G9_IRA = IRA.new_ircfg() G9_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(b, CST1)]]) G9_IRB1 = gen_irblock(LBL1, [[ExprAff(a, a+CST1)], [ExprAff(b, b+CST1)]]) @@ -311,22 +318,22 @@ G9_IRB2 = gen_irblock(LBL2, [[ExprAff(a, a+CST2)], [ExprAff(b, b+CST2)]]) G9_IRB3 = gen_irblock(LBL3, [[ExprAff(a, b)]]) G9_IRB4 = gen_irblock(LBL4, [[ExprAff(r, a)], [ExprAff(r, b)]]) -G9_IRA.blocks = {irb.label : irb for irb in [G9_IRB0, G9_IRB1, G9_IRB2, - G9_IRB3, G9_IRB4]} +for irb in [G9_IRB0, G9_IRB1, G9_IRB2, G9_IRB3, G9_IRB4]: + G9_IRA.add_irblock(irb) -G9_IRA.graph.add_uniq_edge(G9_IRB0.label, G9_IRB4.label) -G9_IRA.graph.add_uniq_edge(G9_IRB0.label, G9_IRB1.label) -G9_IRA.graph.add_uniq_edge(G9_IRB1.label, G9_IRB0.label) -G9_IRA.graph.add_uniq_edge(G9_IRB1.label, G9_IRB4.label) -G9_IRA.graph.add_uniq_edge(G9_IRB1.label, G9_IRB2.label) -G9_IRA.graph.add_uniq_edge(G9_IRB2.label, G9_IRB0.label) -G9_IRA.graph.add_uniq_edge(G9_IRB2.label, G9_IRB3.label) -G9_IRA.graph.add_uniq_edge(G9_IRB3.label, G9_IRB4.label) +G9_IRA.add_uniq_edge(G9_IRB0.loc_key, G9_IRB4.loc_key) +G9_IRA.add_uniq_edge(G9_IRB0.loc_key, G9_IRB1.loc_key) +G9_IRA.add_uniq_edge(G9_IRB1.loc_key, G9_IRB0.loc_key) +G9_IRA.add_uniq_edge(G9_IRB1.loc_key, G9_IRB4.loc_key) +G9_IRA.add_uniq_edge(G9_IRB1.loc_key, G9_IRB2.loc_key) +G9_IRA.add_uniq_edge(G9_IRB2.loc_key, G9_IRB0.loc_key) +G9_IRA.add_uniq_edge(G9_IRB2.loc_key, G9_IRB3.loc_key) +G9_IRA.add_uniq_edge(G9_IRB3.loc_key, G9_IRB4.loc_key) # Expected output for graph 9 -G9_EXP_IRA = IRATest() +G9_EXP_IRA = IRA.new_ircfg() G9_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAff(b, CST1)]]) G9_EXP_IRB1 = gen_irblock(LBL1, [[], [ExprAff(b, b+CST1)]]) @@ -334,42 +341,42 @@ G9_EXP_IRB2 = gen_irblock(LBL2, [[], [ExprAff(b, b+CST2)]]) G9_EXP_IRB3 = gen_irblock(LBL3, [[]]) G9_EXP_IRB4 = gen_irblock(LBL4, [[], [ExprAff(r, b)]]) -G9_EXP_IRA.blocks = {irb.label : irb for irb in [G9_EXP_IRB0, G9_EXP_IRB1, - G9_EXP_IRB2, G9_EXP_IRB3, - G9_EXP_IRB4]} +for irb in [G9_EXP_IRB0, G9_EXP_IRB1, G9_EXP_IRB2, G9_EXP_IRB3, G9_EXP_IRB4]: + G9_EXP_IRA.add_irblock(irb) # graph 10 : Natural loop with alive variables symetric affectation # (a = b <-> b = a ) -G10_IRA = IRATest() +G10_IRA = IRA.new_ircfg() G10_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)]]) G10_IRB1 = gen_irblock(LBL1, [[ExprAff(b, a)]]) G10_IRB2 = gen_irblock(LBL2, [[ExprAff(a, b)]]) G10_IRB3 = gen_irblock(LBL3, [[ExprAff(r, CST1)]]) -G10_IRA.blocks = {irb.label : irb for irb in [G10_IRB0, G10_IRB1, - G10_IRB2, G10_IRB3]} +for irb in [G10_IRB0, G10_IRB1, G10_IRB2, G10_IRB3]: + G10_IRA.add_irblock(irb) + -G10_IRA.graph.add_uniq_edge(G10_IRB0.label, G10_IRB1.label) -G10_IRA.graph.add_uniq_edge(G10_IRB1.label, G10_IRB2.label) -G10_IRA.graph.add_uniq_edge(G10_IRB2.label, G10_IRB1.label) -G10_IRA.graph.add_uniq_edge(G10_IRB2.label, G10_IRB3.label) +G10_IRA.add_uniq_edge(G10_IRB0.loc_key, G10_IRB1.loc_key) +G10_IRA.add_uniq_edge(G10_IRB1.loc_key, G10_IRB2.loc_key) +G10_IRA.add_uniq_edge(G10_IRB2.loc_key, G10_IRB1.loc_key) +G10_IRA.add_uniq_edge(G10_IRB2.loc_key, G10_IRB3.loc_key) # Expected output for graph 10 -G10_EXP_IRA = IRATest() +G10_EXP_IRA = IRA.new_ircfg() G10_EXP_IRB0 = gen_irblock(LBL0, [[]]) G10_EXP_IRB1 = gen_irblock(LBL1, [[]]) G10_EXP_IRB2 = gen_irblock(LBL2, [[]]) G10_EXP_IRB3 = gen_irblock(LBL3, [[ExprAff(r, CST1)]]) -G10_EXP_IRA.blocks = {irb.label : irb for irb in [G10_EXP_IRB0, G10_EXP_IRB1, - G10_EXP_IRB2, G10_EXP_IRB3]} +for irb in [G10_EXP_IRB0, G10_EXP_IRB1, G10_EXP_IRB2, G10_EXP_IRB3]: + G10_EXP_IRA.add_irblock(irb) # graph 11 : If/Else conditions with alive variables -G11_IRA = IRATest() +G11_IRA = IRA.new_ircfg() G11_IRB0 = gen_irblock(LBL0, [[ExprAff(a, b)]]) G11_IRB1 = gen_irblock(LBL1, [[ExprAff(b, a)]]) @@ -378,17 +385,18 @@ G11_IRB3 = gen_irblock(LBL3, [[ExprAff(a, a+CST1)]]) G11_IRB4 = gen_irblock(LBL4, [[ExprAff(b, b+CST1)]]) -G11_IRA.blocks = {irb.label : irb for irb in [G11_IRB0, G11_IRB1, G11_IRB2]} +for irb in [G11_IRB0, G11_IRB1, G11_IRB2]: + G11_IRA.add_irblock(irb) -G11_IRA.graph.add_uniq_edge(G11_IRB0.label, G11_IRB1.label) -#G11_IRA.graph.add_uniq_edge(G11_IRB3.label, G11_IRB1.label) -G11_IRA.graph.add_uniq_edge(G11_IRB1.label, G11_IRB0.label) -#G11_IRA.graph.add_uniq_edge(G11_IRB4.label, G11_IRB0.label) -G11_IRA.graph.add_uniq_edge(G11_IRB1.label, G11_IRB2.label) +G11_IRA.add_uniq_edge(G11_IRB0.loc_key, G11_IRB1.loc_key) +#G11_IRA.add_uniq_edge(G11_IRB3.loc_key, G11_IRB1.loc_key) +G11_IRA.add_uniq_edge(G11_IRB1.loc_key, G11_IRB0.loc_key) +#G11_IRA.add_uniq_edge(G11_IRB4.loc_key, G11_IRB0.loc_key) +G11_IRA.add_uniq_edge(G11_IRB1.loc_key, G11_IRB2.loc_key) # Expected output for graph 11 -G11_EXP_IRA = IRATest() +G11_EXP_IRA = IRA.new_ircfg() G11_EXP_IRB0 = gen_irblock(LBL0, [[ExprAff(a, b)]]) G11_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(b, a)]]) @@ -396,13 +404,14 @@ G11_EXP_IRB2 = gen_irblock(LBL2, [[ExprAff(r, a)]]) #G11_EXP_IRB3 = gen_irblock(LBL3, [[ExprAff(a, a+CST1)]]) #G11_EXP_IRB4 = gen_irblock(LBL4, [[ExprAff(b, b+CST1)]]) -G11_EXP_IRA.blocks = {irb.label : irb for irb in [G11_EXP_IRB0, G11_EXP_IRB1, - G11_EXP_IRB2]} +for irb in [G11_EXP_IRB0, G11_EXP_IRB1, + G11_EXP_IRB2]: + G11_EXP_IRA.add_irblock(irb) # graph 12 : Graph with multiple out points and useless definitions # of return register -G12_IRA = IRATest() +G12_IRA = IRA.new_ircfg() G12_IRB0 = gen_irblock(LBL0, [[ExprAff(r, CST1)], [ExprAff(a, CST2)]]) G12_IRB1 = gen_irblock(LBL1, [[ExprAff(r, CST2)]]) @@ -411,17 +420,17 @@ G12_IRB3 = gen_irblock(LBL3, [[ExprAff(r, CST3)]]) G12_IRB4 = gen_irblock(LBL4, [[ExprAff(r, CST2)]]) G12_IRB5 = gen_irblock(LBL5, [[ExprAff(r, b)]]) -G12_IRA.blocks = {irb.label : irb for irb in [G12_IRB0, G12_IRB1, G12_IRB2, - G12_IRB3, G12_IRB4, G12_IRB5]} +for irb in [G12_IRB0, G12_IRB1, G12_IRB2, G12_IRB3, G12_IRB4, G12_IRB5]: + G12_IRA.add_irblock(irb) -G12_IRA.graph.add_uniq_edge(G12_IRB0.label, G12_IRB1.label) -G12_IRA.graph.add_uniq_edge(G12_IRB0.label, G12_IRB2.label) -G12_IRA.graph.add_uniq_edge(G12_IRB2.label, G12_IRB3.label) -G12_IRA.graph.add_uniq_edge(G12_IRB2.label, G12_IRB4.label) -G12_IRA.graph.add_uniq_edge(G12_IRB4.label, G12_IRB5.label) +G12_IRA.add_uniq_edge(G12_IRB0.loc_key, G12_IRB1.loc_key) +G12_IRA.add_uniq_edge(G12_IRB0.loc_key, G12_IRB2.loc_key) +G12_IRA.add_uniq_edge(G12_IRB2.loc_key, G12_IRB3.loc_key) +G12_IRA.add_uniq_edge(G12_IRB2.loc_key, G12_IRB4.loc_key) +G12_IRA.add_uniq_edge(G12_IRB4.loc_key, G12_IRB5.loc_key) # Expected output for graph 12 -G12_EXP_IRA = IRATest() +G12_EXP_IRA = IRA.new_ircfg() G12_EXP_IRB0 = gen_irblock(LBL0, [[], []]) G12_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(r, CST2)]]) @@ -431,13 +440,14 @@ G12_EXP_IRB4 = gen_irblock(LBL4, [[]]) G12_EXP_IRB5 = gen_irblock(LBL5, [[ExprAff(r, b)]]) -G12_EXP_IRA.blocks = {irb.label : irb for irb in [G12_EXP_IRB0, G12_EXP_IRB1, - G12_EXP_IRB2, G12_EXP_IRB3, - G12_EXP_IRB4, G12_EXP_IRB5]} +for irb in [G12_EXP_IRB0, G12_EXP_IRB1, + G12_EXP_IRB2, G12_EXP_IRB3, + G12_EXP_IRB4, G12_EXP_IRB5]: + G12_EXP_IRA.add_irblock(irb) # graph 13 : Graph where a leaf has lost its son -G13_IRA = IRATest() +G13_IRA = IRA.new_ircfg() G13_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(b, CST2)]]) G13_IRB1 = gen_irblock(LBL1, [[ExprAff(r, b)]]) @@ -446,16 +456,16 @@ G13_IRB2 = gen_irblock(LBL2, [[ExprAff(d, CST2)], [ExprAff(a, b+CST1), G13_IRB3 = gen_irblock(LBL3, [[]]) # lost son G13_IRB4 = gen_irblock(LBL4, [[ExprAff(b, CST2)]]) -G13_IRA.blocks = {irb.label : irb for irb in [G13_IRB0, G13_IRB1, G13_IRB2, - G13_IRB4]} +for irb in [G13_IRB0, G13_IRB1, G13_IRB2, G13_IRB4]: + G13_IRA.add_irblock(irb) -G13_IRA.graph.add_uniq_edge(G13_IRB0.label, G13_IRB1.label) -G13_IRA.graph.add_uniq_edge(G13_IRB0.label, G13_IRB4.label) -G13_IRA.graph.add_uniq_edge(G13_IRB2.label, G13_IRB3.label) -G13_IRA.graph.add_uniq_edge(G13_IRB4.label, G13_IRB2.label) +G13_IRA.add_uniq_edge(G13_IRB0.loc_key, G13_IRB1.loc_key) +G13_IRA.add_uniq_edge(G13_IRB0.loc_key, G13_IRB4.loc_key) +G13_IRA.add_uniq_edge(G13_IRB2.loc_key, G13_IRB3.loc_key) +G13_IRA.add_uniq_edge(G13_IRB4.loc_key, G13_IRB2.loc_key) # Expected output for graph 13 -G13_EXP_IRA = IRATest() +G13_EXP_IRA = IRA.new_ircfg() G13_EXP_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(b, CST2)]]) G13_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(r, b)]]) @@ -464,58 +474,62 @@ G13_EXP_IRB2 = gen_irblock(LBL2, [[ExprAff(d, CST2)], [ExprAff(a, b+CST1), G13_EXP_IRB3 = gen_irblock(LBL3, [[]]) G13_EXP_IRB4 = gen_irblock(LBL4, [[ExprAff(b, CST2)]]) -G13_EXP_IRA.blocks = {irb.label: irb for irb in [G13_EXP_IRB0, G13_EXP_IRB1, - G13_EXP_IRB2, G13_EXP_IRB4]} +for irb in [G13_EXP_IRB0, G13_EXP_IRB1, G13_EXP_IRB2, G13_EXP_IRB4]: + G13_EXP_IRA.add_irblock(irb) #G13_EXP_IRA = G13_IRA # graph 14 : Graph where variable assigned multiple times in a block but still # useful in the end -G14_IRA = IRATest() +G14_IRA = IRA.new_ircfg() G14_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(c, a)], [ExprAff(a, CST2)]]) G14_IRB1 = gen_irblock(LBL1, [[ExprAff(r, a+c)]]) -G14_IRA.blocks = {irb.label : irb for irb in [G14_IRB0, G14_IRB1]} +for irb in [G14_IRB0, G14_IRB1]: + G14_IRA.add_irblock(irb) -G14_IRA.graph.add_uniq_edge(G14_IRB0.label, G14_IRB1.label) +G14_IRA.add_uniq_edge(G14_IRB0.loc_key, G14_IRB1.loc_key) # Expected output for graph 1 -G14_EXP_IRA = IRATest() +G14_EXP_IRA = IRA.new_ircfg() G14_EXP_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1)], [ExprAff(c, a)], [ExprAff(a, CST2)]]) G14_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(r, a+c)]]) -G14_EXP_IRA.blocks = {irb.label: irb for irb in [G14_EXP_IRB0, G14_EXP_IRB1]} +for irb in [G14_EXP_IRB0, G14_EXP_IRB1]: + G14_EXP_IRA.add_irblock(irb) # graph 15 : Graph where variable assigned multiple and read at the same time, # but useless -G15_IRA = IRATest() +G15_IRA = IRA.new_ircfg() G15_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST2)], [ExprAff(a, CST1), ExprAff(b, a+CST2), ExprAff(c, CST1)]]) G15_IRB1 = gen_irblock(LBL1, [[ExprAff(r, a)]]) -G15_IRA.blocks = {irb.label : irb for irb in [G15_IRB0, G15_IRB1]} +for irb in [G15_IRB0, G15_IRB1]: + G15_IRA.add_irblock(irb) -G15_IRA.graph.add_uniq_edge(G15_IRB0.label, G15_IRB1.label) +G15_IRA.add_uniq_edge(G15_IRB0.loc_key, G15_IRB1.loc_key) # Expected output for graph 1 -G15_EXP_IRA = IRATest() +G15_EXP_IRA = IRA.new_ircfg() G15_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAff(a, CST1)]]) G15_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(r, a)]]) -G15_EXP_IRA.blocks = {irb.label: irb for irb in [G15_EXP_IRB0, G15_EXP_IRB1]} +for irb in [G15_EXP_IRB0, G15_EXP_IRB1]: + G15_EXP_IRA.add_irblock(irb) # graph 16 : Graph where variable assigned multiple times in the same bloc -G16_IRA = IRATest() +G16_IRA = IRA.new_ircfg() G16_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1), ExprAff(b, CST2), ExprAff(c, CST3)], [ExprAff(a, c+CST1), @@ -523,25 +537,28 @@ G16_IRB0 = gen_irblock(LBL0, [[ExprAff(a, CST1), ExprAff(b, CST2), G16_IRB1 = gen_irblock(LBL1, [[ExprAff(r, a+b)], [ExprAff(r, c+r)]]) G16_IRB2 = gen_irblock(LBL2, [[]]) -G16_IRA.blocks = {irb.label : irb for irb in [G16_IRB0, G16_IRB1]} +for irb in [G16_IRB0, G16_IRB1]: + G16_IRA.add_irblock(irb) -G16_IRA.graph.add_uniq_edge(G16_IRB0.label, G16_IRB1.label) -G16_IRA.graph.add_uniq_edge(G16_IRB1.label, G16_IRB2.label) +G16_IRA.add_uniq_edge(G16_IRB0.loc_key, G16_IRB1.loc_key) +G16_IRA.add_uniq_edge(G16_IRB1.loc_key, G16_IRB2.loc_key) -G16_IRA.blocks = {irb.label : irb for irb in [G16_IRB0, G16_IRB1]} +for irb in [G16_IRB0, G16_IRB1]: + G16_IRA.add_irblock(irb) # Expected output for graph 1 -G16_EXP_IRA = IRATest() +G16_EXP_IRA = IRA.new_ircfg() G16_EXP_IRB0 = gen_irblock(LBL0, [[ExprAff(c, CST3)], [ExprAff(a, c + CST1), ExprAff(b, c + CST2)]]) G16_EXP_IRB1 = gen_irblock(LBL1, [[ExprAff(r, a+b)], [ExprAff(r, c+r)]]) -G16_EXP_IRA.blocks = {irb.label: irb for irb in [G16_EXP_IRB0, G16_EXP_IRB1]} +for irb in [G16_EXP_IRB0, G16_EXP_IRB1]: + G16_EXP_IRA.add_irblock(irb) # graph 17 : parallel ir -G17_IRA = IRATest() +G17_IRA = IRA.new_ircfg() G17_IRB0 = gen_irblock(LBL0, [[ExprAff(a, a*b), ExprAff(b, c), @@ -597,12 +614,13 @@ G17_IRB0 = gen_irblock(LBL0, [[ExprAff(a, a*b), ]) -G17_IRA.blocks = {irb.label : irb for irb in [G17_IRB0]} +for irb in [G17_IRB0]: + G17_IRA.add_irblock(irb) -G17_IRA.graph.add_node(G17_IRB0.label) +#G17_IRA.graph.add_node(G17_IRB0.loc_key) # Expected output for graph 17 -G17_EXP_IRA = IRATest() +G17_EXP_IRA = IRA.new_ircfg() G17_EXP_IRB0 = gen_irblock(LBL0, [[], @@ -639,7 +657,8 @@ G17_EXP_IRB0 = gen_irblock(LBL0, [[], # Trick because a+b+c != ((a+b)+c) ]) -G17_EXP_IRA.blocks = {irb.label : irb for irb in [G17_EXP_IRB0]} +for irb in [G17_EXP_IRB0]: + G17_EXP_IRA.add_irblock(irb) # Begining of tests @@ -667,17 +686,16 @@ for test_nb, test in enumerate([(G1_IRA, G1_EXP_IRA), print "[+] Test", test_nb+1 # Print initial graph, for debug - open("graph_%02d.dot" % (test_nb+1), "w").write(g_ira.graph.dot()) + open("graph_%02d.dot" % (test_nb+1), "w").write(g_ira.dot()) reaching_defs = ReachingDefinitions(g_ira) defuse = DiGraphDefUse(reaching_defs, deref_mem=True) - #open("defuse_%02d.dot" % (test_nb+1), "w").write(defuse.dot()) # # Simplify graph - dead_simp(g_ira) + dead_simp(IRA, g_ira) # # Print simplified graph, for debug - open("simp_graph_%02d.dot" % (test_nb+1), "w").write(g_ira.graph.dot()) + open("simp_graph_%02d.dot" % (test_nb+1), "w").write(g_ira.dot()) # Same number of blocks assert len(g_ira.blocks) == len(g_exp_ira.blocks) diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py index 9fb046d0..2ba5f044 100644 --- a/test/analysis/depgraph.py +++ b/test/analysis/depgraph.py @@ -1,6 +1,7 @@ """Regression test module for DependencyGraph""" -from miasm2.expression.expression import ExprId, ExprInt, ExprAff, ExprCond -from miasm2.core.asmblock import AsmLabel +from miasm2.expression.expression import ExprId, ExprInt, ExprAff, ExprCond, \ + ExprLoc, LocKey +from miasm2.core.locationdb import LocationDB from miasm2.ir.analysis import ira from miasm2.ir.ir import IRBlock, AssignBlock from miasm2.core.graph import DiGraph @@ -9,6 +10,8 @@ from itertools import count from pdb import pm import re +loc_db = LocationDB() + EMULATION = True try: import z3 @@ -21,6 +24,7 @@ B = ExprId("b", 32) C = ExprId("c", 32) D = ExprId("d", 32) R = ExprId("r", 32) +COND = ExprId("cond", 32) A_INIT = ExprId("a_init", 32) B_INIT = ExprId("b_init", 32) @@ -41,13 +45,13 @@ CST33 = ExprInt(0x33, 32) CST35 = ExprInt(0x35, 32) CST37 = ExprInt(0x37, 32) -LBL0 = AsmLabel("lbl0") -LBL1 = AsmLabel("lbl1") -LBL2 = AsmLabel("lbl2") -LBL3 = AsmLabel("lbl3") -LBL4 = AsmLabel("lbl4") -LBL5 = AsmLabel("lbl5") -LBL6 = AsmLabel("lbl6") +LBL0 = loc_db.add_location("lbl0", 0) +LBL1 = loc_db.add_location("lbl1", 1) +LBL2 = loc_db.add_location("lbl2", 2) +LBL3 = loc_db.add_location("lbl3", 3) +LBL4 = loc_db.add_location("lbl4", 4) +LBL5 = loc_db.add_location("lbl5", 5) +LBL6 = loc_db.add_location("lbl6", 6) def gen_irblock(label, exprs_list): """ Returns an IRBlock. @@ -87,10 +91,10 @@ class IRATest(ira): """Fake IRA class for tests""" - def __init__(self, symbol_pool=None): + def __init__(self, loc_db=None): arch = Arch() - super(IRATest, self).__init__(arch, 32, symbol_pool) - self.IRDst = PC + super(IRATest, self).__init__(arch, 32, loc_db) + self.IRDst = ExprId("IRDst", 32) self.ret_reg = R def get_out_regs(self, _): @@ -111,18 +115,17 @@ def bloc2graph(irgraph, label=False, lines=True): # Generate basic blocks out_blocks = [] - for label in irgraph.graph.nodes(): - if isinstance(label, AsmLabel): - label_name = label.name - else: - label_name = str(label) + for label in irgraph.nodes(): + assert isinstance(label, LocKey) + label_names = irgraph.loc_db.get_location_names(label) + label_name = list(label_names)[0] if hasattr(irgraph, 'blocks'): irblock = irgraph.blocks[label] else: irblock = None - if isinstance(label, AsmLabel): - out_block = '%s [\n' % label.name + if isinstance(label, LocKey): + out_block = '%s [\n' % label_name else: out_block = '%s [\n' % label out_block += "%s " % block_attr @@ -151,20 +154,19 @@ def bloc2graph(irgraph, label=False, lines=True): out += out_blocks # Generate links - for src, dst in irgraph.graph.edges(): - if isinstance(src, AsmLabel): - src_name = src.name - else: - src_name = str(src) - if isinstance(dst, AsmLabel): - dst_name = dst.name - else: - dst_name = str(dst) + for src, dst in irgraph.edges(): + assert isinstance(src, LocKey) + src_names = irgraph.loc_db.get_location_names(src) + assert isinstance(dst, LocKey) + dst_names = irgraph.loc_db.get_location_names(dst) - edge_color = "black" - out.append('%s -> %s' % (src_name, - dst_name) + - '[' + edge_attr % ("", edge_color) + '];') + src_name = list(src_names)[0] + dst_name = list(dst_names)[0] + + edge_color = "black" + out.append('%s -> %s' % (src_name, + dst_name) + + '[' + edge_attr % ("", edge_color) + '];') out.append("}") return '\n'.join(out) @@ -184,19 +186,20 @@ def dg2graph(graph, label=False, lines=True): # Generate basic blocks out_blocks = [] - for label in graph.nodes(): - if isinstance(label, DependencyNode): - label_name = "%s %s %s" % (label.label.name, - label.element, - label.line_nb) + for node in graph.nodes(): + if isinstance(node, DependencyNode): + name = loc_db.pretty_str(node.loc_key) + node_name = "%s %s %s" % (name, + node.element, + node.line_nb) else: - label_name = str(label) - out_block = '%s [\n' % hash(label) + node_name = str(node) + out_block = '%s [\n' % hash(node) out_block += "%s " % block_attr out_block += 'label =<<table border="0" cellborder="0" cellpadding="3">' block_label = '<tr><td %s>%s</td></tr>' % ( - label_attr, label_name) + label_attr, node_name) block_html_lines = [] block_html_lines = ('<tr><td %s>' % td_attr + ('</td></tr><tr><td %s>' % td_attr).join(block_html_lines) + @@ -226,370 +229,476 @@ DNC2 = DependencyNode(LBL1, C, 0) DNB3 = DependencyNode(LBL1, B, 1) DNC3 = DependencyNode(LBL1, C, 0) +IRA = IRATest(loc_db) +IRDst = IRA.IRDst +END = ExprId("END", IRDst.size) # graph 1 -G1_IRA = IRATest() - -G1_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1)]]) -G1_IRB1 = gen_irblock(LBL1, [[ExprAff(B, C)]]) -G1_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B)]]) +G1_IRA = IRA.new_ircfg() -G1_IRA.graph.add_uniq_edge(G1_IRB0.label, G1_IRB1.label) -G1_IRA.graph.add_uniq_edge(G1_IRB1.label, G1_IRB2.label) +G1_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G1_IRB1 = gen_irblock(LBL1, [[ExprAff(B, C), ExprAff(IRDst, ExprLoc(LBL2, 32))]]) +G1_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B), ExprAff(IRDst, END)]]) -G1_IRA.blocks = dict([(irb.label, irb) for irb in [G1_IRB0, G1_IRB1, G1_IRB2]]) +for irb in [G1_IRB0, G1_IRB1, G1_IRB2]: + G1_IRA.add_irblock(irb) # graph 2 -G2_IRA = IRATest() +G2_IRA = IRA.new_ircfg() -G2_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1)]]) -G2_IRB1 = gen_irblock(LBL1, [[ExprAff(B, CST2)]]) -G2_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B + C)]]) +G2_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G2_IRB1 = gen_irblock(LBL1, [[ExprAff(B, CST2), ExprAff(IRDst, ExprLoc(LBL2, 32))]]) +G2_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B + C), ExprAff(IRDst, END)]]) -G2_IRA.graph.add_uniq_edge(G2_IRB0.label, G2_IRB1.label) -G2_IRA.graph.add_uniq_edge(G2_IRB1.label, G2_IRB2.label) - -G2_IRA.blocks = dict([(irb.label, irb) for irb in [G2_IRB0, G2_IRB1, G2_IRB2]]) +for irb in [G2_IRB0, G2_IRB1, G2_IRB2]: + G2_IRA.add_irblock(irb) # graph 3 -G3_IRA = IRATest() - -G3_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1)]]) -G3_IRB1 = gen_irblock(LBL1, [[ExprAff(B, CST2)]]) -G3_IRB2 = gen_irblock(LBL2, [[ExprAff(B, CST3)]]) -G3_IRB3 = gen_irblock(LBL3, [[ExprAff(A, B + C)]]) - -G3_IRA.graph.add_uniq_edge(G3_IRB0.label, G3_IRB1.label) -G3_IRA.graph.add_uniq_edge(G3_IRB0.label, G3_IRB2.label) -G3_IRA.graph.add_uniq_edge(G3_IRB1.label, G3_IRB3.label) -G3_IRA.graph.add_uniq_edge(G3_IRB2.label, G3_IRB3.label) - -G3_IRA.blocks = dict([(irb.label, irb) for irb in [G3_IRB0, G3_IRB1, - G3_IRB2, G3_IRB3]]) +G3_IRA = IRA.new_ircfg() + +G3_IRB0 = gen_irblock( + LBL0, + [ + [ExprAff(C, CST1), ExprAff( + IRDst, ExprCond( + COND, + ExprLoc(LBL1, 32), + ExprLoc(LBL2, 32) + ) + ) + ] + ] +) + +G3_IRB1 = gen_irblock(LBL1, [[ExprAff(B, CST2), ExprAff(IRDst, ExprLoc(LBL3, 32))]]) +G3_IRB2 = gen_irblock(LBL2, [[ExprAff(B, CST3), ExprAff(IRDst, ExprLoc(LBL3, 32))]]) +G3_IRB3 = gen_irblock(LBL3, [[ExprAff(A, B + C), ExprAff(IRDst, END)]]) + +for irb in [G3_IRB0, G3_IRB1, G3_IRB2, G3_IRB3]: + G3_IRA.add_irblock(irb) # graph 4 -G4_IRA = IRATest() - -G4_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1)]]) -G4_IRB1 = gen_irblock(LBL1, [[ExprAff(C, C + CST2)], - [ExprAff(G4_IRA.IRDst, - ExprCond(C, ExprId(LBL2, 32), - ExprId(LBL1, 32)))]]) +G4_IRA = IRA.new_ircfg() -G4_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B)]]) +G4_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G4_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(C, C + CST2)], + [ExprAff(IRDst, + ExprCond( + C, + ExprLoc(LBL2, 32), + ExprLoc(LBL1, 32)) + ) + ]] +) -G4_IRA.graph.add_uniq_edge(G4_IRB0.label, G4_IRB1.label) -G4_IRA.graph.add_uniq_edge(G4_IRB1.label, G4_IRB2.label) -G4_IRA.graph.add_uniq_edge(G4_IRB1.label, G4_IRB1.label) +G4_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B), ExprAff(IRDst, END)]]) -G4_IRA.blocks = dict([(irb.label, irb) for irb in [G4_IRB0, G4_IRB1, G4_IRB2]]) +for irb in [G4_IRB0, G4_IRB1, G4_IRB2]: + G4_IRA.add_irblock(irb) # graph 5 -G5_IRA = IRATest() - -G5_IRB0 = gen_irblock(LBL0, [[ExprAff(B, CST1)]]) -G5_IRB1 = gen_irblock(LBL1, [[ExprAff(B, B + CST2)], - [ExprAff(G5_IRA.IRDst, - ExprCond(B, ExprId(LBL2, 32), - ExprId(LBL1, 32)))]]) - -G5_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B)]]) - -G5_IRA.graph.add_uniq_edge(G5_IRB0.label, G5_IRB1.label) -G5_IRA.graph.add_uniq_edge(G5_IRB1.label, G5_IRB2.label) -G5_IRA.graph.add_uniq_edge(G5_IRB1.label, G5_IRB1.label) - -G5_IRA.blocks = dict([(irb.label, irb) for irb in [G5_IRB0, G5_IRB1, G5_IRB2]]) +G5_IRA = IRA.new_ircfg() + +G5_IRB0 = gen_irblock(LBL0, [[ExprAff(B, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G5_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(B, B + CST2)], + [ExprAff( + IRDst, + ExprCond( + B, + ExprLoc(LBL2, 32), + ExprLoc(LBL1, 32) + ) + ) + ] + ] +) + +G5_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B), ExprAff(IRDst, END)]]) + +for irb in [G5_IRB0, G5_IRB1, G5_IRB2]: + G5_IRA.add_irblock(irb) # graph 6 -G6_IRA = IRATest() +G6_IRA = IRA.new_ircfg() -G6_IRB0 = gen_irblock(LBL0, [[ExprAff(B, CST1)]]) -G6_IRB1 = gen_irblock(LBL1, [[ExprAff(A, B)]]) +G6_IRB0 = gen_irblock(LBL0, [[ExprAff(B, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G6_IRB1 = gen_irblock(LBL1, [[ExprAff(A, B), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) -G6_IRA.graph.add_uniq_edge(G6_IRB0.label, G6_IRB1.label) -G6_IRA.graph.add_uniq_edge(G6_IRB1.label, G6_IRB1.label) - -G6_IRA.blocks = dict([(irb.label, irb) for irb in [G6_IRB0, G6_IRB1]]) +for irb in [G6_IRB0, G6_IRB1]: + G6_IRA.add_irblock(irb) # graph 7 -G7_IRA = IRATest() - -G7_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1)]]) -G7_IRB1 = gen_irblock(LBL1, [[ExprAff(B, C)], [ExprAff(A, B)]]) -G7_IRB2 = gen_irblock(LBL2, [[ExprAff(D, A)]]) - -G7_IRA.graph.add_uniq_edge(G7_IRB0.label, G7_IRB1.label) -G7_IRA.graph.add_uniq_edge(G7_IRB1.label, G7_IRB1.label) -G7_IRA.graph.add_uniq_edge(G7_IRB1.label, G7_IRB2.label) - -G7_IRA.blocks = dict([(irb.label, irb) for irb in [G7_IRB0, G7_IRB1, G7_IRB2]]) +G7_IRA = IRA.new_ircfg() + +G7_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G7_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(B, C)], + [ExprAff(A, B)], + [ExprAff( + IRDst, + ExprCond( + COND, + ExprLoc(LBL1, 32), + ExprLoc(LBL2, 32) + ) + ) + ] + ] +) + +G7_IRB2 = gen_irblock(LBL2, [[ExprAff(D, A), ExprAff(IRDst, END)]]) + +for irb in [G7_IRB0, G7_IRB1, G7_IRB2]: + G7_IRA.add_irblock(irb) # graph 8 -G8_IRA = IRATest() - -G8_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1)]]) -G8_IRB1 = gen_irblock(LBL1, [[ExprAff(B, C)], [ExprAff(C, D)]]) -G8_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B)]]) - -G8_IRA.graph.add_uniq_edge(G8_IRB0.label, G8_IRB1.label) -G8_IRA.graph.add_uniq_edge(G8_IRB1.label, G8_IRB1.label) -G8_IRA.graph.add_uniq_edge(G8_IRB1.label, G8_IRB2.label) - -G8_IRA.blocks = dict([(irb.label, irb) for irb in [G8_IRB0, G8_IRB1, G8_IRB2]]) +G8_IRA = IRA.new_ircfg() + +G8_IRB0 = gen_irblock(LBL0, [[ExprAff(C, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G8_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(B, C)], + [ExprAff(C, D), + ExprAff( + IRDst, + ExprCond( + COND, + ExprLoc(LBL1, 32), + ExprLoc(LBL2, 32) + ) + ) + ] + ] +) +G8_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B), ExprAff(IRDst, END)]]) + +for irb in [G8_IRB0, G8_IRB1, G8_IRB2]: + G8_IRA.add_irblock(irb) # graph 9 is graph 8 # graph 10 -G10_IRA = IRATest() - -G10_IRB1 = gen_irblock(LBL1, [[ExprAff(B, B + CST2)]]) -G10_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B)]]) - -G10_IRA.graph.add_uniq_edge(G10_IRB1.label, G10_IRB2.label) -G10_IRA.graph.add_uniq_edge(G10_IRB1.label, G10_IRB1.label) - -G10_IRA.blocks = dict([(irb.label, irb) for irb in [G10_IRB1, G10_IRB2]]) +G10_IRA = IRA.new_ircfg() + +G10_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(B, B + CST2), + ExprAff( + IRDst, + ExprCond( + COND, + ExprLoc(LBL1, 32), + ExprLoc(LBL2, 32) + ) + ) + ] + ] +) + +G10_IRB2 = gen_irblock(LBL2, [[ExprAff(A, B), ExprAff(IRDst, END)]]) + +for irb in [G10_IRB1, G10_IRB2]: + G10_IRA.add_irblock(irb) # graph 11 -G11_IRA = IRATest() - -G11_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1), - ExprAff(B, CST2)]]) -G11_IRB1 = gen_irblock(LBL1, [[ExprAff(A, B), - ExprAff(B, A)]]) -G11_IRB2 = gen_irblock(LBL2, [[ExprAff(A, A - B)]]) - -G11_IRA.graph.add_uniq_edge(G11_IRB0.label, G11_IRB1.label) -G11_IRA.graph.add_uniq_edge(G11_IRB1.label, G11_IRB2.label) - -G11_IRA.blocks = dict([(irb.label, irb) - for irb in [G11_IRB0, G11_IRB1, G11_IRB2]]) +G11_IRA = IRA.new_ircfg() + +G11_IRB0 = gen_irblock( + LBL0, + [ + [ExprAff(A, CST1), + ExprAff(B, CST2), + ExprAff(IRDst, ExprLoc(LBL1, 32)) + ] + ] +) + +G11_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(A, B), + ExprAff(B, A), + ExprAff(IRDst, ExprLoc(LBL2, 32)) + ] + ] +) + +G11_IRB2 = gen_irblock(LBL2, [[ExprAff(A, A - B), ExprAff(IRDst, END)]]) + +for irb in [G11_IRB0, G11_IRB1, G11_IRB2]: + G11_IRA.add_irblock(irb) # graph 12 -G12_IRA = IRATest() +G12_IRA = IRA.new_ircfg() -G12_IRB0 = gen_irblock(LBL0, [[ExprAff(B, CST1)]]) -G12_IRB1 = gen_irblock(LBL1, [[ExprAff(A, B)], [ExprAff(B, B + CST2)]]) -G12_IRB2 = gen_irblock(LBL2, [[ExprAff(B, A)]]) +G12_IRB0 = gen_irblock(LBL0, [[ExprAff(B, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G12_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(A, B)], + [ExprAff(B, B + CST2), + ExprAff( + IRDst, + ExprCond( + COND, + ExprLoc(LBL1, 32), + ExprLoc(LBL2, 32) + ) + ) + ] + ] +) -G12_IRA.graph.add_uniq_edge(G12_IRB0.label, G12_IRB1.label) -G12_IRA.graph.add_uniq_edge(G12_IRB1.label, G12_IRB2.label) -G12_IRA.graph.add_uniq_edge(G12_IRB1.label, G12_IRB1.label) +G12_IRB2 = gen_irblock(LBL2, [[ExprAff(B, A), ExprAff(IRDst, END)]]) -G12_IRA.blocks = dict([(irb.label, irb) for irb in [G12_IRB0, G12_IRB1, - G12_IRB2]]) +for irb in [G12_IRB0, G12_IRB1, G12_IRB2]: + G12_IRA.add_irblock(irb) # graph 13 -G13_IRA = IRATest() +G13_IRA = IRA.new_ircfg() G13_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1)], #[ExprAff(B, A)], - [ExprAff(G13_IRA.IRDst, - ExprId(LBL1, 32))]]) + [ExprAff(IRDst, + ExprLoc(LBL1, 32))]]) G13_IRB1 = gen_irblock(LBL1, [[ExprAff(C, A)], #[ExprAff(A, A + CST1)], - [ExprAff(G13_IRA.IRDst, - ExprCond(R, ExprId(LBL2, 32), - ExprId(LBL1, 32)))]]) + [ExprAff(IRDst, + ExprCond( + R, + ExprLoc(LBL2, 32), + ExprLoc(LBL3, 32) + ) + )]]) G13_IRB2 = gen_irblock(LBL2, [[ExprAff(B, A + CST3)], [ExprAff(A, B + CST3)], - [ExprAff(G13_IRA.IRDst, - ExprId(LBL1, 32))]]) - -G13_IRB3 = gen_irblock(LBL3, [[ExprAff(R, C)]]) + [ExprAff(IRDst, + ExprLoc(LBL1, 32))]]) -G13_IRA.graph.add_uniq_edge(G13_IRB0.label, G13_IRB1.label) -G13_IRA.graph.add_uniq_edge(G13_IRB1.label, G13_IRB2.label) -G13_IRA.graph.add_uniq_edge(G13_IRB2.label, G13_IRB1.label) -G13_IRA.graph.add_uniq_edge(G13_IRB1.label, G13_IRB3.label) +G13_IRB3 = gen_irblock(LBL3, [[ExprAff(R, C), ExprAff(IRDst, END)]]) -G13_IRA.blocks = dict([(irb.label, irb) for irb in [G13_IRB0, G13_IRB1, - G13_IRB2, G13_IRB3]]) +for irb in [G13_IRB0, G13_IRB1, G13_IRB2, G13_IRB3]: + G13_IRA.add_irblock(irb) # graph 14 -G14_IRA = IRATest() +G14_IRA = IRA.new_ircfg() G14_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1)], - [ExprAff(G14_IRA.IRDst, - ExprId(LBL1, 32))] + [ExprAff(IRDst, + ExprLoc(LBL1, 32))] ]) G14_IRB1 = gen_irblock(LBL1, [[ExprAff(B, A)], - [ExprAff(G14_IRA.IRDst, - ExprCond(C, ExprId(LBL2, 32), - ExprId(LBL3, 32)))] + [ExprAff(IRDst, + ExprCond( + C, + ExprLoc(LBL2, 32), + ExprLoc(LBL3, 32) + ) + ) + ] ]) G14_IRB2 = gen_irblock(LBL2, [[ExprAff(D, A)], [ExprAff(A, D + CST1)], - [ExprAff(G14_IRA.IRDst, - ExprId(LBL1, 32))] + [ExprAff(IRDst, + ExprLoc(LBL1, 32))] ]) -G14_IRB3 = gen_irblock(LBL3, [[ExprAff(R, D + B)]]) - -G14_IRA.graph.add_uniq_edge(G14_IRB0.label, G14_IRB1.label) -G14_IRA.graph.add_uniq_edge(G14_IRB1.label, G14_IRB2.label) -G14_IRA.graph.add_uniq_edge(G14_IRB2.label, G14_IRB1.label) -G14_IRA.graph.add_uniq_edge(G14_IRB1.label, G14_IRB3.label) +G14_IRB3 = gen_irblock(LBL3, [[ExprAff(R, D + B), ExprAff(IRDst, END)]]) -G14_IRA.blocks = dict([(irb.label, irb) for irb in [G14_IRB0, G14_IRB1, - G14_IRB2, G14_IRB3]]) +for irb in [G14_IRB0, G14_IRB1, G14_IRB2, G14_IRB3]: + G14_IRA.add_irblock(irb) # graph 16 -G15_IRA = IRATest() +G15_IRA = IRA.new_ircfg() -G15_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1)]]) +G15_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) G15_IRB1 = gen_irblock(LBL1, [[ExprAff(D, A + B)], [ExprAff(C, D)], - [ExprAff(B, C)]]) -G15_IRB2 = gen_irblock(LBL2, [[ExprAff(R, B)]]) - -G15_IRA.graph.add_uniq_edge(G15_IRB0.label, G15_IRB1.label) -G15_IRA.graph.add_uniq_edge(G15_IRB1.label, G15_IRB2.label) -G15_IRA.graph.add_uniq_edge(G15_IRB1.label, G15_IRB1.label) - -G15_IRA.blocks = dict([(irb.label, irb) for irb in [G15_IRB0, G15_IRB1, - G15_IRB2]]) + [ExprAff(B, C), + ExprAff(IRDst, + ExprCond( + C, + ExprLoc(LBL1, 32), + ExprLoc(LBL2, 32) + ) + )]]) +G15_IRB2 = gen_irblock(LBL2, [[ExprAff(R, B), ExprAff(IRDst, END)]]) + +for irb in [G15_IRB0, G15_IRB1, G15_IRB2]: + G15_IRA.add_irblock(irb) # graph 16 -G16_IRA = IRATest() - -G16_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1)]]) -G16_IRB1 = gen_irblock(LBL1, [[ExprAff(R, D)]]) -G16_IRB2 = gen_irblock(LBL2, [[ExprAff(D, A)]]) -G16_IRB3 = gen_irblock(LBL3, [[ExprAff(R, D)]]) -G16_IRB4 = gen_irblock(LBL4, [[ExprAff(R, A)]]) -G16_IRB5 = gen_irblock(LBL5, [[ExprAff(R, A)]]) - -G16_IRA.graph.add_uniq_edge(G16_IRB0.label, G16_IRB1.label) -G16_IRA.graph.add_uniq_edge(G16_IRB1.label, G16_IRB2.label) -G16_IRA.graph.add_uniq_edge(G16_IRB2.label, G16_IRB1.label) -G16_IRA.graph.add_uniq_edge(G16_IRB1.label, G16_IRB3.label) -G16_IRA.graph.add_uniq_edge(G16_IRB3.label, G16_IRB1.label) -G16_IRA.graph.add_uniq_edge(G16_IRB1.label, G16_IRB4.label) -G16_IRA.graph.add_uniq_edge(G16_IRB4.label, G16_IRB1.label) -G16_IRA.graph.add_uniq_edge(G16_IRB1.label, G16_IRB5.label) - -G16_IRA.blocks = dict([(irb.label, irb) for irb in [G16_IRB0, G16_IRB1, - G16_IRB2, G16_IRB3, - G16_IRB4, G16_IRB5]]) +G16_IRA = IRA.new_ircfg() + +G16_IRB0 = gen_irblock( + LBL0, [ + [ExprAff(A, CST1), ExprAff(IRDst, ExprLoc(LBL1, 32))] + ] +) + +G16_IRB1 = gen_irblock( + LBL1, + [ + [ExprAff(R, D), + ExprAff( + IRDst, + ExprCond( + C, + ExprCond( + C, + ExprCond( + C, + ExprLoc(LBL2, 32), + ExprLoc(LBL3, 32) + ), + ExprLoc(LBL4, 32) + ), + ExprLoc(LBL5, 32) + ) + ) + ] + ] +) + + + +G16_IRB2 = gen_irblock(LBL2, [[ExprAff(D, A), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G16_IRB3 = gen_irblock(LBL3, [[ExprAff(R, D), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G16_IRB4 = gen_irblock(LBL4, [[ExprAff(R, A), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) +G16_IRB5 = gen_irblock(LBL5, [[ExprAff(R, A), ExprAff(IRDst, ExprLoc(LBL1, 32))]]) + +for irb in [G16_IRB0, G16_IRB1, G16_IRB2, G16_IRB3, G16_IRB4, G16_IRB5]: + G16_IRA.add_irblock(irb) # graph 17 -G17_IRA = IRATest() +G17_IRA = IRA.new_ircfg() G17_IRB0 = gen_irblock(LBL0, [[ExprAff(A, CST1), - ExprAff(D, CST2)]]) + ExprAff(D, CST2), + ExprAff(IRDst, ExprLoc(LBL1, 32))]]) G17_IRB1 = gen_irblock(LBL1, [[ExprAff(A, D), - ExprAff(B, D)]]) -G17_IRB2 = gen_irblock(LBL2, [[ExprAff(A, A - B)]]) + ExprAff(B, D), + ExprAff(IRDst, ExprLoc(LBL2, 32))]]) +G17_IRB2 = gen_irblock(LBL2, [[ExprAff(A, A - B), + ExprAff(IRDst, END)]]) -G17_IRA.graph.add_uniq_edge(G17_IRB0.label, G17_IRB1.label) -G17_IRA.graph.add_uniq_edge(G17_IRB1.label, G17_IRB2.label) +G17_IRA.add_uniq_edge(G17_IRB0.loc_key, G17_IRB1.loc_key) +G17_IRA.add_uniq_edge(G17_IRB1.loc_key, G17_IRB2.loc_key) -G17_IRA.blocks = dict([(irb.label, irb) for irb in [G17_IRB0, G17_IRB1, - G17_IRB2]]) +for irb in [G17_IRB0, G17_IRB1, G17_IRB2]: + G17_IRA.add_irblock(irb) # Test graph 1 G1_TEST1_DN1 = DependencyNode( - G1_IRB2.label, A, len(G1_IRB2)) + G1_IRB2.loc_key, A, len(G1_IRB2)) -G1_INPUT = (set([G1_TEST1_DN1]), set([G1_IRB0.label])) +G1_INPUT = (set([G1_TEST1_DN1]), set([G1_IRB0.loc_key])) # Test graph 2 G2_TEST1_DN1 = DependencyNode( - G2_IRB2.label, A, len(G2_IRB2)) + G2_IRB2.loc_key, A, len(G2_IRB2)) -G2_INPUT = (set([G2_TEST1_DN1]), set([G2_IRB0.label])) +G2_INPUT = (set([G2_TEST1_DN1]), set([G2_IRB0.loc_key])) # Test graph 3 G3_TEST1_0_DN1 = DependencyNode( - G3_IRB3.label, A, len(G3_IRB3)) + G3_IRB3.loc_key, A, len(G3_IRB3)) -G3_INPUT = (set([G3_TEST1_0_DN1]), set([G3_IRB0.label])) +G3_INPUT = (set([G3_TEST1_0_DN1]), set([G3_IRB0.loc_key])) # Test graph 4 G4_TEST1_DN1 = DependencyNode( - G4_IRB2.label, A, len(G2_IRB0)) + G4_IRB2.loc_key, A, len(G2_IRB0)) -G4_INPUT = (set([G4_TEST1_DN1]), set([G4_IRB0.label])) +G4_INPUT = (set([G4_TEST1_DN1]), set([G4_IRB0.loc_key])) # Test graph 5 G5_TEST1_0_DN1 = DependencyNode( - G5_IRB2.label, A, len(G5_IRB2)) + G5_IRB2.loc_key, A, len(G5_IRB2)) -G5_INPUT = (set([G5_TEST1_0_DN1]), set([G5_IRB0.label])) +G5_INPUT = (set([G5_TEST1_0_DN1]), set([G5_IRB0.loc_key])) # Test graph 6 G6_TEST1_0_DN1 = DependencyNode( - G6_IRB1.label, A, len(G6_IRB1)) + G6_IRB1.loc_key, A, len(G6_IRB1)) -G6_INPUT = (set([G6_TEST1_0_DN1]), set([G6_IRB0.label])) +G6_INPUT = (set([G6_TEST1_0_DN1]), set([G6_IRB0.loc_key])) # Test graph 7 G7_TEST1_0_DN1 = DependencyNode( - G7_IRB2.label, D, len(G7_IRB2)) + G7_IRB2.loc_key, D, len(G7_IRB2)) -G7_INPUT = (set([G7_TEST1_0_DN1]), set([G7_IRB0.label])) +G7_INPUT = (set([G7_TEST1_0_DN1]), set([G7_IRB0.loc_key])) # Test graph 8 G8_TEST1_0_DN1 = DependencyNode( - G8_IRB2.label, A, len(G8_IRB2)) + G8_IRB2.loc_key, A, len(G8_IRB2)) -G8_INPUT = (set([G8_TEST1_0_DN1]), set([G3_IRB0.label])) +G8_INPUT = (set([G8_TEST1_0_DN1]), set([G3_IRB0.loc_key])) # Test 9: Multi elements G9_TEST1_0_DN1 = DependencyNode( - G8_IRB2.label, A, len(G8_IRB2)) + G8_IRB2.loc_key, A, len(G8_IRB2)) G9_TEST1_0_DN5 = DependencyNode( - G8_IRB2.label, C, len(G8_IRB2)) + G8_IRB2.loc_key, C, len(G8_IRB2)) -G9_INPUT = (set([G9_TEST1_0_DN1, G9_TEST1_0_DN5]), set([G8_IRB0.label])) +G9_INPUT = (set([G9_TEST1_0_DN1, G9_TEST1_0_DN5]), set([G8_IRB0.loc_key])) # Test 10: loop at beginning G10_TEST1_0_DN1 = DependencyNode( - G10_IRB2.label, A, len(G10_IRB2)) + G10_IRB2.loc_key, A, len(G10_IRB2)) -G10_INPUT = (set([G10_TEST1_0_DN1]), set([G10_IRB1.label])) +G10_INPUT = (set([G10_TEST1_0_DN1]), set([G10_IRB1.loc_key])) # Test 11: no dual bloc emulation G11_TEST1_DN1 = DependencyNode( - G11_IRB2.label, A, len(G11_IRB2)) + G11_IRB2.loc_key, A, len(G11_IRB2)) -G11_INPUT = (set([G11_TEST1_DN1]), set([G11_IRB0.label])) +G11_INPUT = (set([G11_TEST1_DN1]), set([G11_IRB0.loc_key])) # Test graph 12 -G12_TEST1_0_DN1 = DependencyNode(G12_IRB2.label, B, 1) +G12_TEST1_0_DN1 = DependencyNode(G12_IRB2.loc_key, B, 1) G12_INPUT = (set([G12_TEST1_0_DN1]), set([])) @@ -597,7 +706,7 @@ G12_INPUT = (set([G12_TEST1_0_DN1]), set([])) # All filters -G13_TEST1_0_DN4 = DependencyNode(G13_IRB3.label, R, 1) +G13_TEST1_0_DN4 = DependencyNode(G13_IRB3.loc_key, R, 1) G13_INPUT = (set([G13_TEST1_0_DN4]), set([])) @@ -605,24 +714,24 @@ G13_INPUT = (set([G13_TEST1_0_DN4]), set([])) # All filters -G14_TEST1_0_DN1 = DependencyNode(G14_IRB3.label, R, 1) +G14_TEST1_0_DN1 = DependencyNode(G14_IRB3.loc_key, R, 1) G14_INPUT = (set([G14_TEST1_0_DN1]), set([])) # Test graph 15 -G15_TEST1_0_DN1 = DependencyNode(G15_IRB2.label, R, 1) +G15_TEST1_0_DN1 = DependencyNode(G15_IRB2.loc_key, R, 1) G15_INPUT = (set([G15_TEST1_0_DN1]), set([])) # Test graph 16 -G16_TEST1_0_DN1 = DependencyNode(G16_IRB5.label, R, 1) +G16_TEST1_0_DN1 = DependencyNode(G16_IRB5.loc_key, R, 1) G16_INPUT = (set([G16_TEST1_0_DN1]), set([])) # Test graph 17 -G17_TEST1_DN1 = DependencyNode(G17_IRB2.label, A, 1) +G17_TEST1_DN1 = DependencyNode(G17_IRB2.loc_key, A, 1) G17_INPUT = (set([G17_TEST1_DN1]), set([])) @@ -638,7 +747,8 @@ def flatNode(node): element = int(node.element.arg) else: RuntimeError("Unsupported type '%s'" % type(enode.element)) - return (node.label.name, + name = loc_db.pretty_str(node.loc_key) + return (name, element, node.line_nb) else: @@ -736,7 +846,8 @@ def match_results(resultsA, resultsB, nodes): def get_flat_init_depnodes(depnodes): out = [] for node in depnodes: - out.append((node.label.name, + name = loc_db.pretty_str(node.loc_key) + out.append((name, node.element.name, node.line_nb, 0)) @@ -1017,21 +1128,23 @@ for test_nb, test in enumerate([(G1_IRA, G1_INPUT), # Extract test elements print "[+] Test", test_nb + 1 - g_ira, (depnodes, heads) = test + ircfg, (depnodes, heads) = test - open("graph_%02d.dot" % (test_nb + 1), "w").write(g_ira.graph.dot()) - open("graph_%02d.dot" % (test_nb + 1), "w").write(bloc2graph(g_ira)) + open("graph_%02d.dot" % (test_nb + 1), "w").write(ircfg.dot()) + open("graph_%02d.dot" % (test_nb + 1), "w").write(bloc2graph(ircfg)) # Different options suffix_key_list = ["", "_nosimp", "_nomem", "_nocall", "_implicit"] # Test classes - for g_ind, g_dep in enumerate([DependencyGraph(g_ira), - DependencyGraph(g_ira, apply_simp=False), - DependencyGraph(g_ira, follow_mem=False), - DependencyGraph(g_ira, follow_mem=False, - follow_call=False), - # DependencyGraph(g_ira, implicit=True), + for g_ind, g_dep in enumerate([DependencyGraph(ircfg), + DependencyGraph(ircfg, apply_simp=False), + DependencyGraph(ircfg, follow_mem=False), + DependencyGraph( + ircfg, follow_mem=False, + follow_call=False + ), + # DependencyGraph(ircfg, implicit=True), ]): # if g_ind == 4: # TODO: Implicit specifications @@ -1052,14 +1165,13 @@ for test_nb, test in enumerate([(G1_IRA, G1_INPUT), all_results.add(unflatGraph(flatGraph(result.graph))) open("graph_test_%02d_%02d.dot" % (test_nb + 1, i), "w").write(dg2graph(result.graph)) - # print all_flat + if g_ind == 0: all_flat = sorted(all_flat) all_flats.append(all_flat) flat_depnodes = get_flat_init_depnodes(depnodes) if not match_results(all_results, test_results[test_nb], flat_depnodes): FAILED.add(test_nb) - # fds continue if FAILED: diff --git a/test/analysis/dg_test_02_implicit_expected.json b/test/analysis/dg_test_02_implicit_expected.json index 9394f01d..cfcf7258 100644 --- a/test/analysis/dg_test_02_implicit_expected.json +++ b/test/analysis/dg_test_02_implicit_expected.json @@ -1 +1 @@ -[{"has_loop": false, "EAX": "0x4", "satisfiability": true, "constraints": {"zf_init": "0x1"}}, {"has_loop": false, "EAX": "0x3", "satisfiability": true, "constraints": {"zf_init": "0x0"}}] +[{"has_loop": false, "EAX": "0x4", "satisfiability": true, "constraints": {"zf": "0x1"}}, {"has_loop": false, "EAX": "0x3", "satisfiability": true, "constraints": {"zf": "0x0"}}] diff --git a/test/analysis/dg_test_04_expected.json b/test/analysis/dg_test_04_expected.json index fb115835..24687e4a 100644 --- a/test/analysis/dg_test_04_expected.json +++ b/test/analysis/dg_test_04_expected.json @@ -1 +1 @@ -[{"EAX": "EBX_init", "has_loop": false}] +[{"EAX": "EBX", "has_loop": false}] diff --git a/test/analysis/dg_test_04_implicit_expected.json b/test/analysis/dg_test_04_implicit_expected.json index 73e7209e..21dbfc96 100644 --- a/test/analysis/dg_test_04_implicit_expected.json +++ b/test/analysis/dg_test_04_implicit_expected.json @@ -1 +1 @@ -[{"has_loop": false, "EAX": "EBX_init", "satisfiability": true, "constraints": {}}, {"has_loop": true, "EAX": "EBX_init", "satisfiability": false, "constraints": {}}] +[{"has_loop": false, "EAX": "EBX", "satisfiability": true, "constraints": {}}, {"has_loop": true, "EAX": "EBX", "satisfiability": false, "constraints": {}}] diff --git a/test/analysis/dg_test_06_implicit_expected.json b/test/analysis/dg_test_06_implicit_expected.json index bda75296..be4e9afb 100644 --- a/test/analysis/dg_test_06_implicit_expected.json +++ b/test/analysis/dg_test_06_implicit_expected.json @@ -1 +1 @@ -[{"has_loop": false, "EAX": "0x1", "satisfiability": true, "constraints": {"EAX_init": "0xffffffff"}}, {"has_loop": false, "EAX": "0x2", "satisfiability": false, "constraints": {}}] +[{"has_loop": false, "EAX": "0x1", "satisfiability": true, "constraints": {"EAX": "0xffffffff"}}, {"has_loop": false, "EAX": "0x2", "satisfiability": false, "constraints": {}}] diff --git a/test/analysis/dg_test_10_implicit_expected.json b/test/analysis/dg_test_10_implicit_expected.json index 05b34918..36a84788 100644 --- a/test/analysis/dg_test_10_implicit_expected.json +++ b/test/analysis/dg_test_10_implicit_expected.json @@ -1 +1 @@ -[{"has_loop": false, "EAX": "0x1", "EBX": "0x3", "satisfiability": true, "constraints": {"zf_init": "0x0"}}, {"has_loop": false, "EAX": "0x2", "EBX": "0x3", "satisfiability": false, "constraints": {}}, {"has_loop": false, "EAX": "0x1", "EBX": "0x4", "satisfiability": false, "constraints": {}}, {"has_loop": false, "EAX": "0x2", "EBX": "0x4", "satisfiability": true, "constraints": {"zf_init": "0x1"}}] +[{"has_loop": false, "EAX": "0x1", "EBX": "0x3", "satisfiability": true, "constraints": {"zf": "0x0"}}, {"has_loop": false, "EAX": "0x2", "EBX": "0x3", "satisfiability": false, "constraints": {}}, {"has_loop": false, "EAX": "0x1", "EBX": "0x4", "satisfiability": false, "constraints": {}}, {"has_loop": false, "EAX": "0x2", "EBX": "0x4", "satisfiability": true, "constraints": {"zf": "0x1"}}] diff --git a/test/analysis/dse.py b/test/analysis/dse.py index 5a72db34..a05d8595 100644 --- a/test/analysis/dse.py +++ b/test/analysis/dse.py @@ -34,8 +34,7 @@ class DSETest(object): self.myjit = jitter(jitter_engine) self.myjit.init_stack() - self.myjit.jit.log_regs = True - self.myjit.jit.log_mn = True + self.myjit.set_trace_log() self.dse = None self.assembly = None @@ -70,17 +69,17 @@ class DSETest(object): def asm(self): mn_x86 = self.machine.mn - blocks, symbol_pool = parse_asm.parse_txt( + blocks, loc_db = parse_asm.parse_txt( mn_x86, self.arch_attrib, self.TXT, - symbol_pool=self.myjit.ir_arch.symbol_pool + loc_db=self.myjit.ir_arch.loc_db ) # fix shellcode addr - symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) + loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) output = StrPatchwork() - patches = asm_resolve_final(mn_x86, blocks, symbol_pool) + patches = asm_resolve_final(mn_x86, blocks, loc_db) for offset, raw in patches.items(): output[offset] = raw diff --git a/test/arch/aarch64/arch.py b/test/arch/aarch64/arch.py index a6aa7ba5..cba175e6 100644 --- a/test/arch/aarch64/arch.py +++ b/test/arch/aarch64/arch.py @@ -2,9 +2,9 @@ import sys import time from pdb import pm from miasm2.arch.aarch64.arch import * -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB -symbol_pool = AsmSymbolPool() +loc_db = LocationDB() reg_tests_aarch64 = [ ("XXXXXXXX MOV W1, WZR", @@ -1814,7 +1814,7 @@ for s, l in reg_tests_aarch64[:]: print s print mn assert(str(mn) == s) - l = mn_aarch64.fromstring(s, symbol_pool, 'l') + l = mn_aarch64.fromstring(s, loc_db, 'l') assert(str(l) == s) a = mn_aarch64.asm(l) print [x for x in a] diff --git a/test/arch/aarch64/unit/asm_test.py b/test/arch/aarch64/unit/asm_test.py index ca27ef9d..677d474f 100644 --- a/test/arch/aarch64/unit/asm_test.py +++ b/test/arch/aarch64/unit/asm_test.py @@ -16,23 +16,18 @@ class Asm_Test(object): self.myjit = Machine("aarch64l").jitter(jitter) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - - def __call__(self): self.asm() self.run() self.check() - def asm(self): - blocks, symbol_pool = parse_asm.parse_txt(mn_aarch64, 'l', self.TXT, - symbol_pool = self.myjit.ir_arch.symbol_pool) + blocks, loc_db = parse_asm.parse_txt(mn_aarch64, 'l', self.TXT, + loc_db = self.myjit.ir_arch.loc_db) # fix shellcode addr - symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) + loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_aarch64, blocks, symbol_pool) + patches = asmblock.asm_resolve_final(mn_aarch64, blocks, loc_db) for offset, raw in patches.items(): s[offset] = raw diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index a951689b..d92c24b2 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -1,45 +1,10 @@ import time from miasm2.arch.arm.arch import * -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB from pdb import pm -symbol_pool = AsmSymbolPool() -if 0: - a = bs('00') - b = bs('01') - c = bs(l=2) - d = bs(l=4, fname='rd') - e = bs_name(l=1, name={'ADD': 0, 'SUB': 1}) - assert(isinstance(e, bs_divert)) - scc = bs_mod_name(l=1, mn_mod=['', 'S']) - f = bs(l=1, cls=(arm_reg,)) - - class arm_mov(mn_arm): - fields = [bs('0000'), bs('0000'), bs('0000')] - - class arm_DATA(mn_arm): - fields = [bs('1111'), e, scc, f, bs('0')] - mn = mn_arm.dis(0xF000000) - - -if 0: - import cProfile - cProfile.run('mn_arm.dis("\xe1\xa0\xa0\x06", "l")') - # l = mn_arm.dis(bin_stream("\xe1\xa0\xa0\x06"), mode_arm) - # print l - """ - mode = 64 - l = mn_x86.fromstring("ADC DWORD PTR [RAX], 0x11223344", mode) - print 'xx' - #t= time.time() - import cProfile - def f(): - x = l.asm(mode) - print x - cProfile.run('f()') - """ - +loc_db = LocationDB() def h2i(s): return s.replace(' ', '').decode('hex') @@ -268,15 +233,11 @@ for s, l in reg_tests_arm: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] - l = mn_arm.fromstring(s, symbol_pool, 'l') - # print l + l = mn_arm.fromstring(s, loc_db, 'l') assert(str(l) == s) a = mn_arm.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) reg_tests_armt = [ @@ -723,36 +684,14 @@ for s, l in reg_tests_armt: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] - l = mn_armt.fromstring(s, symbol_pool, 'l') - # print l + l = mn_armt.fromstring(s, loc_db, 'l') assert(str(l) == s) print 'Asm..', l a = mn_armt.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) -""" -print "*"*30, "START SPECIAL PARSING", "*"*30 -parse_tests = [ - "MOV LR, toto", - "MOV LR, 1+toto", - "MOV LR, (lend-lstart)^toto<<<R1", - "MOV LR, R1 LSL (l_end-l_start)^toto<<<R1", - "MOV LR, R1 LSL (l_end-l_start)^toto<<<R1", - "EOR R0, R1, toto^titi+1", - ] - -for l in parse_tests: - print "-"*80 - l = mn_arm.fromstring(l, 'l') - print l.name, ", ".join([str(a) for a in l.args]) -""" - - print 'TEST time', time.time() - ts # speed test arm @@ -790,7 +729,6 @@ instr_num = 0 ts = time.time() while off < bs.getlen(): mn = mn_armt.dis(bs, 'l', off) - # print instr_num, off, str(mn) instr_num += 1 off += mn.l print 'instr per sec:', instr_num / (time.time() - ts) diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py index d9e6aa76..64cda610 100755 --- a/test/arch/arm/sem.py +++ b/test/arch/arm/sem.py @@ -9,29 +9,30 @@ from miasm2.arch.arm.arch import mn_arm as mn from miasm2.arch.arm.sem import ir_arml as ir_arch from miasm2.arch.arm.regs import * from miasm2.expression.expression import * -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB from pdb import pm logging.getLogger('cpuhelper').setLevel(logging.ERROR) EXCLUDE_REGS = set([ir_arch().IRDst]) -symbol_pool = AsmSymbolPool() def M(addr): return ExprMem(ExprInt(addr, 16), 16) def compute(asm, inputstate={}, debug=False): + loc_db = LocationDB() sympool = dict(regs_init) sympool.update({k: ExprInt(v, k.size) for k, v in inputstate.iteritems()}) - interm = ir_arch() - symexec = SymbolicExecutionEngine(interm, sympool) - instr = mn.fromstring(asm, symbol_pool, "l") + ir_tmp = ir_arch(loc_db) + ircfg = ir_tmp.new_ircfg() + symexec = SymbolicExecutionEngine(ir_tmp, sympool) + instr = mn.fromstring(asm, loc_db, "l") code = mn.asm(instr)[0] instr = mn.dis(code, "l") instr.offset = inputstate.get(PC, 0) - interm.add_instr(instr) - symexec.run_at(instr.offset) + lbl = ir_tmp.add_instr_to_ircfg(instr, ircfg) + symexec.run_at(ircfg, lbl) if debug: for k, v in symexec.symbols.items(): if regs_init.get(k, None) != v: diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py index c6b68c0c..1cbb554d 100644 --- a/test/arch/mips32/arch.py +++ b/test/arch/mips32/arch.py @@ -1,10 +1,10 @@ import time from pdb import pm -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB from miasm2.arch.mips32.arch import * -symbol_pool = AsmSymbolPool() +loc_db = LocationDB() reg_tests_mips32 = [ ("004496D8 ADDU GP, GP, T9", @@ -228,13 +228,9 @@ for s, l in reg_tests_mips32: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] - l = mn_mips32.fromstring(s, symbol_pool, 'b') - # print l + l = mn_mips32.fromstring(s, loc_db, 'b') assert(str(l) == s) a = mn_mips32.asm(l, 'b') print [x for x in a] print repr(b) - # print mn.args assert(b in a) diff --git a/test/arch/mips32/unit/asm_test.py b/test/arch/mips32/unit/asm_test.py index f03a32d7..da792874 100644 --- a/test/arch/mips32/unit/asm_test.py +++ b/test/arch/mips32/unit/asm_test.py @@ -18,21 +18,18 @@ class Asm_Test(object): self.myjit = Machine("mips32l").jitter(jitter) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - def __call__(self): self.asm() self.run() self.check() def asm(self): - blocks, symbol_pool = parse_asm.parse_txt(mn_mips32, 'l', self.TXT, - symbol_pool=self.myjit.ir_arch.symbol_pool) + blocks, loc_db = parse_asm.parse_txt(mn_mips32, 'l', self.TXT, + loc_db=self.myjit.ir_arch.loc_db) # fix shellcode addr - symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) + loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_mips32, blocks, symbol_pool) + patches = asmblock.asm_resolve_final(mn_mips32, blocks, loc_db) for offset, raw in patches.items(): s[offset] = raw diff --git a/test/arch/msp430/arch.py b/test/arch/msp430/arch.py index 3df2becb..91de95b3 100644 --- a/test/arch/msp430/arch.py +++ b/test/arch/msp430/arch.py @@ -1,9 +1,9 @@ import time from pdb import pm from miasm2.arch.msp430.arch import * -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB -symbol_pool = AsmSymbolPool() +loc_db = LocationDB() def h2i(s): return s.replace(' ', '').decode('hex') @@ -95,13 +95,9 @@ for s, l in reg_tests_msp: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] - l = mn_msp430.fromstring(s, symbol_pool, None) - # print l + l = mn_msp430.fromstring(s, loc_db, None) assert(str(l) == s) a = mn_msp430.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py index 3b2c2f2e..10e57e36 100755 --- a/test/arch/msp430/sem.py +++ b/test/arch/msp430/sem.py @@ -9,25 +9,29 @@ from miasm2.arch.msp430.arch import mn_msp430 as mn, mode_msp430 as mode from miasm2.arch.msp430.sem import ir_msp430 as ir_arch from miasm2.arch.msp430.regs import * from miasm2.expression.expression import * +from miasm2.core.locationdb import LocationDB logging.getLogger('cpuhelper').setLevel(logging.ERROR) EXCLUDE_REGS = set([res, ir_arch().IRDst]) + def M(addr): return ExprMem(ExprInt(addr, 16), 16) def compute(asm, inputstate={}, debug=False): + loc_db = LocationDB() sympool = dict(regs_init) sympool.update({k: ExprInt(v, k.size) for k, v in inputstate.iteritems()}) - interm = ir_arch() - symexec = SymbolicExecutionEngine(interm, sympool) + ir_tmp = ir_arch(loc_db) + ircfg = ir_tmp.new_ircfg() + symexec = SymbolicExecutionEngine(ir_tmp, sympool) instr = mn.fromstring(asm, mode) code = mn.asm(instr)[0] instr = mn.dis(code, mode) instr.offset = inputstate.get(PC, 0) - interm.add_instr(instr) - symexec.run_at(instr.offset) + loc_key = ir_tmp.add_instr_to_ircfg(instr, ircfg) + symexec.run_at(ircfg, loc_key) if debug: for k, v in symexec.symbols.items(): if regs_init.get(k, None) != v: diff --git a/test/arch/sh4/arch.py b/test/arch/sh4/arch.py index 574dcf49..f744b215 100644 --- a/test/arch/sh4/arch.py +++ b/test/arch/sh4/arch.py @@ -2,9 +2,9 @@ import time from pdb import pm from sys import stderr from miasm2.arch.sh4.arch import * -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB -symbol_pool = AsmSymbolPool() +loc_db = LocationDB() def h2i(s): return s.replace(' ', '').decode('hex') @@ -398,15 +398,11 @@ for s, l in reg_tests_sh4: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] - l = mn_sh4.fromstring(s, symbol_pool, None) - # print l + l = mn_sh4.fromstring(s, loc_db, None) assert(str(l) == s) a = mn_sh4.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 05b31815..43e973e1 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -5,9 +5,9 @@ from miasm2.arch.x86.arch import mn_x86, deref_mem_ad, \ base_expr, rmarg, print_size from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 from miasm2.core.bin_stream import bin_stream_str -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB -symbol_pool = AsmSymbolPool() +loc_db = LocationDB() mylabel16 = m2_expr.ExprId('mylabel16', 16) mylabel32 = m2_expr.ExprId('mylabel32', 32) @@ -3062,17 +3062,13 @@ for mode, s, l, in reg_tests: print s print mn assert(str(mn).strip() == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] print 'fromstring', repr(s) - l = mn_x86.fromstring(s, symbol_pool, mode) - # print l + l = mn_x86.fromstring(s, loc_db, mode) print 'str args', [(str(x), x.size) for x in l.args] assert(str(l).strip(' ') == s) a = mn_x86.asm(l) print 'asm result', [x for x in a] print repr(b) - # test_file[mode[0]].write(b) for x in a: print "BYTES", repr(x) @@ -3086,7 +3082,6 @@ for mode, s, l, in reg_tests: assert(str(rl).strip(' ') == s) print repr(b), a assert(b in a) - # print mn.args print 'TEST time', time.time() - ts @@ -3118,9 +3113,7 @@ def profile_dis(o): print 'instr per sec:', instr_num / (time.time() - ts) import cProfile -# cProfile.run(r'mn_x86.dis("\x81\x54\x18\xfe\x44\x33\x22\x11", m32)') cProfile.run('profile_dis(o)') -# profile_dis(o) # Test instruction representation with prefix instr_bytes = '\x65\xc7\x00\x09\x00\x00\x00' diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index b3b7e940..0783089d 100755 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -12,24 +12,23 @@ from miasm2.arch.x86.arch import mn_x86 as mn from miasm2.arch.x86.sem import ir_x86_32 as ir_32, ir_x86_64 as ir_64 from miasm2.arch.x86.regs import * from miasm2.expression.expression import * -from miasm2.expression.simplifications import expr_simp +from miasm2.expression.simplifications import expr_simp from miasm2.core import parse_asm, asmblock -from miasm2.core.asmblock import AsmSymbolPool +from miasm2.core.locationdb import LocationDB logging.getLogger('cpuhelper').setLevel(logging.ERROR) EXCLUDE_REGS = set([ir_32().IRDst, ir_64().IRDst]) -symbol_pool = AsmSymbolPool() m32 = 32 m64 = 64 -def symb_exec(interm, inputstate, debug): +def symb_exec(lbl, ir_arch, ircfg, inputstate, debug): sympool = dict(regs_init) sympool.update(inputstate) - symexec = SymbolicExecutionEngine(interm, sympool) - symexec.run_at(0) + symexec = SymbolicExecutionEngine(ir_arch, sympool) + symexec.run_at(ircfg, lbl) if debug: for k, v in symexec.symbols.items(): if regs_init.get(k, None) != v: @@ -38,23 +37,25 @@ def symb_exec(interm, inputstate, debug): if k not in EXCLUDE_REGS and regs_init.get(k, None) != v} def compute(ir, mode, asm, inputstate={}, debug=False): - instr = mn.fromstring(asm, symbol_pool, mode) + loc_db = LocationDB() + instr = mn.fromstring(asm, loc_db, mode) code = mn.asm(instr)[0] instr = mn.dis(code, mode) instr.offset = inputstate.get(EIP, 0) - interm = ir() - interm.add_instr(instr) - return symb_exec(interm, inputstate, debug) + ir_arch = ir(loc_db) + ircfg = ir_arch.new_ircfg() + lbl = ir_arch.add_instr_to_ircfg(instr, ircfg) + return symb_exec(lbl, ir_arch, ircfg, inputstate, debug) def compute_txt(ir, mode, txt, inputstate={}, debug=False): - blocks, symbol_pool = parse_asm.parse_txt(mn, mode, txt) - symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) - patches = asmblock.asm_resolve_final(mn, blocks, symbol_pool) - interm = ir(symbol_pool) - for bbl in blocks: - interm.add_block(bbl) - return symb_exec(interm, inputstate, debug) + asmcfg, loc_db = parse_asm.parse_txt(mn, mode, txt) + loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) + patches = asmblock.asm_resolve_final(mn, asmcfg, loc_db) + ir_arch = ir(loc_db) + lbl = loc_db.get_name_location("main") + ircfg = ir_arch.new_ircfg_from_asmcfg(asmcfg) + return symb_exec(lbl, ir_arch, ircfg, inputstate, debug) op_add = lambda a, b: a+b op_sub = lambda a, b: a-b diff --git a/test/arch/x86/unit/access_xmm.py b/test/arch/x86/unit/access_xmm.py new file mode 100644 index 00000000..950c8b56 --- /dev/null +++ b/test/arch/x86/unit/access_xmm.py @@ -0,0 +1,16 @@ +#! /usr/bin/env python2 +"""Test getter and setter for XMM registers (128 bits)""" + +from miasm2.analysis.machine import Machine + +# Jitter engine doesn't matter, use the always available 'python' one +myjit = Machine("x86_32").jitter("python") + +# Test basic access (get) +assert myjit.cpu.XMM0 == 0 + +# Test set +myjit.cpu.XMM1 = 0x00112233445566778899aabbccddeeffL + +# Ensure set has been correctly handled +assert myjit.cpu.XMM1 == 0x00112233445566778899aabbccddeeffL diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index 961967f9..91da1942 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -18,9 +18,6 @@ class Asm_Test(object): self.myjit = Machine(self.arch_name).jitter(jitter_engine) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - def test_init(self): pass @@ -43,12 +40,12 @@ class Asm_Test(object): assert(self.myjit.pc == self.ret_addr) def asm(self): - blocks, symbol_pool = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, - symbol_pool = self.myjit.ir_arch.symbol_pool) + blocks, loc_db = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, + loc_db = self.myjit.ir_arch.loc_db) # fix shellcode addr - symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0) + loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_x86, blocks, symbol_pool) + patches = asmblock.asm_resolve_final(mn_x86, blocks, loc_db) for offset, raw in patches.items(): s[offset] = raw @@ -81,10 +78,6 @@ class Asm_Test_16(Asm_Test): self.myjit.stack_size = 0x1000 self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - - def init_machine(self): self.myjit.vm.add_memory_page(self.run_addr, PAGE_READ | PAGE_WRITE, self.assembly) self.myjit.push_uint16_t(self.ret_addr) diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py index b6abc781..947b40bb 100644 --- a/test/arch/x86/unit/mn_cdq.py +++ b/test/arch/x86/unit/mn_cdq.py @@ -10,7 +10,7 @@ class Test_CBW_16(Asm_Test_16): MYSTRING = "test CBW 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -31,7 +31,7 @@ class Test_CBW_16_signed(Asm_Test_16): MYSTRING = "test CBW 16 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654381 @@ -52,7 +52,7 @@ class Test_CBW_32(Asm_Test_32): MYSTRING = "test CBW 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -73,7 +73,7 @@ class Test_CBW_32_signed(Asm_Test_32): MYSTRING = "test CBW 32 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654381 @@ -94,7 +94,7 @@ class Test_CDQ_32(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x77654321 @@ -115,7 +115,7 @@ class Test_CDQ_32_signed(Asm_Test_32): MYSTRING = "test cdq 32 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -136,7 +136,7 @@ class Test_CDQ_64(Asm_Test_64): MYSTRING = "test cdq 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567877654321 @@ -157,7 +157,7 @@ class Test_CDQ_64_signed(Asm_Test_64): MYSTRING = "test cdq 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -178,7 +178,7 @@ class Test_CDQE_64(Asm_Test_64): MYSTRING = "test cdq 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567877654321 @@ -199,7 +199,7 @@ class Test_CDQE_64_signed(Asm_Test_64): MYSTRING = "test cdq 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -220,7 +220,7 @@ class Test_CWD_32(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -241,7 +241,7 @@ class Test_CWD_32_signed(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87658321 @@ -262,7 +262,7 @@ class Test_CWD_32(Asm_Test_32): MYSTRING = "test cdq 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -283,7 +283,7 @@ class Test_CWDE_32(Asm_Test_32): MYSTRING = "test cwde 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.EAX = 0x87654321 @@ -304,7 +304,7 @@ class Test_CWDE_32_signed(Asm_Test_32): MYSTRING = "test cwde 32 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x87658321 @@ -325,7 +325,7 @@ class Test_CWDE_64(Asm_Test_64): MYSTRING = "test cwde 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -346,7 +346,7 @@ class Test_CWDE_64_signed(Asm_Test_64): MYSTRING = "test cwde 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887658321 @@ -367,7 +367,7 @@ class Test_CQO_64(Asm_Test_64): MYSTRING = "test cwde 64" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x1234567887654321 @@ -388,7 +388,7 @@ class Test_CQO_64_signed(Asm_Test_64): MYSTRING = "test cwde 64 signed" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.myjit.cpu.RAX = 0x8234567887658321 diff --git a/test/arch/x86/unit/mn_int.py b/test/arch/x86/unit/mn_int.py index 09792371..efacb105 100755 --- a/test/arch/x86/unit/mn_int.py +++ b/test/arch/x86/unit/mn_int.py @@ -8,12 +8,18 @@ from asm_test import Asm_Test_32 class Test_INT(Asm_Test_32): TXT = ''' main: + MOV ECX, 0x10 + loop: INT 0x42 + DEC ECX + JNZ loop + ret: RET ''' def set_int_num(self, jitter): - self.int_num = jitter.cpu.get_interrupt_num() + assert jitter.cpu.get_interrupt_num() == 0x42 + self.int_num += 1 jitter.cpu.set_exception(0) return True @@ -24,7 +30,7 @@ class Test_INT(Asm_Test_32): self.set_int_num) def check(self): - assert self.int_num == 0x42 + assert self.int_num == 0x10 self.myjit.cpu.set_interrupt_num(14) assert self.myjit.cpu.get_interrupt_num() == 14 diff --git a/test/arch/x86/unit/mn_pushpop.py b/test/arch/x86/unit/mn_pushpop.py index 7ac400c0..6e9005ca 100755 --- a/test/arch/x86/unit/mn_pushpop.py +++ b/test/arch/x86/unit/mn_pushpop.py @@ -21,7 +21,7 @@ class Test_PUSHAD_32(Asm_Test_32): MYSTRING = "test pushad 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -48,7 +48,7 @@ class Test_PUSHA_32(Asm_Test_32): MYSTRING = "test pusha 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -75,7 +75,7 @@ class Test_PUSHA_16(Asm_Test_16): MYSTRING = "test pusha 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -102,7 +102,7 @@ class Test_PUSHAD_16(Asm_Test_16): MYSTRING = "test pushad 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -129,7 +129,7 @@ class Test_PUSH_mode32_32(Asm_Test_32): MYSTRING = "test push mode32 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -152,7 +152,7 @@ class Test_PUSH_mode32_16(Asm_Test_32): MYSTRING = "test push mode32 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -175,7 +175,7 @@ class Test_PUSH_mode16_16(Asm_Test_16): MYSTRING = "test push mode16 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -198,7 +198,7 @@ class Test_PUSH_mode16_32(Asm_Test_16): MYSTRING = "test push mode16 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -221,7 +221,7 @@ class Test_POP_mode32_32(Asm_Test_32): MYSTRING = "test pop mode32 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 @@ -243,7 +243,7 @@ class Test_POP_mode32_16(Asm_Test_32): MYSTRING = "test pop mode32 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -265,7 +265,7 @@ class Test_POP_mode16_16(Asm_Test_16): MYSTRING = "test pop mode16 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -287,7 +287,7 @@ class Test_POP_mode16_32(Asm_Test_16): MYSTRING = "test pop mode16 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 diff --git a/test/arch/x86/unit/mn_strings.py b/test/arch/x86/unit/mn_strings.py index 3cb70e2a..8ca148e5 100755 --- a/test/arch/x86/unit/mn_strings.py +++ b/test/arch/x86/unit/mn_strings.py @@ -21,7 +21,8 @@ class Test_SCAS(Asm_Test_32): def check(self): assert(self.myjit.cpu.ECX == len(self.MYSTRING)) - assert(self.myjit.cpu.EDI == self.myjit.ir_arch.symbol_pool.getby_name('mystr').offset + len(self.MYSTRING)+1) + mystr = self.myjit.ir_arch.loc_db.get_name_location('mystr') + assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.get_location_offset(mystr) + len(self.MYSTRING)+1) class Test_MOVS(Asm_Test_32): @@ -42,8 +43,10 @@ class Test_MOVS(Asm_Test_32): def check(self): assert(self.myjit.cpu.ECX == 0) - assert(self.myjit.cpu.EDI == self.myjit.ir_arch.symbol_pool.getby_name('buffer').offset + len(self.MYSTRING)) - assert(self.myjit.cpu.ESI == self.myjit.ir_arch.symbol_pool.getby_name('mystr').offset + len(self.MYSTRING)) + buffer = self.myjit.ir_arch.loc_db.get_name_location('buffer') + assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.get_location_offset(buffer) + len(self.MYSTRING)) + mystr = self.myjit.ir_arch.loc_db.get_name_location('mystr') + assert(self.myjit.cpu.ESI == self.myjit.ir_arch.loc_db.get_location_offset(mystr) + len(self.MYSTRING)) if __name__ == "__main__": diff --git a/test/core/asmblock.py b/test/core/asmblock.py index 7f0dbc5f..cd1d262a 100644 --- a/test/core/asmblock.py +++ b/test/core/asmblock.py @@ -3,7 +3,7 @@ from pdb import pm from miasm2.arch.x86.disasm import dis_x86_32 from miasm2.analysis.binary import Container from miasm2.core.asmblock import AsmCFG, AsmConstraint, AsmBlock, \ - AsmLabel, AsmBlockBad, AsmConstraintTo, AsmConstraintNext, \ + AsmBlockBad, AsmConstraintTo, AsmConstraintNext, \ bbl_simplifier from miasm2.core.graph import DiGraphSimplifier, MatchGraphJoker from miasm2.expression.expression import ExprId @@ -19,57 +19,57 @@ first_block = mdis.dis_block(0) assert len(first_block.lines) == 5 print first_block -## Test redisassemble blocks +## Test redisassemble asmcfg first_block_bis = mdis.dis_block(0) assert len(first_block.lines) == len(first_block_bis.lines) print first_block_bis ## Disassembly of several block, with cache -blocks = mdis.dis_multiblock(0) -assert len(blocks) == 17 +asmcfg = mdis.dis_multiblock(0) +assert len(asmcfg) == 17 -## Test redisassemble blocks -blocks = mdis.dis_multiblock(0) -assert len(blocks) == 17 +## Test redisassemble asmcfg +asmcfg = mdis.dis_multiblock(0) +assert len(asmcfg) == 17 ## Equality between assembly lines is not yet implemented -assert len(blocks.heads()) == 1 -assert len(blocks.heads()[0].lines) == len(first_block.lines) +assert len(asmcfg.heads()) == 1 +assert len(asmcfg.loc_key_to_block(asmcfg.heads()[0]).lines) == len(first_block.lines) # Test AsmCFG -assert isinstance(blocks, AsmCFG) -assert len(blocks.pendings) == 0 -assert len(blocks.nodes()) == 17 -assert len(blocks.edges2constraint) == len(blocks.edges()) -assert len(blocks.edges()) == 24 -assert blocks.getby_offset(0x63).lines[0].offset == 0x5f -assert blocks.getby_offset(0x69).lines[0].offset == 0x69 +assert isinstance(asmcfg, AsmCFG) +assert len(asmcfg.pendings) == 0 +assert len(asmcfg.nodes()) == 17 +assert len(asmcfg.edges2constraint) == len(asmcfg.edges()) +assert len(asmcfg.edges()) == 24 +assert asmcfg.getby_offset(0x63).lines[0].offset == 0x5f +assert asmcfg.getby_offset(0x69).lines[0].offset == 0x69 ## Convert to dot -open("graph.dot", "w").write(blocks.dot()) +open("graph.dot", "w").write(asmcfg.dot()) ## Modify the structure: link the first and the last block -leaves = blocks.leaves() +leaves = asmcfg.leaves() assert len(leaves) == 1 -last_block = leaves.pop() +last_block_loc_key = leaves.pop() ### Remove first_block for the rest of the graph -first_block = blocks.heads()[0] +first_block = asmcfg.loc_key_to_block(asmcfg.heads()[0]) assert len(first_block.bto) == 2 -for succ in blocks.successors(first_block): - blocks.del_edge(first_block, succ) +for succ in asmcfg.successors(first_block.loc_key): + asmcfg.del_edge(first_block.loc_key, succ) ### Modification must be reported from the graph assert len(first_block.bto) == 0 -assert last_block in blocks +assert last_block_loc_key in asmcfg.nodes() ### Remove predecessors of last block -for pred in blocks.predecessors(last_block): - blocks.del_edge(pred, last_block) +for pred in asmcfg.predecessors(last_block_loc_key): + asmcfg.del_edge(pred, last_block_loc_key) ### Link first and last block -blocks.add_edge(first_block, last_block, AsmConstraint.c_next) -### Only one link between two blocks +asmcfg.add_edge(first_block.loc_key, last_block_loc_key, AsmConstraint.c_next) +### Only one link between two asmcfg try: - blocks.add_edge(first_block, last_block, AsmConstraint.c_to) + asmcfg.add_edge(first_block, last_block_loc_key, AsmConstraint.c_to) good = False except AssertionError: good = True @@ -79,222 +79,233 @@ assert good assert len(first_block.bto) == 1 assert list(first_block.bto)[0].c_t == AsmConstraint.c_next -## Simplify the obtained graph to keep only blocks which reach a block +## Simplify the obtained graph to keep only asmcfg which reach a block ## finishing with RET def remove_useless_blocks(d_g, graph): """Remove leaves without a RET""" - for block in graph.leaves(): + for leaf_label in graph.leaves(): + block = graph.loc_key_to_block(leaf_label) if block.lines[-1].name != "RET": - graph.del_node(block) + graph.del_block(graph.loc_key_to_block(leaf_label)) ### Use a graph simplifier to recursively apply the simplification pass dg = DiGraphSimplifier() dg.enable_passes([remove_useless_blocks]) -blocks = dg(blocks) +asmcfg = dg(asmcfg) -### Only two blocks should remain -assert len(blocks) == 2 -assert first_block in blocks -assert last_block in blocks +### Only two asmcfg should remain +assert len(asmcfg) == 2 +assert first_block.loc_key in asmcfg.nodes() +assert last_block_loc_key in asmcfg.nodes() ## Graph the final output -open("graph2.dot", "w").write(blocks.dot()) +open("graph2.dot", "w").write(asmcfg.dot()) # Test helper methods -## Label2block should always be updated -assert blocks.label2block(first_block.label) == first_block -my_block = AsmBlock(AsmLabel("testlabel")) -blocks.add_node(my_block) -assert len(blocks) == 3 -assert blocks.label2block(first_block.label) == first_block -assert blocks.label2block(my_block.label) == my_block +## loc_key_to_block should always be updated +assert asmcfg.loc_key_to_block(first_block.loc_key) == first_block +testlabel = mdis.loc_db.get_or_create_name_location("testlabel") +my_block = AsmBlock(testlabel) +asmcfg.add_block(my_block) +assert len(asmcfg) == 3 +assert asmcfg.loc_key_to_block(first_block.loc_key) == first_block +assert asmcfg.loc_key_to_block(my_block.loc_key) == my_block -## Bad blocks -assert len(list(blocks.get_bad_blocks())) == 0 -assert len(list(blocks.get_bad_blocks_predecessors())) == 0 +## Bad asmcfg +assert len(list(asmcfg.get_bad_blocks())) == 0 +assert len(list(asmcfg.get_bad_blocks_predecessors())) == 0 ### Add a bad block, not linked -my_bad_block = AsmBlockBad(AsmLabel("testlabel_bad")) -blocks.add_node(my_bad_block) -assert list(blocks.get_bad_blocks()) == [my_bad_block] -assert len(list(blocks.get_bad_blocks_predecessors())) == 0 +testlabel_bad = mdis.loc_db.get_or_create_name_location("testlabel_bad") +my_bad_block = AsmBlockBad(testlabel_bad) +asmcfg.add_block(my_bad_block) +assert list(asmcfg.get_bad_blocks()) == [my_bad_block] +assert len(list(asmcfg.get_bad_blocks_predecessors())) == 0 ### Link the bad block and update edges -### Indeed, a sub-element has been modified (bto from a block from blocks) -my_block.bto.add(AsmConstraintTo(my_bad_block.label)) -blocks.rebuild_edges() -assert list(blocks.get_bad_blocks_predecessors()) == [my_block] +### Indeed, a sub-element has been modified (bto from a block from asmcfg) +my_block.bto.add(AsmConstraintTo(my_bad_block.loc_key)) +asmcfg.rebuild_edges() +assert list(asmcfg.get_bad_blocks_predecessors()) == [my_block.loc_key] ### Test strict option -my_block.bto.add(AsmConstraintTo(my_block.label)) -blocks.rebuild_edges() -assert list(blocks.get_bad_blocks_predecessors(strict=False)) == [my_block] -assert len(list(blocks.get_bad_blocks_predecessors(strict=True))) == 0 +my_block.bto.add(AsmConstraintTo(my_block.loc_key)) +asmcfg.rebuild_edges() +assert list(asmcfg.get_bad_blocks_predecessors(strict=False)) == [my_block.loc_key] +assert len(list(asmcfg.get_bad_blocks_predecessors(strict=True))) == 0 ## Sanity check -blocks.sanity_check() +asmcfg.sanity_check() ### Next on itself -my_block_ni = AsmBlock(AsmLabel("testlabel_nextitself")) -my_block_ni.bto.add(AsmConstraintNext(my_block_ni.label)) -blocks.add_node(my_block_ni) +testlabel_nextitself = mdis.loc_db.get_or_create_name_location("testlabel_nextitself") +my_block_ni = AsmBlock(testlabel_nextitself) +my_block_ni.bto.add(AsmConstraintNext(my_block_ni.loc_key)) +asmcfg.add_block(my_block_ni) error_raised = False try: - blocks.sanity_check() + asmcfg.sanity_check() except RuntimeError: error_raised = True assert error_raised ### Back to a normal state -blocks.del_node(my_block_ni) -blocks.sanity_check() +asmcfg.del_block(my_block_ni) +asmcfg.sanity_check() ### Multiple next on the same node -my_block_target = AsmBlock(AsmLabel("testlabel_target")) -blocks.add_node(my_block_target) -my_block_src1 = AsmBlock(AsmLabel("testlabel_src1")) -my_block_src2 = AsmBlock(AsmLabel("testlabel_src2")) -my_block_src1.bto.add(AsmConstraintNext(my_block_target.label)) -blocks.add_node(my_block_src1) +testlabel_target = mdis.loc_db.get_or_create_name_location("testlabel_target") +my_block_target = AsmBlock(testlabel_target) +asmcfg.add_block(my_block_target) +testlabel_src1 = mdis.loc_db.get_or_create_name_location("testlabel_src1") +testlabel_src2 = mdis.loc_db.get_or_create_name_location("testlabel_src2") +my_block_src1 = AsmBlock(testlabel_src1) +my_block_src2 = AsmBlock(testlabel_src2) +my_block_src1.bto.add(AsmConstraintNext(my_block_target.loc_key)) +asmcfg.add_block(my_block_src1) ### OK for now -blocks.sanity_check() +asmcfg.sanity_check() ### Add a second next from src2 to target (already src1 -> target) -my_block_src2.bto.add(AsmConstraintNext(my_block_target.label)) -blocks.add_node(my_block_src2) +my_block_src2.bto.add(AsmConstraintNext(my_block_target.loc_key)) +asmcfg.add_block(my_block_src2) error_raised = False try: - blocks.sanity_check() + asmcfg.sanity_check() except RuntimeError: error_raised = True assert error_raised -blocks.del_node(my_block_src2) -blocks.sanity_check() +asmcfg.del_block(my_block_src2) +asmcfg.sanity_check() ## Guess block size ### Initial state assert not hasattr(first_block, 'size') assert not hasattr(first_block, 'max_size') -blocks.guess_blocks_size(mdis.arch) +asmcfg.guess_blocks_size(mdis.arch) assert first_block.size == 39 -assert blocks.label2block(my_block_src1.label).size == 0 +assert asmcfg.loc_key_to_block(my_block_src1.loc_key).size == 0 assert first_block.max_size == 39 -assert blocks.label2block(my_block_src1.label).max_size == 0 +assert asmcfg.loc_key_to_block(my_block_src1.loc_key).max_size == 0 ## Check pendings ### Create a pending element -my_block_src = AsmBlock(AsmLabel("testlabel_pend_src")) -my_block_dst = AsmBlock(AsmLabel("testlabel_pend_dst")) -my_block_src.bto.add(AsmConstraintTo(my_block_dst.label)) -blocks.add_node(my_block_src) +testlabel_pend_src = mdis.loc_db.get_or_create_name_location("testlabel_pend_src") +testlabel_pend_dst = mdis.loc_db.get_or_create_name_location("testlabel_pend_dst") +my_block_src = AsmBlock(testlabel_pend_src) +my_block_dst = AsmBlock(testlabel_pend_dst) +my_block_src.bto.add(AsmConstraintTo(my_block_dst.loc_key)) +asmcfg.add_block(my_block_src) ### Check resulting state -assert len(blocks) == 7 -assert len(blocks.pendings) == 1 -assert my_block_dst.label in blocks.pendings -assert len(blocks.pendings[my_block_dst.label]) == 1 -pending = list(blocks.pendings[my_block_dst.label])[0] -assert isinstance(pending, blocks.AsmCFGPending) +assert len(asmcfg) == 7 +assert len(asmcfg.pendings) == 1 +assert my_block_dst.loc_key in asmcfg.pendings +assert len(asmcfg.pendings[my_block_dst.loc_key]) == 1 +pending = list(asmcfg.pendings[my_block_dst.loc_key])[0] +assert isinstance(pending, asmcfg.AsmCFGPending) assert pending.waiter == my_block_src assert pending.constraint == AsmConstraint.c_to ### Sanity check must fail error_raised = False try: - blocks.sanity_check() + asmcfg.sanity_check() except RuntimeError: error_raised = True assert error_raised ### Pending must disappeared when adding expected block -blocks.add_node(my_block_dst) -assert len(blocks) == 8 -assert len(blocks.pendings) == 0 -blocks.sanity_check() +asmcfg.add_block(my_block_dst) +assert len(asmcfg) == 8 +assert len(asmcfg.pendings) == 0 +asmcfg.sanity_check() # Test block_merge data2 = "31c0eb0c31c9750c31d2eb0c31ffebf831dbebf031edebfc31f6ebf031e4c3".decode("hex") cont2 = Container.from_string(data2) mdis = dis_x86_32(cont2.bin_stream) ## Elements to merge -blocks = mdis.dis_multiblock(0) +asmcfg = mdis.dis_multiblock(0) ## Block alone -blocks.add_node(mdis.dis_block(0x1c)) +asmcfg.add_block(mdis.dis_block(0x1c)) ## Bad block -blocks.add_node(mdis.dis_block(len(data2))) +asmcfg.add_block(mdis.dis_block(len(data2))) ## Dump the graph before merging -open("graph3.dot", "w").write(blocks.dot()) +open("graph3.dot", "w").write(asmcfg.dot()) ## Apply merging -blocks = bbl_simplifier(blocks) +asmcfg = bbl_simplifier(asmcfg) ## Dump the graph after merging -open("graph4.dot", "w").write(blocks.dot()) +open("graph4.dot", "w").write(asmcfg.dot()) ## Check the final state -assert len(blocks) == 5 -assert len(list(blocks.get_bad_blocks())) == 1 -### Check "special" blocks -entry_blocks = blocks.heads() -bad_block = (block for block in entry_blocks - if isinstance(block, AsmBlockBad)).next() -entry_blocks.remove(bad_block) -alone_block = (block for block in entry_blocks - if len(blocks.successors(block)) == 0).next() -entry_blocks.remove(alone_block) +assert len(asmcfg) == 5 +assert len(list(asmcfg.get_bad_blocks())) == 1 +### Check "special" asmcfg +entry_asmcfg = asmcfg.heads() +bad_block_lbl = (lbl for lbl in entry_asmcfg + if isinstance(asmcfg.loc_key_to_block(lbl), AsmBlockBad)).next() +entry_asmcfg.remove(bad_block_lbl) +alone_block = (asmcfg.loc_key_to_block(lbl) for lbl in entry_asmcfg + if len(asmcfg.successors(lbl)) == 0).next() +entry_asmcfg.remove(alone_block.loc_key) assert alone_block.lines[-1].name == "RET" assert len(alone_block.lines) == 2 ### Check resulting function -entry_block = entry_blocks.pop() +entry_block = asmcfg.loc_key_to_block(entry_asmcfg.pop()) assert len(entry_block.lines) == 4 assert map(str, entry_block.lines) == ['XOR EAX, EAX', 'XOR EBX, EBX', 'XOR ECX, ECX', - 'JNZ loc_0000000000000014:0x00000014'] -assert len(blocks.successors(entry_block)) == 2 + 'JNZ loc_key_3'] +assert len(asmcfg.successors(entry_block.loc_key)) == 2 assert len(entry_block.bto) == 2 -nextb = blocks.label2block((cons.label for cons in entry_block.bto - if cons.c_t == AsmConstraint.c_next).next()) -tob = blocks.label2block((cons.label for cons in entry_block.bto - if cons.c_t == AsmConstraint.c_to).next()) +nextb = asmcfg.loc_key_to_block((cons.loc_key for cons in entry_block.bto + if cons.c_t == AsmConstraint.c_next).next()) +tob = asmcfg.loc_key_to_block((cons.loc_key for cons in entry_block.bto + if cons.c_t == AsmConstraint.c_to).next()) assert len(nextb.lines) == 4 assert map(str, nextb.lines) == ['XOR EDX, EDX', 'XOR ESI, ESI', 'XOR EDI, EDI', - 'JMP loc_0000000000000008:0x00000008'] -assert blocks.successors(nextb) == [nextb] + 'JMP loc_key_4'] +assert asmcfg.successors(nextb.loc_key) == [nextb.loc_key] assert len(tob.lines) == 2 assert map(str, tob.lines) == ['XOR EBP, EBP', - 'JMP loc_0000000000000014:0x00000014'] -assert blocks.successors(tob) == [tob] + 'JMP loc_key_3'] +assert asmcfg.successors(tob.loc_key) == [tob.loc_key] # Check split_block ## Without condition for a split, no change -blocks_bef = blocks.copy() -blocks.apply_splitting(mdis.symbol_pool) -assert blocks_bef == blocks +asmcfg_bef = asmcfg.copy() +asmcfg.apply_splitting(mdis.loc_db) +assert asmcfg_bef == asmcfg +open("graph5.dot", "w").write(asmcfg.dot()) ## Create conditions for a block split -inside_firstbbl = mdis.symbol_pool.getby_offset(4) +inside_firstbbl = mdis.loc_db.get_offset_location(4) tob.bto.add(AsmConstraintTo(inside_firstbbl)) -blocks.rebuild_edges() -assert len(blocks.pendings) == 1 -assert inside_firstbbl in blocks.pendings -blocks.apply_splitting(mdis.symbol_pool) +asmcfg.rebuild_edges() +assert len(asmcfg.pendings) == 1 +assert inside_firstbbl in asmcfg.pendings +asmcfg.apply_splitting(mdis.loc_db) ## Check result -assert len(blocks) == 6 -assert len(blocks.pendings) == 0 +assert len(asmcfg) == 6 +assert len(asmcfg.pendings) == 0 assert len(entry_block.lines) == 2 assert map(str, entry_block.lines) == ['XOR EAX, EAX', 'XOR EBX, EBX'] -assert len(blocks.successors(entry_block)) == 1 -newb = blocks.successors(entry_block)[0] +assert len(asmcfg.successors(entry_block.loc_key)) == 1 +lbl_newb = asmcfg.successors(entry_block.loc_key)[0] +newb = asmcfg.loc_key_to_block(lbl_newb) assert len(newb.lines) == 2 assert map(str, newb.lines) == ['XOR ECX, ECX', - 'JNZ loc_0000000000000014:0x00000014'] -preds = blocks.predecessors(newb) + 'JNZ loc_key_3'] +preds = asmcfg.predecessors(lbl_newb) assert len(preds) == 2 -assert entry_block in preds -assert tob in preds -assert blocks.edges2constraint[(entry_block, newb)] == AsmConstraint.c_next -assert blocks.edges2constraint[(tob, newb)] == AsmConstraint.c_to +assert entry_block.loc_key in preds +assert tob.loc_key in preds +assert asmcfg.edges2constraint[(entry_block.loc_key, lbl_newb)] == AsmConstraint.c_next +assert asmcfg.edges2constraint[(tob.loc_key, lbl_newb)] == AsmConstraint.c_to # Check double block split data = "74097405b8020000007405b803000000b804000000c3".decode('hex') cont = Container.from_string(data) mdis = dis_x86_32(cont.bin_stream) -blocks = mdis.dis_multiblock(0) +asmcfg = mdis.dis_multiblock(0) ## Check resulting disasm -assert len(blocks.nodes()) == 6 -blocks.sanity_check() +assert len(asmcfg.nodes()) == 6 +asmcfg.sanity_check() ## Check graph structure bbl0 = MatchGraphJoker(name="0") bbl2 = MatchGraphJoker(name="2") @@ -307,8 +318,18 @@ matcher = bbl0 >> bbl2 >> bbl4 >> bbl9 >> bblB >> bbl10 matcher += bbl2 >> bbl9 >> bbl10 matcher += bbl0 >> bblB -solutions = list(matcher.match(blocks)) +solutions = list(matcher.match(asmcfg)) assert len(solutions) == 1 solution = solutions.pop() -for jbbl, block in solution.iteritems(): - assert block.label.offset == int(jbbl._name, 16) +for jbbl, label in solution.iteritems(): + offset = mdis.loc_db.get_location_offset(label) + assert offset == int(jbbl._name, 16) + +loc_key_dum = mdis.loc_db.get_or_create_name_location("dummy_loc") +asmcfg.add_node(loc_key_dum) +error_raised = False +try: + asmcfg.sanity_check() +except RuntimeError: + error_raised = True +assert error_raised diff --git a/test/core/graph.py b/test/core/graph.py index 9f8afcae..b71c3d51 100644 --- a/test/core/graph.py +++ b/test/core/graph.py @@ -257,7 +257,7 @@ assert len([sol for sol in sols if sol[j1] == 1]) == 1 assert len([sol for sol in sols if sol[j1] == 2]) == 1 ## Check filter -j2 = MatchGraphJoker(name="son", restrict_out=False, filt=lambda node: node < 2) +j2 = MatchGraphJoker(name="son", restrict_out=False, filt=lambda graph, node: node < 2) matcher = j1 >> j2 >> j1 sols = list(matcher.match(graph)) assert len(sols) == 1 diff --git a/test/core/locationdb.py b/test/core/locationdb.py new file mode 100644 index 00000000..b9a5f707 --- /dev/null +++ b/test/core/locationdb.py @@ -0,0 +1,108 @@ +from miasm2.core.locationdb import LocationDB + + +# Basic tests (LocationDB description) +loc_db = LocationDB() +loc_key1 = loc_db.add_location() +loc_key2 = loc_db.add_location(offset=0x1234) +loc_key3 = loc_db.add_location(name="first_name") +loc_db.add_location_name(loc_key3, "second_name") +loc_db.set_location_offset(loc_key3, 0x5678) +loc_db.remove_location_name(loc_key3, "second_name") + +assert loc_db.get_location_offset(loc_key1) is None +assert loc_db.get_location_offset(loc_key2) == 0x1234 + +assert loc_db.pretty_str(loc_key1) == str(loc_key1) +assert loc_db.pretty_str(loc_key2) == "loc_1234" +assert loc_db.pretty_str(loc_key3) == "first_name" +loc_db.consistency_check() + +# Offset manipulation +loc_key4 = loc_db.add_location() +assert loc_db.get_location_offset(loc_key4) is None +loc_db.set_location_offset(loc_key4, 0x1122) +assert loc_db.get_location_offset(loc_key4) == 0x1122 +loc_db.unset_location_offset(loc_key4) +assert loc_db.get_location_offset(loc_key4) is None +try: + loc_db.set_location_offset(loc_key4, 0x1234) + has_raised = False +except KeyError: + has_raised = True +assert has_raised +assert loc_db.get_location_offset(loc_key4) is None +loc_db.set_location_offset(loc_key4, 0x1122) +try: + loc_db.set_location_offset(loc_key4, 0x1123) + has_raised = False +except ValueError: + has_raised = True +assert has_raised +assert loc_db.get_location_offset(loc_key4) == 0x1122 +loc_db.set_location_offset(loc_key4, 0x1123, force=True) +assert loc_db.get_location_offset(loc_key4) == 0x1123 +assert 0x1123 in loc_db.offsets +try: + loc_db.add_location(offset=0x1123) + has_raised = False +except ValueError: + has_raised = True +assert loc_db.add_location(offset=0x1123, strict=False) == loc_key4 +assert loc_db.get_offset_location(0x1123) == loc_key4 +assert loc_db.get_or_create_offset_location(0x1123) == loc_key4 +loc_key4_bis = loc_db.get_or_create_offset_location(0x1144) +assert loc_db.get_offset_location(0x1144) == loc_key4_bis +loc_db.consistency_check() + +# Names manipulation +loc_key5 = loc_db.add_location() +name1 = "name1" +name2 = "name2" +name3 = "name3" +assert len(loc_db.get_location_names(loc_key5)) == 0 +loc_db.add_location_name(loc_key5, name1) +loc_db.add_location_name(loc_key5, name2) +assert name1 in loc_db.names +assert name2 in loc_db.names +assert name1 in loc_db.get_location_names(loc_key5) +assert name2 in loc_db.get_location_names(loc_key5) +assert loc_db.get_name_location(name1) == loc_key5 +loc_db.remove_location_name(loc_key5, name1) +assert name1 not in loc_db.names +assert name1 not in loc_db.get_location_names(loc_key5) +try: + loc_db.remove_location_name(loc_key5, name1) + has_raised = False +except KeyError: + has_raised = True +try: + loc_db.add_location_name(loc_key1, name2) + has_raised = False +except KeyError: + has_raised = True +try: + loc_db.add_location(name=name2) + has_raised = False +except ValueError: + has_raised = True +assert loc_db.add_location(name=name2, strict=False) == loc_key5 +assert loc_db.get_or_create_name_location(name2) == loc_key5 +loc_key5_bis = loc_db.get_or_create_name_location(name3) +assert loc_db.get_name_location(name3) == loc_key5_bis +loc_db.consistency_check() + +# Merge +loc_db2 = LocationDB() +loc_db2.add_location(offset=0x3344) +loc_db2.add_location(name=name2) +loc_db.merge(loc_db2) +assert 0x3344 in loc_db.offsets +assert name2 in loc_db.names +loc_db.consistency_check() +assert loc_db.get_name_location(name2) == loc_key5 + +# Delete +loc_db.remove_location(loc_key5) +assert loc_db.get_name_location(name2) is None +loc_db.consistency_check() diff --git a/test/core/parse_asm.py b/test/core/parse_asm.py index 54f3be1d..ddb195d2 100755 --- a/test/core/parse_asm.py +++ b/test/core/parse_asm.py @@ -64,18 +64,19 @@ class TestParseAsm(unittest.TestCase): .string "toto" ''' - blocks, symbol_pool = parse_txt(mn_x86, 32, ASM0) + asmcfg, loc_db = parse_txt(mn_x86, 32, ASM0) patches = asm_resolve_final(mn_x86, - blocks, - symbol_pool) + asmcfg, + loc_db) lbls = [] for i in xrange(6): - lbls.append(symbol_pool.getby_name('lbl%d' % i)) + lbls.append(loc_db.get_name_location('lbl%d' % i)) # align test - assert(lbls[5].offset % 0x10 == 0) + offset = loc_db.get_location_offset(lbls[5]) + assert(offset % 0x10 == 0) lbl2block = {} - for block in blocks: - lbl2block[block.label] = block + for block in asmcfg.blocks: + lbl2block[block.loc_key] = block # dontsplit test assert(lbls[2] == lbl2block[lbls[1]].get_next()) assert(lbls[3] == lbl2block[lbls[2]].get_next()) @@ -94,13 +95,13 @@ class TestParseAsm(unittest.TestCase): RET ''' - blocks, symbol_pool = parse_txt(mn_x86, 32, ASM0) + asmcfg, loc_db = parse_txt(mn_x86, 32, ASM0) lbls = [] for i in xrange(2): - lbls.append(symbol_pool.getby_name('lbl%d' % i)) + lbls.append(loc_db.get_name_location('lbl%d' % i)) lbl2block = {} - for block in blocks: - lbl2block[block.label] = block + for block in asmcfg.blocks: + lbl2block[block.loc_key] = block # split test assert(lbl2block[lbls[1]].get_next() is None) diff --git a/test/core/sembuilder.py b/test/core/sembuilder.py index ebf9f385..f7a96b89 100644 --- a/test/core/sembuilder.py +++ b/test/core/sembuilder.py @@ -2,22 +2,23 @@ import inspect from pdb import pm from miasm2.core.sembuilder import SemBuilder +from miasm2.core.locationdb import LocationDB import miasm2.expression.expression as m2_expr -from miasm2.core.asmblock import AsmLabel + + # Test classes class IR(object): + def __init__(self, loc_db): + self.loc_db = loc_db IRDst = m2_expr.ExprId("IRDst", 32) def get_next_instr(self, _): - return AsmLabel("NEXT") - - def get_next_label(self, _): - return AsmLabel("NEXT") + return m2_expr.LocKey(0) - def gen_label(self): - return AsmLabel("GEN") + def get_next_loc_key(self, _): + return m2_expr.LocKey(0) class Instr(object): mode = 32 @@ -44,7 +45,8 @@ def test(Arg1, Arg2, Arg3): a = m2_expr.ExprId('A', 32) b = m2_expr.ExprId('B', 32) c = m2_expr.ExprId('C', 32) -ir = IR() +loc_db = LocationDB() +ir = IR(loc_db) instr = Instr() res = test(ir, instr, a, b, c) @@ -58,7 +60,7 @@ for statement in res[0]: print "[+] Blocks:" for irb in res[1]: - print irb.label + print irb.loc_key for assignblk in irb: for expr in assignblk: print expr diff --git a/test/expression/parser.py b/test/expression/parser.py index 9c01c8a1..1d5889fb 100644 --- a/test/expression/parser.py +++ b/test/expression/parser.py @@ -1,9 +1,10 @@ from miasm2.expression.parser import str_to_expr from miasm2.expression.expression import ExprInt, ExprId, ExprSlice, ExprMem, \ - ExprCond, ExprCompose, ExprOp, ExprAff + ExprCond, ExprCompose, ExprOp, ExprAff, ExprLoc, LocKey for expr_test in [ExprInt(0x12, 32), ExprId('test', 32), + ExprLoc(LocKey(12), 32), ExprSlice(ExprInt(0x10, 32), 0, 8), ExprMem(ExprInt(0x10, 32), 32), ExprCond(ExprInt(0x10, 32), ExprInt(0x11, 32), ExprInt(0x12, 32)), diff --git a/test/expression/simplifications.py b/test/expression/simplifications.py index a4e839cf..b2591a83 100644 --- a/test/expression/simplifications.py +++ b/test/expression/simplifications.py @@ -177,6 +177,10 @@ to_test = [(ExprInt(1, 32) - ExprInt(1, 32), ExprInt(0, 32)), (ExprInt(0x4142, 32)[:32], ExprInt(0x4142, 32)), (ExprInt(0x4142, 32)[:8], ExprInt(0x42, 8)), (ExprInt(0x4142, 32)[8:16], ExprInt(0x41, 8)), + (ExprOp('>>', ExprOp('<<', a, ExprInt(0x4, 32)), ExprInt(0x4, 32)), + ExprOp('&', a, ExprInt(0x0FFFFFFF, 32))), + (ExprOp('<<', ExprOp('>>', a, ExprInt(0x4, 32)), ExprInt(0x4, 32)), + ExprOp('&', a, ExprInt(0xFFFFFFF0, 32))), (a[:32], a), (a[:8][:8], a[:8]), (a[:16][:8], a[:8]), diff --git a/test/ir/symbexec.py b/test/ir/symbexec.py index 7d5bf44a..3158be60 100755 --- a/test/ir/symbexec.py +++ b/test/ir/symbexec.py @@ -10,10 +10,15 @@ class TestSymbExec(unittest.TestCase): from miasm2.expression.expression import ExprInt, ExprId, ExprMem, \ ExprCompose, ExprAff from miasm2.arch.x86.sem import ir_x86_32 + from miasm2.core.locationdb import LocationDB from miasm2.ir.symbexec import SymbolicExecutionEngine from miasm2.ir.ir import AssignBlock + loc_db = LocationDB() + ira = ir_x86_32(loc_db) + ircfg = ira.new_ircfg() + id_x = ExprId('x', 32) id_a = ExprId('a', 32) id_b = ExprId('b', 32) @@ -21,7 +26,7 @@ class TestSymbExec(unittest.TestCase): id_d = ExprId('d', 32) id_e = ExprId('e', 64) - sb = SymbolicExecutionEngine(ir_x86_32(), + sb = SymbolicExecutionEngine(ira, { ExprMem(ExprInt(0x4, 32), 8): ExprInt(0x44, 8), ExprMem(ExprInt(0x5, 32), 8): ExprInt(0x33, 8), @@ -222,16 +227,17 @@ class TestSymbExec(unittest.TestCase): assert found - sb_empty = SymbolicExecutionEngine(ir_x86_32(), {}) + sb_empty = SymbolicExecutionEngine(ira) sb_empty.dump() # Test memory full print 'full' - arch_addr8 = ir_x86_32() + arch_addr8 = ir_x86_32(loc_db) + ircfg = arch_addr8.new_ircfg() # Hack to obtain tiny address space arch_addr8.addrsize = 5 - sb_addr8 = SymbolicExecutionEngine(arch_addr8, {}) + sb_addr8 = SymbolicExecutionEngine(arch_addr8) sb_addr8.dump() # Fulfill memory sb_addr8.apply_change(ExprMem(ExprInt(0, 5), 256), ExprInt(0, 256)) diff --git a/test/ir/translators/z3_ir.py b/test/ir/translators/z3_ir.py index 6ae2dcd0..4806ad96 100644 --- a/test/ir/translators/z3_ir.py +++ b/test/ir/translators/z3_ir.py @@ -1,12 +1,16 @@ import z3 -from miasm2.core.asmblock import AsmLabel +from miasm2.core.locationdb import LocationDB from miasm2.expression.expression import * -from miasm2.ir.translators.translator import Translator -from miasm2.ir.translators.z3_ir import Z3Mem +from miasm2.ir.translators.z3_ir import Z3Mem, TranslatorZ3 # Some examples of use/unit tests. +loc_db = LocationDB() +translator1 = TranslatorZ3(endianness="<", loc_db=loc_db) +translator2 = TranslatorZ3(endianness=">", loc_db=loc_db) + + def equiv(z3_expr1, z3_expr2): s = z3.Solver() s.add(z3.Not(z3_expr1 == z3_expr2)) @@ -34,17 +38,17 @@ assert equiv(z3.BitVec('a', 32) + z3.BitVecVal(3, 32) - z3.BitVecVal(1, 32), # Z3Mem short tests # -------------------------------------------------------------------------- -mem = Z3Mem(endianness='<') # little endian +mem = Z3Mem(endianness='<') # little endian eax = z3.BitVec('EAX', 32) assert equiv( # @32[EAX] mem.get(eax, 32), # @16[EAX+2] . @16[EAX] - z3.Concat(mem.get(eax+2, 16), + z3.Concat(mem.get(eax+2, 16), mem.get(eax, 16))) # -------------------------------------------------------------------------- -ax = z3.BitVec('AX', 16) +ax = z3.BitVec('AX', 16) assert not equiv( # @16[EAX] with EAX = ZeroExtend(AX) mem.get(z3.ZeroExt(16, ax), 16), @@ -54,7 +58,7 @@ assert not equiv( # TranslatorZ3 tests # -------------------------------------------------------------------------- e = ExprId('x', 32) -ez3 = Translator.to_language('z3').from_expr(e) +ez3 = translator1.from_expr(e) z3_e = z3.BitVec('x', 32) assert equiv(ez3, z3_e) @@ -63,7 +67,7 @@ assert equiv(ez3, z3_e) four = ExprInt(4, 32) five = ExprInt(5, 32) e2 = (e + five + four) * five -ez3 = Translator.to_language('z3').from_expr(e2) +ez3 = translator1.from_expr(e2) z3_four = z3.BitVecVal(4, 32) z3_five = z3.BitVecVal(5, 32) @@ -74,7 +78,7 @@ assert equiv(ez3, z3_e2) emem = ExprMem(ExprInt(0xdeadbeef, 32), size=32) emem2 = ExprMem(ExprInt(0xfee1dead, 32), size=32) e3 = (emem + e) * ExprInt(2, 32) * emem2 -ez3 = Translator.to_language('z3').from_expr(e3) +ez3 = translator1.from_expr(e3) mem = Z3Mem() z3_emem = mem.get(z3.BitVecVal(0xdeadbeef, 32), 32) @@ -84,7 +88,7 @@ assert equiv(ez3, z3_e3) # -------------------------------------------------------------------------- e4 = emem * five -ez3 = Translator.to_language('z3').from_expr(e4) +ez3 = translator1.from_expr(e4) z3_e4 = z3_emem * z3_five assert equiv(ez3, z3_e4) @@ -98,7 +102,7 @@ check_interp(model[mem.get_mem_array(32)], [(0xdeadbeef, 2), (0xdeadbeef + 3, 0)]) # -------------------------------------------------------------------------- -ez3 = Translator.to_language("z3", endianness=">").from_expr(e4) +ez3 = translator2.from_expr(e4) memb = Z3Mem(endianness=">") z3_emem = memb.get(z3.BitVecVal(0xdeadbeef, 32), 32) @@ -115,7 +119,7 @@ check_interp(model[memb.get_mem_array(32)], # -------------------------------------------------------------------------- e5 = ExprSlice(ExprCompose(e, four), 0, 32) * five -ez3 = Translator.to_language('z3').from_expr(e5) +ez3 = translator1.from_expr(e5) z3_e5 = z3.Extract(31, 0, z3.Concat(z3_four, z3_e)) * z3_five assert equiv(ez3, z3_e5) @@ -126,7 +130,7 @@ seven = ExprInt(7, 32) one0seven = ExprInt(0x107, 32) for miasm_int, res in [(five, 1), (four, 0), (seven, 0), (one0seven, 0)]: e6 = ExprOp('parity', miasm_int) - ez3 = Translator.to_language('z3').from_expr(e6) + ez3 = translator1.from_expr(e6) z3_e6 = z3.BitVecVal(res, 1) assert equiv(ez3, z3_e6) @@ -134,37 +138,40 @@ for miasm_int, res in [(five, 1), (four, 0), (seven, 0), (one0seven, 0)]: # '-' for miasm_int, res in [(five, -5), (four, -4)]: e6 = ExprOp('-', miasm_int) - ez3 = Translator.to_language('z3').from_expr(e6) + ez3 = translator1.from_expr(e6) z3_e6 = z3.BitVecVal(res, 32) assert equiv(ez3, z3_e6) # -------------------------------------------------------------------------- -e7 = ExprId(AsmLabel("label_histoire", 0xdeadbeef), 32) -ez3 = Translator.to_language('z3').from_expr(e7) +label_histoire = loc_db.add_location("label_histoire", 0xdeadbeef) +e7 = ExprLoc(label_histoire, 32) +ez3 = translator1.from_expr(e7) z3_e7 = z3.BitVecVal(0xdeadbeef, 32) assert equiv(ez3, z3_e7) # Should just not throw anything to pass -e8 = ExprId(AsmLabel("label_jambe"), 32) -ez3 = Translator.to_language('z3').from_expr(e8) +lbl_e8 = loc_db.add_location("label_jambe") + +e8 = ExprLoc(lbl_e8, 32) +ez3 = translator1.from_expr(e8) assert not equiv(ez3, z3_e7) # -------------------------------------------------------------------------- # cntleadzeros, cnttrailzeros # cnttrailzeros(0x1138) == 3 -cnttrailzeros1 = Translator.to_language('z3').from_expr(ExprOp("cnttrailzeros", ExprInt(0x1138, 32))) +cnttrailzeros1 = translator1.from_expr(ExprOp("cnttrailzeros", ExprInt(0x1138, 32))) cnttrailzeros2 = z3.BitVecVal(3, 32) assert(equiv(cnttrailzeros1, cnttrailzeros2)) # cntleadzeros(0x11300) == 0xf -cntleadzeros1 = Translator.to_language('z3').from_expr(ExprOp("cntleadzeros", ExprInt(0x11300, 32))) +cntleadzeros1 = translator1.from_expr(ExprOp("cntleadzeros", ExprInt(0x11300, 32))) cntleadzeros2 = z3.BitVecVal(0xf, 32) assert(equiv(cntleadzeros1, cntleadzeros2)) # cnttrailzeros(0x8000) + 1 == cntleadzeros(0x8000) -cnttrailzeros3 = Translator.to_language('z3').from_expr(ExprOp("cnttrailzeros", ExprInt(0x8000, 32)) + ExprInt(1, 32)) -cntleadzeros3 = Translator.to_language('z3').from_expr(ExprOp("cntleadzeros", ExprInt(0x8000, 32))) +cnttrailzeros3 = translator1.from_expr(ExprOp("cnttrailzeros", ExprInt(0x8000, 32)) + ExprInt(1, 32)) +cntleadzeros3 = translator1.from_expr(ExprOp("cntleadzeros", ExprInt(0x8000, 32))) assert(equiv(cnttrailzeros3, cntleadzeros3)) print "TranslatorZ3 tests are OK." diff --git a/test/jitter/bad_block.py b/test/jitter/bad_block.py new file mode 100644 index 00000000..ae11e696 --- /dev/null +++ b/test/jitter/bad_block.py @@ -0,0 +1,43 @@ +import sys +from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE, EXCEPT_UNK_MNEMO +from miasm2.analysis.machine import Machine + +def code_sentinelle(jitter): + jitter.run = False + jitter.pc = 0 + return True + +machine = Machine("x86_32") +jitter = machine.jitter(sys.argv[1]) + +jitter.init_stack() + +# nop +# mov eax, 0x42 +# XX +data = "90b842000000ffff90909090".decode('hex') + +# Will raise memory error at 0x40000006 + +error_raised = False +def raise_me(jitter): + global error_raised + error_raised = True + assert jitter.pc == 0x40000006 + return False + +jitter.add_exception_handler(EXCEPT_UNK_MNEMO, raise_me) + +run_addr = 0x40000000 + +jitter.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) + +jitter.set_trace_log() +jitter.push_uint32_t(0x1337beef) + +jitter.add_breakpoint(0x1337beef, code_sentinelle) + +jitter.init_run(run_addr) +jitter.continue_run() + +assert error_raised is True diff --git a/test/jitter/jit_options.py b/test/jitter/jit_options.py index 4fe936d5..a0ddbc11 100644 --- a/test/jitter/jit_options.py +++ b/test/jitter/jit_options.py @@ -33,8 +33,7 @@ def init_jitter(): # Init jitter myjit.init_stack() - myjit.jit.log_regs = True - myjit.jit.log_mn = True + myjit.set_trace_log() myjit.push_uint32_t(0x1337beef) myjit.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/test/jitter/jmp_out_mem.py b/test/jitter/jmp_out_mem.py new file mode 100644 index 00000000..93ae8304 --- /dev/null +++ b/test/jitter/jmp_out_mem.py @@ -0,0 +1,46 @@ +import sys +from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE, EXCEPT_ACCESS_VIOL +from miasm2.analysis.machine import Machine + +def code_sentinelle(jitter): + jitter.run = False + jitter.pc = 0 + return True + + +machine = Machine("x86_32") +jitter = machine.jitter(sys.argv[1]) + +jitter.init_stack() + +# nop +# mov eax, 0x42 +# jmp 0x20 + +data = "90b842000000eb20".decode('hex') + +# Will raise memory error at 0x40000028 + +error_raised = False +def raise_me(jitter): + global error_raised + error_raised = True + assert jitter.pc == 0x40000028 + return False + +jitter.add_exception_handler(EXCEPT_ACCESS_VIOL, raise_me) + + +run_addr = 0x40000000 + +jitter.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) + +jitter.set_trace_log() +jitter.push_uint32_t(0x1337beef) + +jitter.add_breakpoint(0x1337beef, code_sentinelle) + +jitter.init_run(run_addr) +jitter.continue_run() + +assert error_raised is True diff --git a/test/jitter/test_post_instr.py b/test/jitter/test_post_instr.py index 3e68d58e..39e87616 100644 --- a/test/jitter/test_post_instr.py +++ b/test/jitter/test_post_instr.py @@ -1,6 +1,6 @@ +import sys from miasm2.analysis.machine import Machine from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE, EXCEPT_BREAKPOINT_MEMORY, EXCEPT_ACCESS_VIOL -import sys machine = Machine("x86_32") jitter = machine.jitter(sys.argv[1]) @@ -23,8 +23,8 @@ jitter.vm.add_memory_page(0x1000, PAGE_READ|PAGE_WRITE, "\x00"*0x1000, "code pag # RET jitter.vm.set_mem(0x1000, "B844332211C3".decode('hex')) -jitter.jit.log_mn = True -jitter.jit.log_regs = True + +jitter.set_trace_log() def do_not_raise_me(jitter): raise ValueError("Should not be here") @@ -41,6 +41,3 @@ try: jitter.continue_run() except AssertionError: assert jitter.vm.get_exception() == EXCEPT_ACCESS_VIOL -except RuntimeError: - assert sys.argv[1] == 'python' - assert jitter.vm.get_exception() == EXCEPT_ACCESS_VIOL diff --git a/test/test_all.py b/test/test_all.py index 52873f4b..40df315c 100755 --- a/test/test_all.py +++ b/test/test_all.py @@ -59,7 +59,6 @@ class ArchUnitTest(RegressionTest): # script -> blacklisted jitter blacklist = { "x86/unit/mn_float.py": ["python", "llvm"], - "x86/unit/mn_div.py": ["gcc"], } for script in ["x86/sem.py", "x86/unit/mn_strings.py", @@ -98,6 +97,8 @@ for script in ["x86/sem.py", tags = [TAGS[jitter]] if jitter in TAGS else [] testset += ArchUnitTest(script, jitter, base_dir="arch", tags=tags) +testset += ArchUnitTest("x86/unit/access_xmm.py", "python", base_dir="arch") + ### QEMU regression tests class QEMUTest(RegressionTest): """Test against QEMU regression tests @@ -231,6 +232,7 @@ for script in ["interval.py", "parse_asm.py", "utils.py", "sembuilder.py", + "locationdb.py", "test_types.py", ]: testset += RegressionTest([script], base_dir="core") @@ -379,6 +381,8 @@ for script in ["jitload.py", "vm_mngr.py", "jit_options.py", "test_post_instr.py", + "bad_block.py", + "jmp_out_mem.py", ]: for engine in ArchUnitTest.jitter_engines: testset += RegressionTest([script, engine], base_dir="jitter", |