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-rw-r--r--test/arch/aarch64/arch.py6
-rw-r--r--test/arch/aarch64/unit/asm_test.py1
-rw-r--r--test/arch/arm/arch.py225
-rwxr-xr-xtest/arch/arm/sem.py4
-rw-r--r--test/arch/mips32/arch.py5
-rw-r--r--test/arch/mips32/unit/asm_test.py3
-rw-r--r--test/arch/msp430/arch.py5
-rw-r--r--test/arch/sh4/arch.py6
-rw-r--r--test/arch/x86/arch.py60
-rwxr-xr-xtest/arch/x86/sem.py5
-rw-r--r--test/arch/x86/unit/asm_test.py1
-rw-r--r--test/core/asmblock.py2
-rwxr-xr-xtest/core/test_types.py2
-rwxr-xr-xtest/ir/ir2C.py2
14 files changed, 257 insertions, 70 deletions
diff --git a/test/arch/aarch64/arch.py b/test/arch/aarch64/arch.py
index 8364fcf1..a6aa7ba5 100644
--- a/test/arch/aarch64/arch.py
+++ b/test/arch/aarch64/arch.py
@@ -1,6 +1,10 @@
 import sys
 import time
+from pdb import pm
 from miasm2.arch.aarch64.arch import *
+from miasm2.core.asmblock import AsmSymbolPool
+
+symbol_pool = AsmSymbolPool()
 
 reg_tests_aarch64 = [
     ("XXXXXXXX    MOV        W1, WZR",
@@ -1810,7 +1814,7 @@ for s, l in reg_tests_aarch64[:]:
     print s
     print mn
     assert(str(mn) == s)
-    l = mn_aarch64.fromstring(s, 'l')
+    l = mn_aarch64.fromstring(s, symbol_pool, 'l')
     assert(str(l) == s)
     a = mn_aarch64.asm(l)
     print [x for x in a]
diff --git a/test/arch/aarch64/unit/asm_test.py b/test/arch/aarch64/unit/asm_test.py
index ddb8a08c..ca27ef9d 100644
--- a/test/arch/aarch64/unit/asm_test.py
+++ b/test/arch/aarch64/unit/asm_test.py
@@ -1,7 +1,6 @@
 import sys
 import os
 
-from miasm2.core.cpu import ParseAst
 from miasm2.arch.aarch64.arch import mn_aarch64, base_expr, variable
 from miasm2.core import parse_asm
 from miasm2.expression.expression import *
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py
index 3ba2dbd4..90d137d0 100644
--- a/test/arch/arm/arch.py
+++ b/test/arch/arm/arch.py
@@ -1,6 +1,10 @@
 import time
 from miasm2.arch.arm.arch import *
+from miasm2.core.asmblock import AsmSymbolPool
+from pdb import pm
 
+
+symbol_pool = AsmSymbolPool()
 if 0:
     a = bs('00')
     b = bs('01')
@@ -266,7 +270,7 @@ for s, l in reg_tests_arm:
     assert(str(mn) == s)
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
-    l = mn_arm.fromstring(s, 'l')
+    l = mn_arm.fromstring(s, symbol_pool, 'l')
     # print l
     assert(str(l) == s)
     a = mn_arm.asm(l)
@@ -314,6 +318,9 @@ reg_tests_armt = [
     # adcs
     # sbcs
     # rors
+    ("003258b6    RORS       R3, R2",
+     "D341"),
+
     ("0017b754    TST        R0, R2",
      "1042"),
     ("0006e3fc    NEGS       R5, R5",
@@ -401,6 +408,8 @@ reg_tests_armt = [
      "0cb0"),
     ("0006c1b0    SUB        SP, 0x18",
      "86b0"),
+    ("0006ff5c    SUB        SP, SP, 0x670",
+     "ADF5CE6D"),
 
 
     ("0006aeee    POP        {R4, PC}",
@@ -435,7 +444,7 @@ reg_tests_armt = [
      "f2e7"),
     ("C010163C    BLX        0x1F916C",
      "F9F1B6E8"),
-    ("C01015E8    BL         0x1F8D5C",
+    ("C01015E8    BL         0x1F8D60",
      "F8F1AEFE"),
 
 
@@ -489,6 +498,215 @@ reg_tests_armt = [
     ("xxxxxxxx    WFI        ",
      "30bf"),
 
+
+    ("xxxxxxxx    PUSH       {R4-R8, LR}",
+     "2DE9F041"),
+    ("xxxxxxxx    POP        {R4-R8, PC}",
+     "BDE8F081"),
+    ("xxxxxxxx    MOV        R12, 0x3",
+     "4FF0030C"),
+    ("xxxxxxxx    MOVS       R12, 0x3",
+     "5FF0030C"),
+    ("xxxxxxxx    ASR        R7, R3, R6",
+     "43FA06F7"),
+    ("xxxxxxxx    LSL        LR, R12, R7",
+     "0CFA07FE"),
+    ("xxxxxxxx    MVN        LR, LR",
+     "6FEA0E0E"),
+    ("xxxxxxxx    AND        R5, LR, R5",
+     "0EEA0505"),
+    ("xxxxxxxx    ORR        R5, R8, R5",
+     "48EA0505"),
+    ("xxxxxxxx    ORR        R5, R8, R5",
+     "48EA0505"),
+    ("xxxxxxxx    MOV        R0, 0x600",
+     "4FF4C060"),
+    ("xxxxxxxx    MOV        R0, 0x811",
+     "40F61100"),
+    ("xxxxxxxx    MOV        R1, R1 LSL 0x10",
+     "4FEA0141"),
+
+
+    ("xxxxxxxx    ADD        R1, R4, 0x30",
+     "04F13001"),
+
+    ("xxxxxxxx    SDIV       R3, R5, R2",
+     "95FBF2F3"),
+
+    ("xxxxxxxx    MLS        R5, R2, R3, R5",
+     "02FB1355"),
+
+    ("xxxxxxxx    SMLABB     R2, R2, R3, R1",
+     "12FB0312"),
+    ("xxxxxxxx    SMLABT     R2, R2, R3, R1",
+     "12FB1312"),
+    ("xxxxxxxx    SMLATB     R2, R2, R3, R1",
+     "12FB2312"),
+    ("xxxxxxxx    SMLATT     R2, R2, R3, R1",
+     "12FB3312"),
+
+    ("xxxxxxxx    BIC        R1, R1, R3",
+     "21EA0301"),
+    ("xxxxxxxx    BIC        R4, R0, 0x400",
+     "20F48064"),
+    ("xxxxxxxx    ADD        R3, R1, R3 LSL 0x1",
+     "01EB4303"),
+    ("xxxxxxxx    SUB        R3, R0, 0x22",
+     "A0F12203"),
+    ("xxxxxxxx    UDIV       R3, R3, R1",
+     "B3FBF1F3"),
+    ("xxxxxxxx    MLA        R2, R6, R3, R2",
+     "06FB0322"),
+
+    ("xxxxxxxx    SUB        LR, R3, R2",
+     "A3EB020E"),
+
+    ("xxxxxxxx    ADD        R3, R3, 0x908",
+     "03F60813"),
+
+    ("xxxxxxxx    ADD        R3, R3, 0x23800",
+     "03F50E33"),
+
+
+
+
+    ("xxxxxxxx    B          0x4",
+     "00F000B8"),
+    #("xxxxxxxx    BEQ        0x4",
+    # "00F000A8"),
+    ("xxxxxxxx    BEQ        0x1D4",
+     "00F0E880"),
+
+
+    ("xxxxxxxx    UBFX       R1, R1, 0x0, 0x9",
+     "C1F30801"),
+    ("xxxxxxxx    UXTH       R9, R8",
+     "1FFA88F9"),
+
+    ("xxxxxxxx    AND        R2, R0, 0x1F",
+     "00F01F02"),
+    ("xxxxxxxx    RSB        R3, R3, 0x4",
+     "C3F10403"),
+    ("xxxxxxxx    RSB        R9, R9, R9 LSL 0x4",
+     "C9EB0919"),
+
+
+    ("xxxxxxxx    ITT        EQ",
+     "04BF"),
+    ("xxxxxxxx    ITE        EQ",
+     "0CBF"),
+    ("xxxxxxxx    ITT        HI",
+     "84BF"),
+    ("xxxxxxxx    ITTT       LT",
+     "BEBF"),
+    ("xxxxxxxx    ITE        NE",
+     "14BF"),
+
+    ("xxxxxxxx    STR        R5, [R0, 0xDC]",
+     "C0F8DC50"),
+    ("xxxxxxxx    STRB       R1, [R5, 0x4C]",
+     "85F84C10"),
+    ("xxxxxxxx    STRB       R2, [R3], 0x1",
+     "03F8012B"),
+    ("xxxxxxxx    STRH       R3, [R0, 0xE0]",
+     "A0F8E030"),
+    ("xxxxxxxx    STRH       R3, [R0], 0x2",
+     "20F8023B"),
+
+
+    ("xxxxxxxx    LDR        R3, [R0, 0xDC]",
+     "D0F8DC30"),
+    ("xxxxxxxx    LDR        R4, [SP], 0x4",
+     "5DF8044B"),
+    ("xxxxxxxx    LDRH       R3, [SP, 0x20]",
+     "BDF82030"),
+
+    ("xxxxxxxx    LDRB       R3, [R3, 0xFFFFFFF8]",
+     "13F8083C"),
+    ("xxxxxxxx    LDRB       R2, [R3, 0x30]",
+     "93F83020"),
+    ("xxxxxxxx    LDRB       R5, [R8, R6]",
+     "18F80650"),
+    ("xxxxxxxx    LDR        R3, [R4, R3 LSL 0x2]",
+     "54F82330"),
+    ("xxxxxxxx    LDRSB      R2, [R4, 0x30]",
+     "94F93020"),
+    ("xxxxxxxx    LDRH       R3, [R1], 0x2",
+     "31F8023B"),
+    ("xxxxxxxx    LDRH       R9, [SP, 0x14]",
+     "BDF81490"),
+
+    ("xxxxxxxx    STR        R3, [R2, 0xFFFFFFE4]",
+     "42F81C3C"),
+
+
+
+    ("xxxxxxxx    STR        R1, [R0, R3 LSL 0x2]",
+     "40F82310"),
+
+    ("xxxxxxxx    CLZ        R3, R3",
+     "B3FA83F3"),
+
+    ("xxxxxxxx    MOV        R0, 0x603",
+     "40F20360"),
+    ("xxxxxxxx    TBB        [PC, R0]",
+     "DFE800F0"),
+    ("xxxxxxxx    TBH        [PC, R0 LSL 0x1]",
+     "DFE810F0"),
+
+
+    ("xxxxxxxx    STRD       R5, R5, [R2, 0xFFFFFFF0]",
+     "42E90455"),
+
+    ("xxxxxxxx    MOV        R3, R3 ROR 0x19",
+     "4FEA7363"),
+    ("xxxxxxxx    MOV        R5, R5 LSL 0x3",
+     "4FEAC505"),
+
+
+    ("xxxxxxxx    SUB        R3, R3, 0x6BE",
+     "A3F2BE63"),
+
+    ("xxxxxxxx    PLD        [R0]",
+     "90F800F0"),
+
+    ("xxxxxxxx    LDRD       R2, R3, [R1]",
+     "D1E90023"),
+
+    ("xxxxxxxx    TST        R4, 0x4",
+     "14F0040F"),
+
+    ("xxxxxxxx    ORN        R2, R2, R5",
+     "62EA0502"),
+
+    ("xxxxxxxx    UADD8      R2, R2, R12",
+     "82FA4CF2"),
+
+    ("xxxxxxxx    SEL        R2, R4, R12",
+     "A4FA8CF2"),
+
+    ("xxxxxxxx    REV        R2, R2",
+     "12BA"),
+
+    ("xxxxxxxx    ADD        R8, SP, 0xC8",
+     "0DF1C808"),
+
+    ("xxxxxxxx    CMP        R9, 0x80",
+     "B9F1800F"),
+
+    ("xxxxxxxx    MUL        R2, R1, R2",
+     "01FB02F2"),
+
+    ("xxxxxxxx    LDRSH      R3, [R4, 0xC]",
+     "B4F90C30"),
+
+    ("xxxxxxxx    EOR        R3, R3, R1",
+     "83EA0103"),
+
+    ("xxxxxxxx    DSB        SY",
+     "bff34f8f"),
+
+
 ]
 print "#" * 40, 'armthumb', '#' * 40
 
@@ -504,9 +722,10 @@ for s, l in reg_tests_armt:
     assert(str(mn) == s)
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
-    l = mn_armt.fromstring(s, 'l')
+    l = mn_armt.fromstring(s, symbol_pool, 'l')
     # print l
     assert(str(l) == s)
+    print 'Asm..', l
     a = mn_armt.asm(l)
     print [x for x in a]
     print repr(b)
diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py
index 1b14214e..d9e6aa76 100755
--- a/test/arch/arm/sem.py
+++ b/test/arch/arm/sem.py
@@ -9,11 +9,13 @@ from miasm2.arch.arm.arch import mn_arm as mn
 from miasm2.arch.arm.sem import ir_arml as ir_arch
 from miasm2.arch.arm.regs import *
 from miasm2.expression.expression import *
+from miasm2.core.asmblock import AsmSymbolPool
 from pdb import pm
 
 logging.getLogger('cpuhelper').setLevel(logging.ERROR)
 EXCLUDE_REGS = set([ir_arch().IRDst])
 
+symbol_pool = AsmSymbolPool()
 
 def M(addr):
     return ExprMem(ExprInt(addr, 16), 16)
@@ -24,7 +26,7 @@ def compute(asm, inputstate={}, debug=False):
     sympool.update({k: ExprInt(v, k.size) for k, v in inputstate.iteritems()})
     interm = ir_arch()
     symexec = SymbolicExecutionEngine(interm, sympool)
-    instr = mn.fromstring(asm, "l")
+    instr = mn.fromstring(asm, symbol_pool, "l")
     code = mn.asm(instr)[0]
     instr = mn.dis(code, "l")
     instr.offset = inputstate.get(PC, 0)
diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py
index b28e2583..c6b68c0c 100644
--- a/test/arch/mips32/arch.py
+++ b/test/arch/mips32/arch.py
@@ -1,8 +1,11 @@
 import time
 from pdb import pm
 
+from miasm2.core.asmblock import AsmSymbolPool
 from miasm2.arch.mips32.arch import *
 
+symbol_pool = AsmSymbolPool()
+
 reg_tests_mips32 = [
     ("004496D8    ADDU       GP, GP, T9",
      "0399E021"),
@@ -227,7 +230,7 @@ for s, l in reg_tests_mips32:
     assert(str(mn) == s)
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
-    l = mn_mips32.fromstring(s, 'b')
+    l = mn_mips32.fromstring(s, symbol_pool, 'b')
     # print l
     assert(str(l) == s)
     a = mn_mips32.asm(l, 'b')
diff --git a/test/arch/mips32/unit/asm_test.py b/test/arch/mips32/unit/asm_test.py
index 9281f1b6..f03a32d7 100644
--- a/test/arch/mips32/unit/asm_test.py
+++ b/test/arch/mips32/unit/asm_test.py
@@ -1,8 +1,7 @@
 import sys
 import os
 
-from miasm2.core.cpu import ParseAst
-from miasm2.arch.mips32.arch import mn_mips32, base_expr, variable
+from miasm2.arch.mips32.arch import mn_mips32
 from miasm2.core import parse_asm
 from miasm2.expression.expression import *
 from miasm2.core import asmblock
diff --git a/test/arch/msp430/arch.py b/test/arch/msp430/arch.py
index b3dbac82..3df2becb 100644
--- a/test/arch/msp430/arch.py
+++ b/test/arch/msp430/arch.py
@@ -1,6 +1,9 @@
 import time
+from pdb import pm
 from miasm2.arch.msp430.arch import *
+from miasm2.core.asmblock import AsmSymbolPool
 
+symbol_pool = AsmSymbolPool()
 
 def h2i(s):
     return s.replace(' ', '').decode('hex')
@@ -94,7 +97,7 @@ for s, l in reg_tests_msp:
     assert(str(mn) == s)
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
-    l = mn_msp430.fromstring(s, None)
+    l = mn_msp430.fromstring(s, symbol_pool, None)
     # print l
     assert(str(l) == s)
     a = mn_msp430.asm(l)
diff --git a/test/arch/sh4/arch.py b/test/arch/sh4/arch.py
index 4d173add..574dcf49 100644
--- a/test/arch/sh4/arch.py
+++ b/test/arch/sh4/arch.py
@@ -1,6 +1,10 @@
 import time
+from pdb import pm
 from sys import stderr
 from miasm2.arch.sh4.arch import *
+from miasm2.core.asmblock import AsmSymbolPool
+
+symbol_pool = AsmSymbolPool()
 
 def h2i(s):
     return s.replace(' ', '').decode('hex')
@@ -396,7 +400,7 @@ for s, l in reg_tests_sh4:
     assert(str(mn) == s)
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
-    l = mn_sh4.fromstring(s, None)
+    l = mn_sh4.fromstring(s, symbol_pool, None)
     # print l
     assert(str(l) == s)
     a = mn_sh4.asm(l)
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py
index 7b834e2c..05b31815 100644
--- a/test/arch/x86/arch.py
+++ b/test/arch/x86/arch.py
@@ -1,19 +1,13 @@
 import time
+from pdb import pm
 import miasm2.expression.expression as m2_expr
-from miasm2.arch.x86.arch import mn_x86, deref_mem_ad, ParseAst, ast_int2expr, \
+from miasm2.arch.x86.arch import mn_x86, deref_mem_ad, \
     base_expr, rmarg, print_size
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
 from miasm2.core.bin_stream import bin_stream_str
+from miasm2.core.asmblock import AsmSymbolPool
 
-for s in ["[EAX]",
-          "[0x10]",
-          "[EBX + 0x10]",
-          "[EBX + ECX*0x10]",
-          "[EBX + ECX*0x10 + 0x1337]"]:
-    (e, a, b) = deref_mem_ad.scanString(s).next()
-    print 'expr', e[0]
-
-print '---'
+symbol_pool = AsmSymbolPool()
 
 mylabel16 = m2_expr.ExprId('mylabel16', 16)
 mylabel32 = m2_expr.ExprId('mylabel32', 32)
@@ -26,32 +20,6 @@ reg_and_id.update({'mylabel16': mylabel16,
                    })
 
 
-def my_ast_id2expr(t):
-    r = reg_and_id.get(t, m2_expr.ExprId(t, size=32))
-    return r
-
-my_var_parser = ParseAst(my_ast_id2expr, ast_int2expr)
-base_expr.setParseAction(my_var_parser)
-
-for s in ['EAX',
-          "BYTE PTR [EAX]",
-          "WORD PTR [EAX]",
-          "DWORD PTR [ECX+0x1337]",
-          "QWORD PTR [RAX+4*RCX + 0x1337]",
-          "DWORD PTR [EAX+EBX]",
-          "QWORD PTR [RAX+RBX+0x55667788]",
-          "BYTE PTR CS:[EAX]",
-          "QWORD PTR [RAX+RBX+mylabel64]",
-          "BYTE PTR [RAX+RBX+mylabel64]",
-          "BYTE PTR [AX+BX+mylabel16]",
-          "BYTE PTR [mylabel32]",
-          ]:
-    print '*' * 80
-    print s
-    (e, a, b) = rmarg.scanString(s).next()
-    print 'expr', e[0]
-    e[0].visit(print_size)
-
 
 def h2i(s):
     return int(s.replace(' ', '').decode('hex')[::].encode('hex'), 16)
@@ -3080,27 +3048,9 @@ reg_tests = [
 ]
 
 
-    # mode = 64
-    # l = mn_x86.dis('\x4D\x11\x7c\x18\x00', mode)
-    # print l
-    #"""
-    # mode = 64
-    # l = mn_x86.fromstring("ADC      DWORD PTR [RAX], 0x11223344", mode)
-    # print 'xx'
-    # t= time.time()
-    # import cProfile
-    # def f():
-    #    x = l.asm(mode)
-    #    print x
-    # cProfile.run('f()')
-    # l.asm(mode)
-    # print time.time()-t
-# reg_tests = reg_tests[-1:]
-
 test_file = {16: open('regression_test16_ia32.bin', 'w'),
              32: open('regression_test32_ia32.bin', 'w'),
              64: open('regression_test64_ia32.bin', 'w')}
-             # 64: open('testmnemo', 'r+')}
 ts = time.time()
 for mode, s, l, in reg_tests:
     print "-" * 80
@@ -3115,7 +3065,7 @@ for mode, s, l, in reg_tests:
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
     print 'fromstring', repr(s)
-    l = mn_x86.fromstring(s, mode)
+    l = mn_x86.fromstring(s, symbol_pool, mode)
     # print l
     print 'str args', [(str(x), x.size) for x in l.args]
     assert(str(l).strip(' ') == s)
diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py
index eb3c15c0..b3b7e940 100755
--- a/test/arch/x86/sem.py
+++ b/test/arch/x86/sem.py
@@ -14,11 +14,14 @@ from miasm2.arch.x86.regs import *
 from miasm2.expression.expression import *
 from miasm2.expression.simplifications      import expr_simp
 from miasm2.core import parse_asm, asmblock
+from miasm2.core.asmblock import AsmSymbolPool
 
 
 logging.getLogger('cpuhelper').setLevel(logging.ERROR)
 EXCLUDE_REGS = set([ir_32().IRDst, ir_64().IRDst])
 
+symbol_pool = AsmSymbolPool()
+
 m32 = 32
 m64 = 64
 
@@ -35,7 +38,7 @@ def symb_exec(interm, inputstate, debug):
             if k not in EXCLUDE_REGS and regs_init.get(k, None) != v}
 
 def compute(ir, mode, asm, inputstate={}, debug=False):
-    instr = mn.fromstring(asm, mode)
+    instr = mn.fromstring(asm, symbol_pool, mode)
     code = mn.asm(instr)[0]
     instr = mn.dis(code, mode)
     instr.offset = inputstate.get(EIP, 0)
diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py
index 8a6b215c..961967f9 100644
--- a/test/arch/x86/unit/asm_test.py
+++ b/test/arch/x86/unit/asm_test.py
@@ -1,7 +1,6 @@
 import sys
 import os
 
-from miasm2.core.cpu import ParseAst
 from miasm2.arch.x86.arch import mn_x86, base_expr, variable
 from miasm2.core import parse_asm
 from miasm2.expression.expression import *
diff --git a/test/core/asmblock.py b/test/core/asmblock.py
index eb7b54b2..7f0dbc5f 100644
--- a/test/core/asmblock.py
+++ b/test/core/asmblock.py
@@ -41,6 +41,8 @@ assert len(blocks.pendings) == 0
 assert len(blocks.nodes()) == 17
 assert len(blocks.edges2constraint) == len(blocks.edges())
 assert len(blocks.edges()) == 24
+assert blocks.getby_offset(0x63).lines[0].offset == 0x5f
+assert blocks.getby_offset(0x69).lines[0].offset == 0x69
 
 ## Convert to dot
 open("graph.dot", "w").write(blocks.dot())
diff --git a/test/core/test_types.py b/test/core/test_types.py
index ab1d47c4..0b5f6baa 100755
--- a/test/core/test_types.py
+++ b/test/core/test_types.py
@@ -465,7 +465,7 @@ assert Union([("f2", Num("B")), ("f2", Num("H"))]) != \
 assert Union([("f1", Num("B")), ("f2", Num("H"))]) != \
         Union([("f1", Num("I")), ("f2", Num("H"))])
 assert Bits(Num("I"), 3, 8) == Bits(Num("I"), 3, 8)
-assert Bits(Num("I"), 3, 8) != Bits(Num("I"), 3, 8)
+assert (Bits(Num("I"), 3, 8) != Bits(Num("I"), 3, 8)) is False
 assert Bits(Num("H"), 2, 8) != Bits(Num("I"), 3, 8)
 assert Bits(Num("I"), 3, 7) != Bits(Num("I"), 3, 8)
 assert BitField(Num("B"), [("f1", 2), ("f2", 4), ("f3", 1)]) == \
diff --git a/test/ir/ir2C.py b/test/ir/ir2C.py
index a966938b..c84473c3 100755
--- a/test/ir/ir2C.py
+++ b/test/ir/ir2C.py
@@ -40,7 +40,7 @@ class TestIrIr2C(unittest.TestCase):
         self.translationTest(
             ExprOp('bsr',     *args[:1]), r'x86_bsr(0x0, 0x20)')
         self.translationTest(
-            ExprOp('cpuid0',  *args[:2]), r'cpuid0(0x0, 0x1)')
+            ExprOp('cpuid',  *args[:2]), r'cpuid(0x0, 0x1)')
         self.translationTest(
             ExprOp('fcom0',   *args[:2]), r'fcom0(0x0, 0x1)')
         self.translationTest(