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-rw-r--r--test/analysis/depgraph.py2
-rw-r--r--test/arch/arm/arch.py9
-rw-r--r--test/arch/mips32/arch.py38
-rwxr-xr-xtest/arch/msp430/sem.py6
-rw-r--r--test/arch/ppc32/arch.py8
-rwxr-xr-xtest/arch/x86/sem.py6
-rw-r--r--test/core/graph.py22
-rw-r--r--test/expression/expression.py45
-rw-r--r--test/expression/simplifications.py1
-rw-r--r--test/ir/translators/smt2.py4
-rw-r--r--test/ir/translators/z3_ir.py17
-rwxr-xr-xtest/test_all.py13
-rw-r--r--test/utils/testset.py2
13 files changed, 154 insertions, 19 deletions
diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py
index 69b93f69..eb6507dc 100644
--- a/test/analysis/depgraph.py
+++ b/test/analysis/depgraph.py
@@ -748,7 +748,7 @@ def flatNode(node):
         if isinstance(node.element, ExprId):
             element = node.element.name
         elif isinstance(node.element, ExprInt):
-            element = int(node.element.arg)
+            element = int(node.element)
         else:
             RuntimeError("Unsupported type '%s'" % type(enode.element))
         names = loc_db.get_location_names(node.loc_key)
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py
index 5aa619ea..740655da 100644
--- a/test/arch/arm/arch.py
+++ b/test/arch/arm/arch.py
@@ -233,6 +233,15 @@ reg_tests_arm = [
     ('XXXXXXXX    PKHTB      R1, R2, R3 ASR 0x20',
      '531082e6'),
 
+    ('XXXXXXXX    MRC        p15, 0x0, R0, c1, c1, 0x0',
+     '110f11ee'),
+    ('XXXXXXXX    MCR        p15, 0x0, R8, c2, c0, 0x0',
+     '108f02ee'),
+    ('XXXXXXXX    MRCNE      p15, 0x0, R0, c1, c1, 0x0',
+     '110f111e'),
+    ('XXXXXXXX    MCRCC      p15, 0x0, R8, c2, c0, 0x1',
+     '308f023e'),
+
 
 ]
 ts = time.time()
diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py
index e5e8cff6..de6d4547 100644
--- a/test/arch/mips32/arch.py
+++ b/test/arch/mips32/arch.py
@@ -214,6 +214,44 @@ reg_tests_mips32 = [
 
     ("XXXXXXXX    LDC1       F22, 0xFFFF9148(V0)",
      "D4569148"),
+
+    ("XXXXXXXX    BEQL       S0, V0, 0x124",
+     "52020048"),
+    ("XXXXXXXX    BGEZL      T3, 0x24",
+     "05630008"),
+    ("XXXXXXXX    BNEL       A0, ZERO, 0x2C",
+     "5480000A"),
+    ("XXXXXXXX    BLTZL      S6, 0x5C",
+     "06C20016"),
+    ("XXXXXXXX    BLEZL      V1, 0x80",
+     "5860001F"),
+    ("XXXXXXXX    BGTZL      S4, 0x14",
+     "5E800004"),
+    ("XXXXXXXX    BC1FL      FCC0, 0x24",
+     "45020008"),
+    ("XXXXXXXX    BC1TL      FCC0, 0xB8",
+     "4503002D"),
+
+    ("XXXXXXXX    CLZ        K0, K1",
+     "737AD020"),
+
+    ("XXXXXXXX    LL         A0, 0x123(A1)",
+     "C0A40123"),
+    ("XXXXXXXX    SC         A1, 0x123(A0)",
+     "E0850123"),
+
+    ("XXXXXXXX    SYNC       0x19",
+     "0000064F"),
+    ("XXXXXXXX    TLBR       ",
+     "42000001"),
+
+    ("XXXXXXXX    ERET       ",
+     "42000018"),
+
+    ("XXXXXXXX    MTHI       A0",
+     "00800011"),
+    ("XXXXXXXX    MTLO       A1",
+     "00A00013")
 ]
 
 
diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py
index 2aca66ed..cb101937 100755
--- a/test/arch/msp430/sem.py
+++ b/test/arch/msp430/sem.py
@@ -39,10 +39,12 @@ def compute(asm, inputstate={}, debug=False):
         for k, v in viewitems(symexec.symbols):
             if regs_init.get(k, None) != v:
                 print(k, v)
-    return {
-        k: v.arg.arg for k, v in viewitems(symexec.symbols)
+
+    result =  {
+        k: int(v) for k, v in viewitems(symexec.symbols)
         if k not in EXCLUDE_REGS and regs_init.get(k, None) != v
     }
+    return result
 
 
 class TestMSP430Semantic(unittest.TestCase):
diff --git a/test/arch/ppc32/arch.py b/test/arch/ppc32/arch.py
index c10a046e..13c69c73 100644
--- a/test/arch/ppc32/arch.py
+++ b/test/arch/ppc32/arch.py
@@ -42,6 +42,7 @@ reg_tests = [
     ('b', "XXXXXXXX    LBZU       R0, 0x1(R31)", "8c1f0001"),
     ('b', "XXXXXXXX    LBZUX      R0, R31, R3", "7c1f18ee"),
     ('b', "XXXXXXXX    LBZX       R0, R30, R31", "7c1ef8ae"),
+    ('b', "XXXXXXXX    LFS        FPR6, 0x1(R1)", "c0c10001"),
     ('b', "XXXXXXXX    LHA        R9, 0x8(R31)", "a93f0008"),
     ('b', "XXXXXXXX    LHAU       R0, 0xFFFFFFFE(R9)", "ac09fffe"),
     ('b', "XXXXXXXX    LHAX       R0, R11, R9", "7c0b4aae"),
@@ -49,10 +50,16 @@ reg_tests = [
     ('b', "XXXXXXXX    LHZX       R0, R9, R10", "7c09522e"),
     ('b', "XXXXXXXX    LMW        R14, 0x8(R1)", "b9c10008"),
     ('b', "XXXXXXXX    LSWI       R5, R4, 0xC", "7ca464aa"),
+    ('b', "XXXXXXXX    LVEWX      VR0, R1, R2", "7c01108e"),
+    ('b', "XXXXXXXX    LVSL       VR0, R1, R2", "7c01100c"),
+    ('b', "XXXXXXXX    LVSR       VR0, R1, R2", "7c01104c"),
     ('b', "XXXXXXXX    LWZ        R0, 0x24(R1)", "80010024"),
     ('b', "XXXXXXXX    LWZU       R0, 0x4(R7)", "84070004"),
     ('b', "XXXXXXXX    LWZX       R29, R25, R0", "7fb9002e"),
     ('b', "XXXXXXXX    MCRF       CR1, CR2", "4c880000"),
+    ('b', "XXXXXXXX    MFFS       FPR23", "fee0048e"),
+    ('b', "XXXXXXXX    MTFSF      0x88, FPR6", "fd10358e"),
+    ('b', "XXXXXXXX    MTVSCR     VR0", "10000644"),
     ('b', "XXXXXXXX    MULLI      R0, R2, 0xFFFFFFE7", "1c02ffe7"),
     ('b', "XXXXXXXX    MULLI      R3, R30, 0xC", "1c7e000c"),
     ('b', "XXXXXXXX    NAND       R0, R0, R0", "7c0003b8"),
@@ -72,6 +79,7 @@ reg_tests = [
     ('b', "XXXXXXXX    SRW        R0, R23, R10", "7ee05430"),
     ('b', "XXXXXXXX    STB        R0, 0x1020(R30)", "981e1020"),
     ('b', "XXXXXXXX    STBU       R0, 0x1(R11)", "9c0b0001"),
+    ('b', "XXXXXXXX    STFS       FPR6, 0x1(R1)", "d0c10001"),
     ('b', "XXXXXXXX    STH        R6, (R3)", "b0c30000"),
     ('b', "XXXXXXXX    STMW       R14, 0x8(R1)", "bdc10008"),
     ('b', "XXXXXXXX    STW        R0, 0x24(R1)", "90010024"),
diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py
index 5109d2b4..10980b05 100755
--- a/test/arch/x86/sem.py
+++ b/test/arch/x86/sem.py
@@ -104,7 +104,7 @@ class TestX86Semantic(unittest.TestCase):
         sem = compute(ir_32, m32, '%s XMM0, XMM1' % name,
                                   {XMM0: arg1, XMM1: arg2},
                                   False)
-        ref = ExprInt(int_vec_op(op, elt_size, reg_size, arg1.arg, arg2.arg), XMM0.size)
+        ref = ExprInt(int_vec_op(op, elt_size, reg_size, int(arg1), int(arg2)), XMM0.size)
         self.assertEqual(sem, {XMM0: ref, XMM1: arg2})
 
     def symb_sse_ops(self, names, a, b, ref):
@@ -121,7 +121,7 @@ class TestX86Semantic(unittest.TestCase):
         sem = compute(ir_32, m32, '%s MM0, MM1' % name,
                                   {mm0: arg1, mm1: arg2},
                                   False)
-        ref = ExprInt(op(arg1.arg, arg2.arg), mm0.size)
+        ref = ExprInt(op(int(arg1), int(arg2)), mm0.size)
         self.assertEqual(sem, {mm0: ref, mm1: arg2})
 
     def sse_logical_op(self, name, op, arg1, arg2):
@@ -130,7 +130,7 @@ class TestX86Semantic(unittest.TestCase):
         sem = compute(ir_32, m32, '%s XMM0, XMM1' % name,
                                   {XMM0: arg1, XMM1: arg2},
                                   False)
-        ref = ExprInt(op(arg1.arg, arg2.arg), XMM0.size)
+        ref = ExprInt(op(int(arg1), int(arg2)), XMM0.size)
         self.assertEqual(sem, {XMM0: ref, XMM1: arg2})
 
     def test_SSE_ADD(self):
diff --git a/test/core/graph.py b/test/core/graph.py
index 3db5e523..ff27b780 100644
--- a/test/core/graph.py
+++ b/test/core/graph.py
@@ -286,3 +286,25 @@ assert sols[0] == {j1: 1,
                    j2: 2,
                    j3: 3}
 
+
+
+# Test replace_node
+graph = DiGraph()
+graph.add_edge(1, 2)
+graph.add_edge(2, 2)
+graph.add_edge(2, 3)
+
+graph.replace_node(2, 4)
+assert graph.nodes() == set([1, 3, 4])
+assert sorted(graph.edges()) == [(1, 4), (4, 3), (4, 4)]
+
+
+
+# Test compute_weakly_connected_components
+graph = DiGraph()
+graph.add_edge(1, 2)
+graph.add_edge(2, 2)
+graph.add_edge(3, 4)
+
+components = graph.compute_weakly_connected_components()
+assert sorted(components) == [set([1, 2]), set([3, 4])]
diff --git a/test/expression/expression.py b/test/expression/expression.py
index 3597eae8..9b0c2807 100644
--- a/test/expression/expression.py
+++ b/test/expression/expression.py
@@ -17,6 +17,7 @@ assert big_cst.size == 0x1000
 # Possible values
 #- Common constants
 A = ExprId("A", 32)
+B = ExprId("B", 32)
 cond1 = ExprId("cond1", 1)
 cond2 = ExprId("cond2", 16)
 cst1 = ExprInt(1, 32)
@@ -71,3 +72,47 @@ for expr in [
 aff = ExprAssign(A[0:32], cst1)
 
 assert aff.dst == A and aff.src == cst1
+
+
+mem = ExprMem(A, 32)
+assert mem.get_r() == set([mem])
+assert mem.get_r(mem_read=True) == set([mem, A])
+
+C = A+B
+D = C + A
+
+assert A in A
+assert A in C
+assert B in C
+assert C in C
+
+assert A in D
+assert B in D
+assert C in D
+assert D in D
+
+assert C not in A
+assert C not in B
+
+assert D not in A
+assert D not in B
+assert D not in C
+
+
+assert cst1.get_r(cst_read=True) == set([cst1])
+mem1 = ExprMem(A, 32)
+mem2 = ExprMem(mem1 + B, 32)
+assert mem2.get_r() == set([mem2])
+
+assign1 = ExprAssign(A, cst1)
+assert assign1.get_r() == set([])
+
+assign2 = ExprAssign(mem1, D)
+assert assign2.get_r() == set([A, B])
+assert assign2.get_r(mem_read=True) == set([A, B])
+assert assign2.get_w() == set([mem1])
+
+assign3 = ExprAssign(mem1, mem2)
+assert assign3.get_r() == set([mem2])
+assert assign3.get_r(mem_read=True) == set([mem1, mem2, A, B])
+assert assign3.get_w() == set([mem1])
diff --git a/test/expression/simplifications.py b/test/expression/simplifications.py
index f36a7b4d..1f243425 100644
--- a/test/expression/simplifications.py
+++ b/test/expression/simplifications.py
@@ -457,6 +457,7 @@ to_test = [(ExprInt(1, 32) - ExprInt(1, 32), ExprInt(0, 32)),
     (ExprOp("signExt_16", ExprInt(-0x8, 8)), ExprInt(-0x8, 16)),
 
     (ExprCond(a8.zeroExtend(32), a, b), ExprCond(a8, a, b)),
+    (ExprCond(a8, bi1, bi0).zeroExtend(32), ExprCond(a8, i1, i0)),
 
 
     (- (i2*a), a * im2),
diff --git a/test/ir/translators/smt2.py b/test/ir/translators/smt2.py
index 81f63b45..bf418f44 100644
--- a/test/ir/translators/smt2.py
+++ b/test/ir/translators/smt2.py
@@ -43,8 +43,8 @@ e_z3 = t_z3.from_expr(e)
 smt2 = t_smt2.to_smt2([t_smt2.from_expr(e)])
 
 # parse smt2 string with z3
-smt2_z3 = parse_smt2_string(smt2)
-
+result = parse_smt2_string(smt2)
+smt2_z3 = result[0]
 # initialise SMT solver
 s = Solver()
 
diff --git a/test/ir/translators/z3_ir.py b/test/ir/translators/z3_ir.py
index b28269fb..b96e43bb 100644
--- a/test/ir/translators/z3_ir.py
+++ b/test/ir/translators/z3_ir.py
@@ -24,13 +24,12 @@ def check_interp(interp, constraints, bits=32, valbits=8):
     constraints = dict((addr,
                         z3.BitVecVal(val, valbits))
                        for addr, val in constraints)
-    l = interp.as_list()
-    for entry in l:
-        if not isinstance(entry, list) or len(entry) < 2:
-            continue
-        addr, value = entry[0], entry[1]
-        if addr.as_long() in constraints:
-            assert equiv(value, constraints[addr.as_long()])
+    entry = interp.children()
+    assert len(entry) == 3
+    _, addr, value = entry
+    addr = addr.as_long()
+    assert addr in constraints
+    assert equiv(value, constraints[addr])
 
 # equiv short test
 # --------------------------------------------------------------------------
@@ -100,7 +99,7 @@ solver.add(ez3 == 10)
 solver.check()
 model = solver.model()
 check_interp(model[mem.get_mem_array(32)],
-             [(0xdeadbeef, 2), (0xdeadbeef + 3, 0)])
+             [(0xdeadbeef, 2)])
 
 # --------------------------------------------------------------------------
 ez3 = translator2.from_expr(e4)
@@ -116,7 +115,7 @@ solver.add(ez3 == 10)
 solver.check()
 model = solver.model()
 check_interp(model[memb.get_mem_array(32)],
-             [(0xdeadbeef, 0), (0xdeadbeef + 3, 2)])
+             [(0xdeadbeef+3, 2)])
 
 # --------------------------------------------------------------------------
 e5 = ExprSlice(ExprCompose(e, four), 0, 32) * five
diff --git a/test/test_all.py b/test/test_all.py
index 7fb43525..71eccc6f 100755
--- a/test/test_all.py
+++ b/test/test_all.py
@@ -17,6 +17,7 @@ from utils import cosmetics, multithread
 from multiprocessing import Queue
 
 is_win = platform.system() == "Windows"
+is_64bit = platform.architecture()[0] == "64bit"
 
 testset = TestSet("../")
 TAGS = {"regression": "REGRESSION", # Regression tests
@@ -112,7 +113,7 @@ for script in ["x86/sem.py",
         if jitter in blacklist.get(script, []):
             continue
         tags = [TAGS[jitter]] if jitter in TAGS else []
-        if is_win and script.endswith("mn_div.py"):
+        if (not is_64bit) and script.endswith("mn_div.py"):
             continue
         testset += ArchUnitTest(script, jitter, base_dir="arch", tags=tags)
 
@@ -548,6 +549,13 @@ test_x86_32_if_reg = ExampleShellcode(['x86_32', 'x86_32_if_reg.S', "x86_32_if_r
 test_x86_32_seh = ExampleShellcode(["x86_32", "x86_32_seh.S", "x86_32_seh.bin",
                                     "--PE"])
 test_x86_32_dead = ExampleShellcode(['x86_32', 'x86_32_dead.S', "x86_32_dead.bin"])
+test_x86_32_automod_2 = ExampleShellcode(
+    [
+        'x86_32', 'x86_32_automod_2.S', "x86_32_automod_2.bin", "--PE"
+    ]
+)
+
+
 test_x86_32_dis = ExampleShellcode(
     [
         "x86_32", "test_x86_32_dis.S", "test_x86_32_dis.bin", "--PE"
@@ -573,6 +581,7 @@ testset += test_x86_32_seh
 testset += test_x86_32_dead
 testset += test_human
 testset += test_x86_32_dis
+testset += test_x86_32_automod_2
 
 class ExampleDisassembler(Example):
     """Disassembler examples specificities:
@@ -801,6 +810,8 @@ for script, dep in [(["x86_32.py", Example.get_sample("x86_32_sc.bin")], []),
                     (["arm_sc.py", "0", Example.get_sample("demo_arm_l.bin"),
                       "l", "-a", "0"], [test_arml]),
                     (["sandbox_call.py", Example.get_sample("md5_arm")], []),
+                    (["sandbox_pe_x86_32.py", Example.get_sample("x86_32_automod_2.bin")],
+                          [test_x86_32_automod_2])
                     ] + [(["sandbox_pe_x86_32.py",
                            Example.get_sample("x86_32_" + name + ".bin")],
                           [test_box[name]])
diff --git a/test/utils/testset.py b/test/utils/testset.py
index eee0e6f7..2bdb7450 100644
--- a/test/utils/testset.py
+++ b/test/utils/testset.py
@@ -203,7 +203,7 @@ class TestSet(object):
             try:
                 os.remove(product)
             except OSError:
-                print("Cleanning error: Unable to remove %s" % product)
+                print("Cleaning error: Unable to remove %s" % product)
 
     def add_additional_args(self, args):
         """Add arguments to used on the test command line