diff options
Diffstat (limited to 'test')
43 files changed, 4701 insertions, 0 deletions
diff --git a/test/arch/mep/asm/launch.py b/test/arch/mep/asm/launch.py new file mode 100644 index 00000000..ed8d9f27 --- /dev/null +++ b/test/arch/mep/asm/launch.py @@ -0,0 +1,22 @@ +# Toshiba MeP-c4 - pytest unit tests wrapper +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import launch_tests + +from test_major_opcode_0 import TestMajor0; launch_tests(TestMajor0()) +from test_major_opcode_1 import TestMajor1; launch_tests(TestMajor1()) +from test_major_opcode_2 import TestMajor2; launch_tests(TestMajor2()) +from test_major_opcode_3 import TestMajor3; launch_tests(TestMajor3()) +from test_major_opcode_4 import TestMajor4; launch_tests(TestMajor4()) +from test_major_opcode_5 import TestMajor5; launch_tests(TestMajor5()) +from test_major_opcode_6 import TestMajor6; launch_tests(TestMajor6()) +from test_major_opcode_7 import TestMajor7; launch_tests(TestMajor7()) +from test_major_opcode_8 import TestMajor8; launch_tests(TestMajor8()) +from test_major_opcode_9 import TestMajor9; launch_tests(TestMajor9()) +from test_major_opcode_10 import TestMajor10; launch_tests(TestMajor10()) +from test_major_opcode_11 import TestMajor11; launch_tests(TestMajor11()) +from test_major_opcode_12 import TestMajor12; launch_tests(TestMajor12()) +from test_major_opcode_13 import TestMajor13; launch_tests(TestMajor13()) +from test_major_opcode_14 import TestMajor14; launch_tests(TestMajor14()) +from test_major_opcode_15 import TestMajor15; launch_tests(TestMajor15()) +from test_asm import TestMisc; launch_tests(TestMisc()) diff --git a/test/arch/mep/asm/test_asm.py b/test/arch/mep/asm/test_asm.py new file mode 100644 index 00000000..ddf91ed6 --- /dev/null +++ b/test/arch/mep/asm/test_asm.py @@ -0,0 +1,38 @@ +# Toshiba MeP-c4 - Misc unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from miasm2.arch.mep.arch import mn_mep + +class TestMisc: + + def test(self): + + # Disassemble & assemble unit tests + unit_tests = [("ADD R1, 2", "6108")] + unit_tests += [("JMP 0xC3FA38", "d9c8c3fa")] + unit_tests += [("SLT3 R0, R8, R10", "08a2")] + unit_tests += [("SB R9, (R4)", "0948")] + unit_tests += [("SSARB 3(GP)", "13ec")] + unit_tests += [("SWCPI C13, (R2+)", "3d20")] + unit_tests += [("ADD3 R2, SP, 0x1C", "421c")] + unit_tests += [("SW R7, 0x50(SP)", "4752")] + + for mn_str, mn_hex in unit_tests: + print "-" * 49 # Tests separation + + # Dissassemble + mn_bin = mn_hex.decode("hex") + mn = mn_mep.dis(mn_bin, "b") + + print "dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20)) + assert(str(mn) == mn_str) # dissassemble assertion + + # Assemble and return all possible candidates + instr = mn_mep.fromstring(str(mn), "b") + instr.mode = "b" + asm_list = [i.encode("hex") for i in mn_mep.asm(instr)] + + # Print the results + print "asm: %s -> %s" % (mn_str.rjust(20), + ", ".join(asm_list).rjust(20)) + assert(mn_hex in asm_list) # assemble assertion diff --git a/test/arch/mep/asm/test_major_opcode_0.py b/test/arch/mep/asm/test_major_opcode_0.py new file mode 100644 index 00000000..d517850a --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_0.py @@ -0,0 +1,268 @@ +# Toshiba MeP-c4 - Major Opcode #0 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor0: + + def test_MOV(self): + """Test the MOV instruction""" + + # Top instructions + check_instruction("MOV $0, $4", "0040") + check_instruction("MOV $TP, $1", "0d10") + check_instruction("MOV $1, $7", "0170") + check_instruction("MOV $1, $8", "0180") + check_instruction("MOV $1, $TP", "01d0") + + # Randomly choosen instructions + check_instruction("MOV $3, $7", "0370") + check_instruction("MOV $0, $SP", "00f0") + check_instruction("MOV $5, $SP", "05f0") + check_instruction("MOV $2, $10", "02a0") + check_instruction("MOV $GP, $12", "0ec0") + + def test_NEG(self): + """Test the NEG instruction""" + + # Top instructions + check_instruction("NEG $0, $12", "00c1") + check_instruction("NEG $1, $0", "0101") + check_instruction("NEG $0, $1", "0011") + check_instruction("NEG $0, $0", "0001") + check_instruction("NEG $0, $8", "0081") + + # Randomly choosen instructions + check_instruction("NEG $6, $6", "0661") + check_instruction("NEG $9, $5", "0951") + check_instruction("NEG $11, $12", "0bc1") + check_instruction("NEG $2, $6", "0261") + check_instruction("NEG $4, $9", "0491") + + def test_SLT3(self): + """Test the SLT3 instruction""" + + # Top instructions + check_instruction("SLT3 $0, $1, $0", "0102") + check_instruction("SLT3 $0, $4, $12", "04c2") + check_instruction("SLT3 $0, $0, $12", "00c2") + check_instruction("SLT3 $0, $0, $0", "0002") + check_instruction("SLT3 $0, $0, $8", "0082") + + # Randomly choosen instructions + check_instruction("SLT3 $0, $2, $4", "0242") + check_instruction("SLT3 $0, $SP, $2", "0f22") + check_instruction("SLT3 $0, $5, $9", "0592") + check_instruction("SLT3 $0, $6, $4", "0642") + check_instruction("SLT3 $0, $12, $6", "0c62") + + def test_SLTU3(self): + """Test the SLTU3 instruction""" + + # Top instructions + check_instruction("SLTU3 $0, $6, $8", "0683") + check_instruction("SLTU3 $0, $0, $0", "0003") + check_instruction("SLTU3 $0, $10, $11", "0ab3") + check_instruction("SLTU3 $0, $12, $0", "0c03") + check_instruction("SLTU3 $0, $4, $3", "0433") + + # Randomly choosen instructions + check_instruction("SLTU3 $0, $5, $TP", "05d3") + check_instruction("SLTU3 $0, $2, $5", "0253") + check_instruction("SLTU3 $0, $SP, $TP", "0fd3") + check_instruction("SLTU3 $0, $11, $10", "0ba3") + check_instruction("SLTU3 $0, $4, $7", "0473") + + def test_SUB(self): + """Test the SUB instruction""" + + # Top instructions + check_instruction("SUB $0, $6", "0064") + check_instruction("SUB $0, $0", "0004") + check_instruction("SUB $12, $4", "0c44") + check_instruction("SUB $4, $3", "0434") + check_instruction("SUB $0, $8", "0084") + + # Randomly choosen instructions + check_instruction("SUB $11, $9", "0b94") + check_instruction("SUB $9, $9", "0994") + check_instruction("SUB $TP, $2", "0d24") + check_instruction("SUB $1, $9", "0194") + check_instruction("SUB $SP, $11", "0fb4") + + def test_SBVCK3(self): + """Test the SBVCK3 instruction""" + + # Top instructions + check_instruction("SBVCK3 $0, $0, $4", "0045") + check_instruction("SBVCK3 $0, $5, $0", "0505") + check_instruction("SBVCK3 $0, $0, $0", "0005") + check_instruction("SBVCK3 $0, $0, $6", "0065") + check_instruction("SBVCK3 $0, $0, $12", "00c5") + + # Randomly choosen instructions + check_instruction("SBVCK3 $0, $0, $5", "0055") + check_instruction("SBVCK3 $0, $4, $8", "0485") + check_instruction("SBVCK3 $0, $4, $1", "0415") + check_instruction("SBVCK3 $0, $TP, $4", "0d45") + check_instruction("SBVCK3 $0, $1, $7", "0175") + + def test_RI(self): + """Test the (RI) instruction""" + + # No samples were found + assert(True) + + def test_ADVCK3(self): + """Test the ADVCK3 instruction""" + + # Top instructions + check_instruction("ADVCK3 $0, $0, $6", "0067") + check_instruction("ADVCK3 $0, $0, $4", "0047") + check_instruction("ADVCK3 $0, $8, $9", "0897") + check_instruction("ADVCK3 $0, $0, $0", "0007") + check_instruction("ADVCK3 $0, $0, $12", "00c7") + + # Randomly choosen instructions + check_instruction("ADVCK3 $0, $3, $9", "0397") + check_instruction("ADVCK3 $0, $10, $7", "0a77") + check_instruction("ADVCK3 $0, $1, $5", "0157") + check_instruction("ADVCK3 $0, $0, $9", "0097") + check_instruction("ADVCK3 $0, $0, $2", "0027") + + def test_SB(self): + """Test the SB instruction""" + + # Top instructions + check_instruction("SB $10, ($12)", "0ac8") + check_instruction("SB $8, ($0)", "0808") + check_instruction("SB $12, ($10)", "0ca8") + check_instruction("SB $12, ($4)", "0c48") + check_instruction("SB $12, ($11)", "0cb8") + + # Randomly choosen instructions + check_instruction("SB $4, ($4)", "0448") + check_instruction("SB $10, ($8)", "0a88") + check_instruction("SB $7, ($6)", "0768") + check_instruction("SB $8, ($11)", "08b8") + check_instruction("SB $2, ($GP)", "02e8") + + def test_SH(self): + """Test the SH instruction""" + + # Top instructions + check_instruction("SH $12, ($11)", "0cb9") + check_instruction("SH $12, ($0)", "0c09") + check_instruction("SH $12, ($4)", "0c49") + check_instruction("SH $0, ($2)", "0029") + check_instruction("SH $0, ($12)", "00c9") + + # Randomly choosen instructions + check_instruction("SH $GP, ($12)", "0ec9") + check_instruction("SH $6, ($10)", "06a9") + check_instruction("SH $10, ($11)", "0ab9") + check_instruction("SH $9, ($4)", "0949") + check_instruction("SH $1, ($5)", "0159") + + def test_SW(self): + """Test the SW instruction""" + + # Top instructions + check_instruction("SW $10, ($12)", "0aca") + check_instruction("SW $0, ($12)", "00ca") + check_instruction("SW $0, ($0)", "000a") + check_instruction("SW $12, ($SP)", "0cfa") + check_instruction("SW $0, ($SP)", "00fa") + + # Randomly choosen instructions + check_instruction("SW $0, ($7)", "007a") + check_instruction("SW $4, ($12)", "04ca") + check_instruction("SW $12, ($7)", "0c7a") + check_instruction("SW $9, ($12)", "09ca") + check_instruction("SW $TP, ($1)", "0d1a") + + def test_LBU(self): + """Test the LBU instruction""" + + # Top instructions + check_instruction("LBU $12, ($TP)", "0cdb") + check_instruction("LBU $12, ($10)", "0cab") + check_instruction("LBU $12, ($11)", "0cbb") + check_instruction("LBU $12, ($4)", "0c4b") + check_instruction("LBU $0, ($4)", "004b") + + # Randomly choosen instructions + check_instruction("LBU $6, ($TP)", "06db") + check_instruction("LBU $11, ($SP)", "0bfb") + check_instruction("LBU $10, ($10)", "0aab") + check_instruction("LBU $1, ($9)", "019b") + check_instruction("LBU $12, ($1)", "0c1b") + + def test_LB(self): + """Test the LB instruction""" + + # Top instructions + check_instruction("LB $11, ($TP)", "0bdc") + check_instruction("LB $11, ($12)", "0bcc") + check_instruction("LB $11, ($4)", "0b4c") + check_instruction("LB $10, ($4)", "0a4c") + check_instruction("LB $12, ($TP)", "0cdc") + + # Randomly choosen instructions + check_instruction("LB $0, ($12)", "00cc") + check_instruction("LB $2, ($7)", "027c") + check_instruction("LB $5, ($7)", "057c") + check_instruction("LB $10, ($1)", "0a1c") + check_instruction("LB $12, ($12)", "0ccc") + + def test_LH(self): + """Test the LH instruction""" + + # Top instructions + check_instruction("LH $0, ($4)", "004d") + check_instruction("LH $0, ($0)", "000d") + check_instruction("LH $12, ($4)", "0c4d") + check_instruction("LH $0, ($12)", "00cd") + check_instruction("LH $10, ($0)", "0a0d") + + # Randomly choosen instructions + check_instruction("LH $0, ($GP)", "00ed") + check_instruction("LH $12, ($5)", "0c5d") + check_instruction("LH $0, ($3)", "003d") + check_instruction("LH $10, ($SP)", "0afd") + check_instruction("LH $3, ($6)", "036d") + + def test_LW(self): + """Test the LW instruction""" + + # Top instructions + check_instruction("LW $0, ($SP)", "00fe") + check_instruction("LW $12, ($4)", "0c4e") + check_instruction("LW $12, ($SP)", "0cfe") + check_instruction("LW $0, ($12)", "00ce") + check_instruction("LW $1, ($SP)", "01fe") + + # Randomly choosen instructions + check_instruction("LW $1, ($0)", "010e") + check_instruction("LW $7, ($12)", "07ce") + check_instruction("LW $TP, ($2)", "0d2e") + check_instruction("LW $5, ($2)", "052e") + check_instruction("LW $10, ($2)", "0a2e") + + def test_LHU(self): + """Test the LHU instruction""" + + # Top instructions + check_instruction("LHU $12, ($1)", "0c1f") + check_instruction("LHU $11, ($4)", "0b4f") + check_instruction("LHU $11, ($3)", "0b3f") + check_instruction("LHU $12, ($8)", "0c8f") + check_instruction("LHU $12, ($4)", "0c4f") + + # Randomly choosen instructions + check_instruction("LHU $5, ($11)", "05bf") + check_instruction("LHU $12, ($3)", "0c3f") + check_instruction("LHU $9, ($8)", "098f") + check_instruction("LHU $10, ($3)", "0a3f") + check_instruction("LHU $5, ($8)", "058f") diff --git a/test/arch/mep/asm/test_major_opcode_1.py b/test/arch/mep/asm/test_major_opcode_1.py new file mode 100644 index 00000000..acdb9ca2 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_1.py @@ -0,0 +1,294 @@ +# Toshiba MeP-c4 - Major Opcode #1 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor1: + + def test_OR(self): + """Test the OR instruction""" + + # Top instructions + check_instruction("OR $0, $4", "1040") + check_instruction("OR $12, $10", "1ca0") + check_instruction("OR $11, $12", "1bc0") + check_instruction("OR $0, $11", "10b0") + check_instruction("OR $0, $12", "10c0") + + # Randomly choosen instructions + check_instruction("OR $1, $12", "11c0") + check_instruction("OR $6, $11", "16b0") + check_instruction("OR $10, $9", "1a90") + check_instruction("OR $2, $10", "12a0") + check_instruction("OR $11, $4", "1b40") + + def test_AND(self): + """Test the AND instruction""" + + # Top instructions + check_instruction("AND $11, $12", "1bc1") + check_instruction("AND $12, $10", "1ca1") + check_instruction("AND $4, $12", "14c1") + check_instruction("AND $12, $11", "1cb1") + check_instruction("AND $0, $0", "1001") + + # Randomly choosen instructions + check_instruction("AND $6, $12", "16c1") + check_instruction("AND $8, $6", "1861") + check_instruction("AND $1, $12", "11c1") + check_instruction("AND $11, $2", "1b21") + check_instruction("AND $2, $4", "1241") + + def test_XOR(self): + """Test the XOR instruction""" + + # Top instructions + check_instruction("XOR $0, $2", "1022") + check_instruction("XOR $6, $10", "16a2") + check_instruction("XOR $2, $2", "1222") + check_instruction("XOR $4, $0", "1402") + check_instruction("XOR $11, $12", "1bc2") + + # Randomly choosen instructions + check_instruction("XOR $0, $12", "10c2") + check_instruction("XOR $12, $1", "1c12") + check_instruction("XOR $SP, $10", "1fa2") + check_instruction("XOR $3, $11", "13b2") + check_instruction("XOR $1, $8", "1182") + + def test_NOR(self): + """Test the NOR instruction""" + + # Top instructions + check_instruction("NOR $9, $2", "1923") + check_instruction("NOR $12, $12", "1cc3") + check_instruction("NOR $4, $4", "1443") + check_instruction("NOR $11, $0", "1b03") + check_instruction("NOR $0, $0", "1003") + + # Randomly choosen instructions + check_instruction("NOR $4, $1", "1413") + check_instruction("NOR $11, $11", "1bb3") + check_instruction("NOR $9, $9", "1993") + check_instruction("NOR $11, $2", "1b23") + check_instruction("NOR $0, $5", "1053") + + def test_MUL(self): + """Test the MUL instruction""" + + # Top instructions + check_instruction("MUL $9, $SP", "19f4") + check_instruction("MUL $0, $8", "1084") + check_instruction("MUL $8, $12", "18c4") + check_instruction("MUL $10, $9", "1a94") + check_instruction("MUL $10, $3", "1a34") + + # Randomly choosen instructions + check_instruction("MUL $2, $2", "1224") + check_instruction("MUL $4, $12", "14c4") + check_instruction("MUL $9, $3", "1934") + check_instruction("MUL $4, $11", "14b4") + check_instruction("MUL $6, $0", "1604") + + def test_MULU(self): + """Test the MULU instruction""" + + # Top instructions + check_instruction("MULU $4, $2", "1425") + check_instruction("MULU $8, $9", "1895") + check_instruction("MULU $7, $12", "17c5") + check_instruction("MULU $5, $12", "15c5") + check_instruction("MULU $1, $8", "1185") + + # Randomly choosen instructions + check_instruction("MULU $9, $6", "1965") + check_instruction("MULU $5, $1", "1515") + check_instruction("MULU $5, $11", "15b5") + check_instruction("MULU $1, $10", "11a5") + check_instruction("MULU $0, $4", "1045") + + def test_MULR(self): + """Test the MULR instruction""" + + # Top instructions + check_instruction("MULR $SP, $0", "1f06") + check_instruction("MULR $8, $3", "1836") + check_instruction("MULR $SP, $6", "1f66") + check_instruction("MULR $12, $1", "1c16") + check_instruction("MULR $6, $1", "1616") + + # Randomly choosen instructions + check_instruction("MULR $7, $1", "1716") + check_instruction("MULR $10, $8", "1a86") + check_instruction("MULR $4, $1", "1416") + check_instruction("MULR $12, $11", "1cb6") + check_instruction("MULR $12, $4", "1c46") + + def test_MULRU(self): + """Test the MULRU instruction""" + + # Top instructions + check_instruction("MULRU $12, $2", "1c27") + check_instruction("MULRU $0, $4", "1047") + check_instruction("MULRU $2, $1", "1217") + check_instruction("MULRU $7, $1", "1717") + check_instruction("MULRU $GP, $6", "1e67") + + # Randomly choosen instructions + check_instruction("MULRU $3, $12", "13c7") + check_instruction("MULRU $2, $TP", "12d7") + check_instruction("MULRU $3, $TP", "13d7") + check_instruction("MULRU $2, $12", "12c7") + check_instruction("MULRU $TP, $2", "1d27") + + def test_DIV(self): + """Test the DIV instruction""" + + # Top instructions + check_instruction("DIV $1, $12", "11c8") + check_instruction("DIV $8, $1", "1818") + check_instruction("DIV $GP, $0", "1e08") + check_instruction("DIV $9, $12", "19c8") + check_instruction("DIV $12, $11", "1cb8") + + # Randomly choosen instructions + check_instruction("DIV $6, $1", "1618") + check_instruction("DIV $5, $11", "15b8") + check_instruction("DIV $1, $9", "1198") + check_instruction("DIV $GP, $GP", "1ee8") + check_instruction("DIV $0, $1", "1018") + + def test_DIVU(self): + """Test the DIVU instruction""" + + # Top instructions + check_instruction("DIVU $1, $TP", "11d9") + check_instruction("DIVU $4, $12", "14c9") + check_instruction("DIVU $9, $1", "1919") + check_instruction("DIVU $0, $10", "10a9") + check_instruction("DIVU $11, $10", "1ba9") + + # Randomly choosen instructions + check_instruction("DIVU $3, $9", "1399") + check_instruction("DIVU $SP, $4", "1f49") + check_instruction("DIVU $12, $5", "1c59") + check_instruction("DIVU $8, $4", "1849") + check_instruction("DIVU $8, $11", "18b9") + + def test_RI(self): + """Test the (RI) instruction""" + + # No samples were found + assert(True) + + def test_SSARB(self): + """Test the SSARB instruction""" + + # Top instructions + check_instruction("SSARB 0($8)", "108c") + check_instruction("SSARB 3($GP)", "13ec") + check_instruction("SSARB 0($3)", "103c") + check_instruction("SSARB 0($TP)", "10dc") + check_instruction("SSARB 3($0)", "130c") + + def test_EXTB(self): + """Test the EXTB instruction""" + + # Top instructions + check_instruction("EXTB $8", "180d") + check_instruction("EXTB $0", "100d") + check_instruction("EXTB $4", "140d") + check_instruction("EXTB $11", "1b0d") + check_instruction("EXTB $12", "1c0d") + + # Randomly choosen instructions + check_instruction("EXTB $6", "160d") + check_instruction("EXTB $10", "1a0d") + check_instruction("EXTB $9", "190d") + check_instruction("EXTB $7", "170d") + check_instruction("EXTB $3", "130d") + + def test_EXTH(self): + """Test the EXTH instruction""" + + # Top instructions + check_instruction("EXTH $0", "102d") + check_instruction("EXTH $11", "1b2d") + check_instruction("EXTH $2", "122d") + check_instruction("EXTH $6", "162d") + check_instruction("EXTH $12", "1c2d") + + def test_EXTUB(self): + """Test the EXTUB instruction""" + + # Top instructions + check_instruction("EXTUB $2", "128d") + check_instruction("EXTUB $11", "1b8d") + check_instruction("EXTUB $12", "1c8d") + check_instruction("EXTUB $0", "108d") + check_instruction("EXTUB $4", "148d") + + # Randomly choosen instructions + check_instruction("EXTUB $7", "178d") + check_instruction("EXTUB $1", "118d") + check_instruction("EXTUB $6", "168d") + check_instruction("EXTUB $9", "198d") + check_instruction("EXTUB $10", "1a8d") + + def test_EXTUH(self): + """Test the EXTUH instruction""" + + # Top instructions + check_instruction("EXTUH $4", "14ad") + check_instruction("EXTUH $1", "11ad") + check_instruction("EXTUH $12", "1cad") + check_instruction("EXTUH $3", "13ad") + check_instruction("EXTUH $0", "10ad") + + # Randomly choosen instructions + check_instruction("EXTUH $7", "17ad") + check_instruction("EXTUH $5", "15ad") + check_instruction("EXTUH $2", "12ad") + check_instruction("EXTUH $GP", "1ead") + check_instruction("EXTUH $8", "18ad") + + def test_JMP(self): + """Test the JMP instruction""" + + # Top instructions + check_instruction("JMP $11", "10be") + check_instruction("JMP $2", "102e") + check_instruction("JMP $4", "104e") + check_instruction("JMP $12", "10ce") + check_instruction("JMP $1", "101e") + + # Randomly choosen instructions + check_instruction("JMP $7", "107e") + check_instruction("JMP $8", "108e") + check_instruction("JMP $10", "10ae") + check_instruction("JMP $9", "109e") + check_instruction("JMP $3", "103e") + + def test_JSR(self): + """Test the JSR instruction""" + + # Top instructions + check_instruction("JSR $11", "10bf") + check_instruction("JSR $0", "100f") + check_instruction("JSR $3", "103f") + check_instruction("JSR $12", "10cf") + check_instruction("JSR $4", "104f") + + # Randomly choosen instructions + check_instruction("JSR $9", "109f") + check_instruction("JSR $10", "10af") + check_instruction("JSR $6", "106f") + check_instruction("JSR $5", "105f") + check_instruction("JSR $7", "107f") + + def test_JSRV(self): + """Test the JSRV instruction""" + + # Top instructions + check_instruction("JSRV $GP", "18ef") diff --git a/test/arch/mep/asm/test_major_opcode_10.py b/test/arch/mep/asm/test_major_opcode_10.py new file mode 100644 index 00000000..6c8d0cf4 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_10.py @@ -0,0 +1,41 @@ +# Toshiba MeP-c4 - Major Opcode #10 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor10: + + def test_BEQZ(self): + """Test the BEQZ instruction""" + + # Top instructions + check_instruction("BEQZ $11, 0xFFFFFF8C", "ab8c") + check_instruction("BEQZ $4, 0x6", "a406") + check_instruction("BEQZ $TP, 0x4", "ad04") + check_instruction("BEQZ $11, 0x4", "ab04") + check_instruction("BEQZ $12, 0xA", "ac0a") + + # Randomly choosen instructions + check_instruction("BEQZ $0, 0x42", "a042") + check_instruction("BEQZ $10, 0x6", "aa06") + check_instruction("BEQZ $0, 0x8", "a008") + check_instruction("BEQZ $12, 0x4", "ac04") + check_instruction("BEQZ $1, 0x70", "a170") + + def test_BNEZ(self): + """Test the BNEZ instruction""" + + # Top instructions + check_instruction("BNEZ $7, 0x46", "a747") + check_instruction("BNEZ $0, 0x40", "a041") + check_instruction("BNEZ $9, 0x1C", "a91d") + check_instruction("BNEZ $0, 0xFFFFFFF6", "a0f7") + check_instruction("BNEZ $4, 0xA", "a40b") + + # Randomly choosen instructions + check_instruction("BNEZ $7, 0xE", "a70f") + check_instruction("BNEZ $11, 0xE", "ab0f") + check_instruction("BNEZ $10, 0x28", "aa29") + check_instruction("BNEZ $9, 0xFFFFFFAE", "a9af") + check_instruction("BNEZ $9, 0xE", "a90f") diff --git a/test/arch/mep/asm/test_major_opcode_11.py b/test/arch/mep/asm/test_major_opcode_11.py new file mode 100644 index 00000000..7876a968 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_11.py @@ -0,0 +1,44 @@ +# Toshiba MeP-c4 - Major Opcode #11 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor11: + + def test_BRA(self): + """Test the BRA instruction""" + + # Top instructions + check_instruction("BRA 0xFFFFF9B4", "b9b4") + check_instruction("BRA 0x34", "b034") + check_instruction("BRA 0x16", "b016") + check_instruction("BRA 0x46", "b046") + check_instruction("BRA 0xFFFFFF98", "bf98") + + # Randomly choosen instructions + check_instruction("BRA 0x2AA", "b2aa") + check_instruction("BRA 0x22", "b022") + check_instruction("BRA 0x12", "b012") + check_instruction("BRA 0x7FE", "b7fe") + check_instruction("BRA 0x34", "b034") + + def test_BSR(self): + """Test the BSR instruction""" + + # Top instructions + check_instruction("BSR 0xFFFFFF22", "bf23", multi=2) + check_instruction("BSR 0x716", "b717", multi=2) + check_instruction("BSR 0xFFFFFE36", "be37", multi=2) + check_instruction("BSR 0xFFFFFBB2", "bbb3", multi=2) + check_instruction("BSR 0xFFFFFCCE", "bccf", multi=2) + + # Randomly choosen instructions + check_instruction("BSR 0xFFFFFED4", "bed5", multi=2) + check_instruction("BSR 0xFFFFFF62", "bf63", multi=2) + check_instruction("BSR 0xFFFFFF36", "bf37", multi=2) + check_instruction("BSR 0xFFFFFBD0", "bbd1", multi=2) + check_instruction("BSR 0x5AA", "b5ab", multi=2) + + # Manually crafted + check_instruction("BSR 0xC67BFA", "bfa3", offset=0xc67c58) diff --git a/test/arch/mep/asm/test_major_opcode_12.py b/test/arch/mep/asm/test_major_opcode_12.py new file mode 100644 index 00000000..c9a0be79 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_12.py @@ -0,0 +1,300 @@ +# Toshiba MeP-c4 - Major Opcode #12 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor12: + + def test_ADD3(self): + """Test the ADD3 instruction""" + + # Top instructions + check_instruction("ADD3 $SP, $SP, -64", "cff0ffc0") + check_instruction("ADD3 $SP, $SP, -44", "cff0ffd4") + check_instruction("ADD3 $SP, $SP, -36", "cff0ffdc") + check_instruction("ADD3 $12, $4, 0x48", "cc400048") + check_instruction("ADD3 $SP, $SP, -68", "cff0ffbc") + + # Randomly choosen instructions + check_instruction("ADD3 $12, $SP, 0x6", "ccf00006") + check_instruction("ADD3 $12, $12, 0x3E4", "ccc003e4") + check_instruction("ADD3 $7, $5, -31912", "c7508358") + check_instruction("ADD3 $1, $8, 0x54", "c1800054") + check_instruction("ADD3 $2, $8, 0x28", "c2800028") + + def test_MOV(self): + """Test the MOV instruction""" + + # Top instructions + check_instruction("MOV $11, 136", "cb010088", multi=2) + check_instruction("MOV $10, 170", "ca0100aa", multi=2) + check_instruction("MOV $2, 130", "c2010082", multi=2) + check_instruction("MOV $2, 139", "c201008b", multi=2) + check_instruction("MOV $0, 194", "c00100c2", multi=2) + + # Randomly choosen instructions + check_instruction("MOV $12, 239", "cc0100ef", multi=2) + check_instruction("MOV $1, 136", "c1010088", multi=2) + check_instruction("MOV $3, 168", "c30100a8", multi=2) + check_instruction("MOV $10, 133", "ca010085", multi=2) + check_instruction("MOV $11, 32640", "cb017f80", multi=2) + + def test_MOVU(self): + """Test the MOVU instruction""" + + # Top instructions + check_instruction("MOVU $2, 0x0", "c2110000", multi=2) + check_instruction("MOVU $2, 0x8002", "c2118002") + check_instruction("MOVU $10, 0x8106", "ca118106") + check_instruction("MOVU $11, 0x8105", "cb118105") + check_instruction("MOVU $11, 0x8106", "cb118106") + + # Randomly choosen instructions + check_instruction("MOVU $9, 0x8126", "c9118126") + check_instruction("MOVU $7, 0xFF00", "c711ff00") + check_instruction("MOVU $2, 0xE200", "c211e200") + check_instruction("MOVU $10, 0xE102", "ca11e102") + check_instruction("MOVU $11, 0xD6D8", "cb11d6d8") + + def test_MOVH(self): + """Test the MOVH instruction""" + + # Top instructions + check_instruction("MOVH $11, 0x8000", "cb218000") + check_instruction("MOVH $11, 0x1000", "cb211000") + check_instruction("MOVH $11, 0x100", "cb210100") + check_instruction("MOVH $1, 0x101", "c1210101") + check_instruction("MOVH $12, 0x81", "cc210081") + + # Randomly choosen instructions + check_instruction("MOVH $4, 0xF4D5", "c421f4d5") + check_instruction("MOVH $10, 0xFC00", "ca21fc00") + check_instruction("MOVH $12, 0xC003", "cc21c003") + check_instruction("MOVH $TP, 0x400", "cd210400") + check_instruction("MOVH $7, 0x8000", "c7218000") + + def test_SLT3(self): + """Test the SLT3 instruction""" + + # Top instructions + check_instruction("SLT3 $0, $2, 0x908", "c0220908") + check_instruction("SLT3 $0, $1, 0x90F", "c012090f") + check_instruction("SLT3 $0, $1, 0x1CE", "c01201ce") + check_instruction("SLT3 $0, $12, 0x801", "c0c20801") + check_instruction("SLT3 $0, $4, 0x800", "c0420800") + + # Randomly choosen instructions + check_instruction("SLT3 $2, $4, 0x6A18", "c2426a18") + check_instruction("SLT3 $2, $11, -31153", "c2b2864f") + check_instruction("SLT3 $11, $12, 0x5BFA", "cbc25bfa") + check_instruction("SLT3 $SP, $4, -30809", "cf4287a7") + check_instruction("SLT3 $0, $12, 0x21", "c0c20021") + + def test_SLTU3(self): + """Test the SLTU3 instruction""" + + # Top instructions + check_instruction("SLTU3 $11, $8, 0x8813", "cb838813") + check_instruction("SLTU3 $12, $11, 0x2711", "ccb32711") + check_instruction("SLTU3 $0, $11, 0x941", "c0b30941") + check_instruction("SLTU3 $0, $12, 0x941", "c0c30941") + check_instruction("SLTU3 $12, $8, 0x1001", "cc831001") + + # Randomly choosen instructions + check_instruction("SLTU3 $8, $12, 0x8BA9", "c8c38ba9") + check_instruction("SLTU3 $12, $11, 0x1E", "ccb3001e") + check_instruction("SLTU3 $6, $GP, 0x6C90", "c6e36c90") + check_instruction("SLTU3 $TP, $7, 0x86C3", "cd7386c3") + check_instruction("SLTU3 $12, $10, 0x1", "cca30001") + + def test_OR3(self): + """Test the OR3 instruction""" + + # Top instructions + check_instruction("OR3 $1, $1, 0x1", "c1140001") + check_instruction("OR3 $11, $11, 0x8", "cbb40008") + check_instruction("OR3 $4, $4, 0x20", "c4440020") + check_instruction("OR3 $12, $12, 0x1", "ccc40001") + check_instruction("OR3 $12, $12, 0x2", "ccc40002") + + # Randomly choosen instructions + check_instruction("OR3 $12, $GP, 0xC7", "cce400c7") + check_instruction("OR3 $10, $3, 0x40", "ca340040") + check_instruction("OR3 $3, $3, 0xFF97", "c334ff97") + check_instruction("OR3 $9, $TP, 0x7A0D", "c9d47a0d") + check_instruction("OR3 $1, $1, 0x1122", "c1141122") + + def test_AND3(self): + """Test the AND3 instruction""" + + # Top instructions + check_instruction("AND3 $10, $12, 0x1", "cac50001") + check_instruction("AND3 $11, $4, 0x8", "cb450008") + check_instruction("AND3 $12, $4, 0x1", "cc450001") + check_instruction("AND3 $11, $12, 0x8", "cbc50008") + check_instruction("AND3 $11, $12, 0x1", "cbc50001") + + # Randomly choosen instructions + check_instruction("AND3 $12, $7, 0x1FF", "cc7501ff") + check_instruction("AND3 $9, $10, 0x4E27", "c9a54e27") + check_instruction("AND3 $4, $4, 0xFB", "c44500fb") + check_instruction("AND3 $10, $7, 0x10", "ca750010") + check_instruction("AND3 $8, $9, 0xCE", "c89500ce") + + def test_XOR3(self): + """Test the XOR3 instruction""" + + # Top instructions + check_instruction("XOR3 $GP, $0, 0x9D72", "ce069d72") + check_instruction("XOR3 $10, $9, 0xDB3C", "ca96db3c") + check_instruction("XOR3 $7, $7, 0x6060", "c7766060") + check_instruction("XOR3 $12, $11, 0x4", "ccb60004") + check_instruction("XOR3 $4, $4, 0x1", "c4460001") + + # Randomly choosen instructions + check_instruction("XOR3 $TP, $9, 0x8704", "cd968704") + check_instruction("XOR3 $11, $SP, 0x7411", "cbf67411") + check_instruction("XOR3 $SP, $8, 0x8801", "cf868801") + check_instruction("XOR3 $12, $8, 0x8648", "cc868648") + check_instruction("XOR3 $5, $8, 0xC5", "c58600c5") + + def test_SB(self): + """Test the SB instruction""" + + # Top instructions + check_instruction("SB $12, 0x14($SP)", "ccf80014") + check_instruction("SB $4, 0x4($SP)", "c4f80004") + check_instruction("SB $4, 0x3($3)", "c4380003") + check_instruction("SB $11, 0x17($SP)", "cbf80017") + check_instruction("SB $12, 0x16($SP)", "ccf80016") + + # Randomly choosen instructions + check_instruction("SB $TP, -31053($6)", "cd6886b3") + check_instruction("SB $3, 0x6E($8)", "c388006e") + check_instruction("SB $7, 0x81($8)", "c7880081") + check_instruction("SB $11, 0x1FE($7)", "cb7801fe") + check_instruction("SB $11, 0x7B($4)", "cb48007b") + + def test_SH(self): + """Test the SH instruction""" + + # Top instructions + check_instruction("SH $11, 0x8($12)", "cbc90008") + check_instruction("SH $11, 0x2($4)", "cb490002") + check_instruction("SH $4, 0xE($SP)", "c4f9000e") + check_instruction("SH $4, 0xC($SP)", "c4f9000c") + check_instruction("SH $11, 0x1E($4)", "cb49001e") + + # Randomly choosen instructions + check_instruction("SH $SP, -30753($6)", "cf6987df") + check_instruction("SH $12, 0x6C4($TP)", "ccd906c4") + check_instruction("SH $4, 0x38($3)", "c4390038") + check_instruction("SH $TP, 0x8($2)", "cd290008") + check_instruction("SH $11, 0x62F5($10)", "cba962f5") + + # Manually generated instruction + check_instruction("SH $0, 0x7FFF($1)", "c0197fff") + check_instruction("SH $0, -32767($1)", "c0198001") + + def test_SW(self): + """Test the SW instruction""" + + # Top instructions + check_instruction("SW $12, 0x4($1)", "cc1a0004") + check_instruction("SW $9, 0x4($6)", "c96a0004") + check_instruction("SW $12, 0x10($4)", "cc4a0010") + check_instruction("SW $10, 0xC($12)", "caca000c") + check_instruction("SW $10, 0x4($12)", "caca0004") + + # Randomly choosen instructions + check_instruction("SW $12, 0x100($1)", "cc1a0100") + check_instruction("SW $10, 0x88($6)", "ca6a0088") + check_instruction("SW $0, 0x188($SP)", "c0fa0188") + check_instruction("SW $10, 0x22C($SP)", "cafa022c") + check_instruction("SW $4, 0x60A9($SP)", "c4fa60a9") + + def test_LBU(self): + """Test the LBU instruction""" + + # Top instructions + check_instruction("LBU $10, 0x3($12)", "cacb0003") + check_instruction("LBU $12, 0x2($0)", "cc0b0002") + check_instruction("LBU $4, 0x2($7)", "c47b0002") + check_instruction("LBU $12, 0x16($SP)", "ccfb0016") + check_instruction("LBU $11, 0x2($4)", "cb4b0002") + + # Randomly choosen instructions + check_instruction("LBU $12, 0x16($4)", "cc4b0016") + check_instruction("LBU $2, 0x3($11)", "c2bb0003") + check_instruction("LBU $7, 0x5($2)", "c72b0005") + check_instruction("LBU $12, 0x1E1($1)", "cc1b01e1") + check_instruction("LBU $10, -31425($6)", "ca6b853f") + + def test_LB(self): + """Test the LB instruction""" + + # Top instructions + check_instruction("LB $9, 0x26($1)", "c91c0026") + check_instruction("LB $4, 0x5($7)", "c47c0005") + check_instruction("LB $12, 0x14($SP)", "ccfc0014") + check_instruction("LB $9, 0x2($12)", "c9cc0002") + check_instruction("LB $12, 0x16($SP)", "ccfc0016") + + # Randomly choosen instructions + check_instruction("LB $0, 0x5784($10)", "c0ac5784") + check_instruction("LB $11, -31243($9)", "cb9c85f5") + check_instruction("LB $5, 0x11($6)", "c56c0011") + check_instruction("LB $4, 0x154($7)", "c47c0154") + check_instruction("LB $12, 0x18($SP)", "ccfc0018") + + def test_LH(self): + """Test the LH instruction""" + + # Top instructions + check_instruction("LH $4, 0x14($SP)", "c4fd0014") + check_instruction("LH $4, 0x6($8)", "c48d0006") + check_instruction("LH $4, 0x10($7)", "c47d0010") + check_instruction("LH $4, 0x4($8)", "c48d0004") + check_instruction("LH $9, 0x10($1)", "c91d0010") + + # Randomly choosen instructions + check_instruction("LH $4, 0x8($8)", "c48d0008") + check_instruction("LH $12, 0x8($10)", "ccad0008") + check_instruction("LH $6, -32042($6)", "c66d82d6") + check_instruction("LH $9, -31509($8)", "c98d84eb") + check_instruction("LH $0, 0x7E8D($6)", "c06d7e8d") + + def test_LW(self): + """Test the LW instruction""" + + # Top instructions + check_instruction("LW $4, 0x1C($8)", "c48e001c") + check_instruction("LW $12, 0x4($11)", "ccbe0004") + check_instruction("LW $7, 0x18($3)", "c73e0018") + check_instruction("LW $2, 0x8($8)", "c28e0008") + check_instruction("LW $4, 0x14($8)", "c48e0014") + + # Randomly choosen instructions + check_instruction("LW $12, 0x1D48($7)", "cc7e1d48") + check_instruction("LW $8, 0x58($1)", "c81e0058") + check_instruction("LW $12, 0xB0($7)", "cc7e00b0") + check_instruction("LW $SP, 0x6653($SP)", "cffe6653") + check_instruction("LW $12, -8($10)", "ccaefff8") + + def test_LHU(self): + """Test the LHU instruction""" + + # Top instructions + check_instruction("LHU $3, 0x10($8)", "c38f0010") + check_instruction("LHU $12, 0x10($1)", "cc1f0010") + check_instruction("LHU $4, 0x2($8)", "c48f0002") + check_instruction("LHU $4, 0x18($8)", "c48f0018") + check_instruction("LHU $2, 0x10($8)", "c28f0010") + + # Randomly choosen instructions + check_instruction("LHU $12, 0x94($8)", "cc8f0094") + check_instruction("LHU $4, 0xE($6)", "c46f000e") + check_instruction("LHU $11, 0x5B59($GP)", "cbef5b59") + check_instruction("LHU $1, 0x601D($10)", "c1af601d") + check_instruction("LHU $6, 0x74F6($11)", "c6bf74f6") diff --git a/test/arch/mep/asm/test_major_opcode_13.py b/test/arch/mep/asm/test_major_opcode_13.py new file mode 100644 index 00000000..b6e99dd5 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_13.py @@ -0,0 +1,143 @@ +# Toshiba MeP-c4 - Major Opcode #13 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor13: + + def test_MOVU(self): + """Test the MOVU instruction""" + + # Top instructions + check_instruction("MOVU $0, 0xC901", "d00100c9", multi=2) + check_instruction("MOVU $4, 0xC7C708", "d408c7c7", multi=2) + check_instruction("MOVU $4, 0x202EFE", "d4fe202e", multi=2) + check_instruction("MOVU $4, 0x202EE0", "d4e0202e", multi=2) + check_instruction("MOVU $4, 0xC12A8E", "d48ec12a", multi=2) + + # Randomly choosen instructions + check_instruction("MOVU $4, 0x1D7100", "d4001d71", multi=2) + check_instruction("MOVU $4, 0x8A395B", "d45b8a39", multi=2) + check_instruction("MOVU $4, 0x67A3E6", "d4e667a3", multi=2) + check_instruction("MOVU $2, 0xCA2D02", "d202ca2d", multi=2) + check_instruction("MOVU $1, 0xCE820C", "d10cce82", multi=2) + + def test_BCPEQ(self): + """Test the BCPEQ instruction""" + + # Top instructions + check_instruction("BCPEQ 0xE, 0xA504", "d8e45282") + check_instruction("BCPEQ 0x4, 0xD5F4", "d8446afa") + check_instruction("BCPEQ 0xC, 0xAADA", "d8c4556d") + check_instruction("BCPEQ 0x7, 0xFFFF18F6", "d8748c7b") + + # Randomly choosen instructions + check_instruction("BCPEQ 0x6, 0xFFFF18CA", "d8648c65") + + def test_BCPNE(self): + """Test the BCPNE instruction""" + + # Top instructions + check_instruction("BCPNE 0xF, 0x9DEA", "d8f54ef5") + check_instruction("BCPNE 0x5, 0xFFFF18A4", "d8558c52") + check_instruction("BCPNE 0x7, 0xFFFF18FA", "d8758c7d") + check_instruction("BCPNE 0x1, 0x674E", "d81533a7") + + # Randomly choosen instructions + check_instruction("BCPNE 0xB, 0xD820", "d8b56c10") + check_instruction("BCPNE 0x8, 0xFFFF1922", "d8858c91") + check_instruction("BCPNE 0xD, 0xA6C8", "d8d55364") + check_instruction("BCPNE 0xA, 0xBDFE", "d8a55eff") + check_instruction("BCPNE 0x8, 0xFFFF1920", "d8858c90") + + def test_BCPAT(self): + """Test the BCPAT instruction""" + + # Top instructions + check_instruction("BCPAT 0xE, 0xA526", "d8e65293") + check_instruction("BCPAT 0xF, 0x9E4A", "d8f64f25") + check_instruction("BCPAT 0x8, 0xFFFF1922", "d8868c91") + check_instruction("BCPAT 0xC, 0x9D88", "d8c64ec4") + check_instruction("BCPAT 0x7, 0xFFFF18FA", "d8768c7d") + + # Randomly choosen instructions + check_instruction("BCPAT 0x6, 0xFFFF18D0", "d8668c68") + check_instruction("BCPAT 0x7, 0xFFFF18FC", "d8768c7e") + check_instruction("BCPAT 0x6, 0xFFFF18CE", "d8668c67") + check_instruction("BCPAT 0x5, 0xFFFF18A8", "d8568c54") + check_instruction("BCPAT 0xB, 0xADBE", "d8b656df") + + def test_BCPAF(self): + """Test the BCPAF instruction""" + + # Top instructions + check_instruction("BCPAF 0xE, 0xA304", "d8e75182") + check_instruction("BCPAF 0x5, 0xFFFF18AA", "d8578c55") + check_instruction("BCPAF 0xB, 0xFFFF01C8", "d8b780e4") + check_instruction("BCPAF 0xF, 0x9E4E", "d8f74f27") + check_instruction("BCPAF 0xD, 0xA412", "d8d75209") + + # Randomly choosen instructions + check_instruction("BCPAF 0xB, 0xFFFF01CA", "d8b780e5") + check_instruction("BCPAF 0xA, 0x9C2A", "d8a74e15") + check_instruction("BCPAF 0x8, 0xFFFF1924", "d8878c92") + check_instruction("BCPAF 0x6, 0xFFFF18D2", "d8678c69") + check_instruction("BCPAF 0xC, 0xA71A", "d8c7538d") + + def test_JMP(self): + """Test the JMP instruction""" + + # Top instructions + check_instruction("JMP 0xC9706A", "db58c970") + check_instruction("JMP 0xC7517A", "dbd8c751") + check_instruction("JMP 0x4", "d8280000") + check_instruction("JMP 0x80FF2C", "d96880ff") + check_instruction("JMP 0x814174", "dba88141") + + # Randomly choosen instructions + check_instruction("JMP 0xC3F782", "dc18c3f7") + check_instruction("JMP 0xC814", "d8a800c8") + check_instruction("JMP 0x9079EE", "df789079") + check_instruction("JMP 0xC6982A", "d958c698") + check_instruction("JMP 0xC3986C", "db68c398") + + # Manually crafted + check_instruction("JMP 0xC3F782", "dc18c3f7", offset=0x1024) + + def test_BSR(self): + """Test the BSR instruction""" + + # Top instructions + check_instruction("BSR 0xFFFEFB20", "d909fefb", multi=2) + check_instruction("BSR 0x603A92", "dc99603a", multi=2) + check_instruction("BSR 0xAF64", "db2900af", multi=2) + check_instruction("BSR 0x36C4", "de290036", multi=2) + check_instruction("BSR 0xFFFC6AC4", "de29fc6a", multi=2) + + # Randomly choosen instructions + check_instruction("BSR 0x22C", "d9690002", multi=2) + check_instruction("BSR 0x5FEE6A", "db595fee", multi=2) + check_instruction("BSR 0x4AFF4", "dfa904af", multi=2) + check_instruction("BSR 0x1B126", "d93901b1", multi=2) + check_instruction("BSR 0xFFFB3F76", "dbb9fb3f", multi=2) + + # Manually crafted + check_instruction("BSR 0xC7FB84", "d869017f", offset=0xc67c78) + + def test_BSRV(self): + """Test the BSRV instruction""" + + # Top instructions + check_instruction("BSRV 0x8E8488", "dc4b8e84") + check_instruction("BSRV 0x8E396E", "db7b8e39") + check_instruction("BSRV 0xF785CE", "de7bf785") + check_instruction("BSRV 0x6509F4", "dfab6509") + check_instruction("BSRV 0x8F50C8", "de4b8f50") + + # Randomly choosen instructions + check_instruction("BSRV 0x544BF6", "dfbb544b") + check_instruction("BSRV 0x8CCA2A", "d95b8cca") + check_instruction("BSRV 0x4F681E", "d8fb4f68") + check_instruction("BSRV 0x8EAA8C", "dc6b8eaa") + check_instruction("BSRV 0x30A030", "d98b30a0") diff --git a/test/arch/mep/asm/test_major_opcode_14.py b/test/arch/mep/asm/test_major_opcode_14.py new file mode 100644 index 00000000..1c2ac466 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_14.py @@ -0,0 +1,179 @@ +# Toshiba MeP-c4 - Major Opcode #14 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor14: + + def test_BEQI(self): + """Test the BEQI instruction""" + + # Top instructions + check_instruction("BEQI $0, 0x5, 0x32", "e0500019") + check_instruction("BEQI $4, 0x3, 0x3C", "e430001e") + check_instruction("BEQI $4, 0x3, 0x20", "e4300010") + check_instruction("BEQI $0, 0xA, 0x8", "e0a00004") + check_instruction("BEQI $0, 0x0, 0xC4", "e0000062") + + # Randomly choosen instructions + check_instruction("BEQI $0, 0x1, 0xFFFFFF6A", "e010ffb5") + check_instruction("BEQI $1, 0x2, 0x20", "e1200010") + check_instruction("BEQI $9, 0x0, 0xE0", "e9000070") + check_instruction("BEQI $5, 0x8, 0xFFFF2696", "e580934b") + check_instruction("BEQI $4, 0xA, 0x0", "e4a00000") + + def test_BEQ(self): + """Test the BEQ instruction""" + + # Top instructions + check_instruction("BEQ $12, $9, 0x3A", "ec91001d") + check_instruction("BEQ $11, $10, 0x34", "eba1001a") + check_instruction("BEQ $11, $12, 0x1E", "ebc1000f") + check_instruction("BEQ $0, $0, 0x102", "e0010081") + check_instruction("BEQ $7, $11, 0x56", "e7b1002b") + + # Randomly choosen instructions + check_instruction("BEQ $11, $9, 0x26", "eb910013") + check_instruction("BEQ $12, $11, 0x28", "ecb10014") + check_instruction("BEQ $0, $0, 0xA12", "e0010509") + check_instruction("BEQ $12, $3, 0x24", "ec310012") + check_instruction("BEQ $10, $TP, 0xE", "ead10007") + + # Manually crafted + check_instruction("BEQ $0, $12, 0xC67CA4", "e0c10024", offset=0xc67c5c) + + def test_BNEI(self): + """Test the BNEI instruction""" + + # Top instructions + check_instruction("BNEI $0, 0x1, 0x16", "e014000b") + check_instruction("BNEI $11, 0x1, 0x1E", "eb14000f") + check_instruction("BNEI $0, 0x1, 0xFFFFFFB4", "e014ffda") + check_instruction("BNEI $4, 0x2, 0xDA", "e424006d") + check_instruction("BNEI $12, 0x1, 0x8", "ec140004") + + # Randomly choosen instructions + check_instruction("BNEI $12, 0x2, 0x6", "ec240003") + check_instruction("BNEI $3, 0xC, 0xFFFF2D68", "e3c496b4") + check_instruction("BNEI $4, 0x1, 0x10", "e4140008") + check_instruction("BNEI $4, 0x1, 0x2A", "e4140015") + check_instruction("BNEI $TP, 0xC, 0xF040", "edc47820") + + def test_BNE(self): + """Test the BNE instruction""" + + # Top instructions + check_instruction("BNE $TP, $7, 0xFFFFFFCC", "ed75ffe6") + check_instruction("BNE $12, $TP, 0x6", "ecd50003") + check_instruction("BNE $10, $11, 0x1C", "eab5000e") + check_instruction("BNE $3, $0, 0xFFFF35A8", "e3059ad4") + check_instruction("BNE $10, $3, 0xA", "ea350005") + + # Randomly choosen instructions + check_instruction("BNE $4, $12, 0x8", "e4c50004") + check_instruction("BNE $4, $1, 0x10", "e4150008") + check_instruction("BNE $4, $12, 0x34", "e4c5001a") + check_instruction("BNE $10, $11, 0x1C", "eab5000e") + check_instruction("BNE $2, $11, 0xFFFFFFD8", "e2b5ffec") + + def test_BGEI(self): + """Test the BGEI instruction""" + + # Top instructions + check_instruction("BGEI $4, 0x3, 0xE", "e4380007") + check_instruction("BGEI $11, 0x3, 0xFFFFFFF2", "eb38fff9") + check_instruction("BGEI $TP, 0x0, 0x12", "ed080009") + check_instruction("BGEI $12, 0x0, 0x22", "ec080011") + check_instruction("BGEI $GP, 0xE, 0xFFFF2996", "eee894cb") + + # Randomly choosen instructions + check_instruction("BGEI $4, 0x5, 0x52", "e4580029") + check_instruction("BGEI $1, 0x4, 0xA", "e1480005") + check_instruction("BGEI $8, 0x0, 0x10", "e8080008") + check_instruction("BGEI $11, 0x3, 0xFFFFFFF2", "eb38fff9") + + def test_REPEAT(self): + """Test the REPEAT instruction""" + + # Top instructions + check_instruction("REPEAT $2, 0x2A", "e2090015") + check_instruction("REPEAT $10, 0x16", "ea09000b") + check_instruction("REPEAT $12, 0x6", "ec090003") + check_instruction("REPEAT $11, 0x8", "eb090004") + check_instruction("REPEAT $11, 0x6", "eb090003") + + # Randomly choosen instructions + check_instruction("REPEAT $12, 0x24", "ec090012") + check_instruction("REPEAT $9, 0x8", "e9090004") + check_instruction("REPEAT $12, 0x14", "ec09000a") + check_instruction("REPEAT $10, 0x6", "ea090003") + check_instruction("REPEAT $10, 0x8", "ea090004") + + def test_EREPEAT(self): + """Test the EREPEAT instruction""" + + # Top instructions + check_instruction("EREPEAT 0xA", "e0190005") + check_instruction("EREPEAT 0x24", "e0190012") + check_instruction("EREPEAT 0x18", "e019000c") + check_instruction("EREPEAT 0x12", "e0190009") + check_instruction("EREPEAT 0x1C", "e019000e") + + # Randomly choosen instructions + check_instruction("EREPEAT 0x12", "e0190009") + check_instruction("EREPEAT 0x7E", "e019003f") + check_instruction("EREPEAT 0x8", "e0190004") + check_instruction("EREPEAT 0x1A", "e019000d") + check_instruction("EREPEAT 0xC", "e0190006") + + def test_BLTI(self): + """Test the BLTI instruction""" + + # Top instructions + check_instruction("BLTI $12, 0x1, 0x26", "ec1c0013") + check_instruction("BLTI $2, 0x2, 0xC", "e22c0006") + check_instruction("BLTI $8, 0x0, 0x10", "e80c0008") + check_instruction("BLTI $7, 0x1, 0x1A", "e71c000d") + check_instruction("BLTI $12, 0x9, 0xEA52", "ec9c7529") + + # Randomly choosen instructions + check_instruction("BLTI $4, 0x6, 0xFFFF25AE", "e46c92d7") + check_instruction("BLTI $12, 0x1, 0x24", "ec1c0012") + check_instruction("BLTI $9, 0xF, 0xFFFF1F0A", "e9fc8f85") + check_instruction("BLTI $2, 0x2, 0x2A", "e22c0015") + check_instruction("BLTI $12, 0x8, 0xFFFFFFCE", "ec8cffe7") + + def test_SW(self): + """Test the SW instruction""" + + # Top instructions + check_instruction("SW $4, (0x825BE0)", "e4e2825b") + check_instruction("SW $4, (0x816834)", "e4368168") + check_instruction("SW $4, (0x817318)", "e41a8173") + check_instruction("SW $4, (0x826864)", "e4668268") + check_instruction("SW $4, (0x826994)", "e4968269") + + # Randomly choosen instructions + check_instruction("SW $1, (0x815864)", "e1668158") + check_instruction("SW $1, (0x825BD8)", "e1da825b") + check_instruction("SW $10, (0x6225AC)", "eaae6225") + check_instruction("SW $GP, (0x9497CC)", "eece9497") + check_instruction("SW $3, (0x6CEEF8)", "e3fa6cee") + + def test_LW(self): + """Test the LW instruction""" + + # Top instructions + check_instruction("LW $0, (0x8200)", "e0030082") + check_instruction("LW $4, (0x816820)", "e4238168") + check_instruction("LW $0, (0x8500)", "e0030085") + check_instruction("LW $3, (0x816820)", "e3238168") + check_instruction("LW $4, (0x81F0F0)", "e4f381f0") + + # Randomly choosen instructions + check_instruction("LW $GP, (0x94CEE8)", "eeeb94ce") + check_instruction("LW $4, (0x823608)", "e40b8236") + check_instruction("LW $0, (0x815E40)", "e043815e") + check_instruction("LW $0, (0x814D50)", "e053814d") + check_instruction("LW $0, (0x8269C4)", "e0c78269") diff --git a/test/arch/mep/asm/test_major_opcode_15.py b/test/arch/mep/asm/test_major_opcode_15.py new file mode 100644 index 00000000..8eeb2eff --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_15.py @@ -0,0 +1,583 @@ +# Toshiba MeP-c4 - Major Opcode #15 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor15: + + def test_DSP(self): + """Test the DSP instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("DSP $1, $2, 0x3", "f1200003") + + def test_DSP0(self): + """Test the DSP0 instruction""" + + # No samples were found + assert(True) + + def test_DSP1(self): + """Test the DSP1 instruction""" + + # No samples were found + assert(True) + + def test_LDZ(self): + """Test the LDZ instruction""" + + # Top instructions + check_instruction("LDZ $10, $9", "fa910000") + check_instruction("LDZ $SP, $12", "ffc10000") + + def test_AVE(self): + """Test the AVE instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("AVE $1, $2", "f1210002") + + def test_ABS(self): + """Test the ABS instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("ABS $1, $2", "f1210003") + + def test_MIN(self): + """Test the MIN instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("MIN $1, $2", "f1210004") + + def test_MAX(self): + """Test the MAX instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("MAX $1, $2", "f1210005") + + def test_MINU(self): + """Test the MINU instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("MINU $1, $2", "f1210006") + + def test_MAXU(self): + """Test the MAXU instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("MAXU $1, $2", "f1210007") + + def test_SADD(self): + """Test the SADD instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SADD $1, $2", "f1210008") + + def test_SADDU(self): + """Test the SADDU instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SADDU $1, $2", "f1210009") + + def test_SSUB(self): + """Test the SSUB instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SSUB $1, $2", "f121000a") + + def test_SSUBU(self): + """Test the SSUBU instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SSUBU $1, $2", "f121000b") + + def test_CLIP(self): + """Test the CLIP instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("CLIP $1, 0x2", "f1011010") + + def test_CLIPU(self): + """Test the CLIPU instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("CLIPU $1, 0x2", "f1011011") + + def test_MADD(self): + """Test the MADD instruction""" + + # Top instructions + check_instruction("MADD $3, $12", "f3c13004") + check_instruction("MADD $11, $1", "fb113004") + check_instruction("MADD $9, $1", "f9113004") + check_instruction("MADD $10, $4", "fa413004") + check_instruction("MADD $4, $11", "f4b13004") + + # Randomly choosen instructions + check_instruction("MADD $7, $10", "f7a13004") + check_instruction("MADD $0, $10", "f0a13004") + check_instruction("MADD $12, $9", "fc913004") + check_instruction("MADD $5, $TP", "f5d13004") + check_instruction("MADD $10, $12", "fac13004") + + def test_MADDU(self): + """Test the MADDU instruction""" + + # Top instructions + check_instruction("MADDU $12, $11", "fcb13005") + check_instruction("MADDU $6, $12", "f6c13005") + check_instruction("MADDU $6, $11", "f6b13005") + check_instruction("MADDU $6, $9", "f6913005") + check_instruction("MADDU $6, $10", "f6a13005") + + # Randomly choosen instructions + check_instruction("MADDU $10, $12", "fac13005") + check_instruction("MADDU $10, $2", "fa213005") + check_instruction("MADDU $1, $12", "f1c13005") + check_instruction("MADDU $11, $10", "fba13005") + check_instruction("MADDU $8, $12", "f8c13005") + + def test_MADDR(self): + """Test the MADDR instruction""" + + # Top instructions + check_instruction("MADDR $12, $3", "fc313006") + check_instruction("MADDR $10, $2", "fa213006") + check_instruction("MADDR $6, $12", "f6c13006") + check_instruction("MADDR $11, $10", "fba13006") + + def test_MADDRU(self): + """Test the MADDRU instruction""" + + # Top instructions + check_instruction("MADDRU $11, $2", "fb213007") + check_instruction("MADDRU $10, $9", "fa913007") + check_instruction("MADDRU $12, $10", "fca13007") + check_instruction("MADDRU $11, $1", "fb113007") + check_instruction("MADDRU $12, $1", "fc113007") + + # Randomly choosen instructions + check_instruction("MADDRU $1, $0", "f1013007") + check_instruction("MADDRU $10, $3", "fa313007") + check_instruction("MADDRU $12, $11", "fcb13007") + check_instruction("MADDRU $12, $9", "fc913007") + check_instruction("MADDRU $3, $1", "f3113007") + + def test_UCI(self): + """Test the UCI instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("UCI $1, $2, 0x3", "f1220003") + + def test_STCB(self): + """Test the STCB instruction""" + + # Top instructions + check_instruction("STCB $11, 0x1000", "fb041000") + check_instruction("STCB $3, 0x1005", "f3041005") + check_instruction("STCB $1, 0x1004", "f1041004") + check_instruction("STCB $11, 0x0", "fb040000") + check_instruction("STCB $12, 0x4100", "fc044100") + + # Randomly choosen instructions + check_instruction("STCB $2, 0x4007", "f2044007") + check_instruction("STCB $10, 0x4002", "fa044002") + check_instruction("STCB $11, 0x2", "fb040002") + check_instruction("STCB $10, 0x420", "fa040420") + check_instruction("STCB $4, 0x405", "f4040405") + + def test_LDCB(self): + """Test the LDCB instruction""" + + # Top instructions + check_instruction("LDCB $12, 0x3", "fc140003") + check_instruction("LDCB $12, 0x1001", "fc141001") + check_instruction("LDCB $11, 0x1000", "fb141000") + check_instruction("LDCB $12, 0x1000", "fc141000") + check_instruction("LDCB $12, 0x0", "fc140000") + + # Randomly choosen instructions + check_instruction("LDCB $12, 0x420", "fc140420") + check_instruction("LDCB $10, 0x1", "fa140001") + check_instruction("LDCB $11, 0x5", "fb140005") + check_instruction("LDCB $2, 0x4002", "f2144002") + check_instruction("LDCB $1, 0x4005", "f1144005") + + def test_SBCPA(self): + """Test the SBCPA instruction""" + + # Top instructions + check_instruction("SBCPA $C5, ($GP+), -50", "f5e500ce") + check_instruction("SBCPA $C5, ($GP+), -55", "f5e500c9") + check_instruction("SBCPA $C6, ($9+), -50", "f69500ce") + check_instruction("SBCPA $C4, ($TP+), -52", "f4d500cc") + check_instruction("SBCPA $C6, ($4+), -55", "f64500c9") + + # Randomly choosen instructions + check_instruction("SBCPA $C2, ($SP+), -51", "f2f500cd") + check_instruction("SBCPA $C13, ($8+), -52", "fd8500cc") + check_instruction("SBCPA $C2, ($TP+), -51", "f2d500cd") + check_instruction("SBCPA $C6, ($6+), -55", "f66500c9") + check_instruction("SBCPA $C2, ($10+), -51", "f2a500cd") + + def test_SHCPA(self): + """Test the SHCPA instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SHCPA $C1, ($2+), 6", "f1251006") + + def test_SWCPA(self): + """Test the SWCPA instruction""" + + # Top instructions + check_instruction("SWCPA $C10, ($5+), 48", "fa552030") + + # Manually generated instruction + check_instruction("SWCPA $C1, ($2+), 4", "f1252004") + + def test_SMCPA(self): + """Test the SMCPA instruction""" + + # Top instructions + check_instruction("SMCPA $C15, ($0+), -16", "ff0530f0") + check_instruction("SMCPA $C15, ($0+), 32", "ff053020") + + # Manually generated instruction + check_instruction("SMCPA $C1, ($2+), 8", "f1253008") + + def test_LBCPA(self): + """Test the LBCPA instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LBCPA $C1, ($2+), 8", "f1254008") + + def test_LHCPA(self): + """Test the LHCPA instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LHCPA $C1, ($2+), 8", "f1255008") + + def test_LWCPA(self): + """Test the LWCPA instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LWCPA $C1, ($2+), 8", "f1256008") + + def test_LMCPA(self): + """Test the LMCPA instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LMCPA $C1, ($2+), 8", "f1257008") + + def test_SBCPM0(self): + """Test the SBCPM0 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SBCPM0 $C1, ($2+), 8", "f1250808") + + def test_SHCPM0(self): + """Test the SHCPM0 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SHCPM0 $C1, ($2+), 8", "f1251808") + + def test_SWCPM0(self): + """Test the SWCPM0 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SWCPM0 $C1, ($2+), 8", "f1252808") + + def test_SMCPM0(self): + """Test the SMCPM0 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SMCPM0 $C1, ($2+), 8", "f1253808") + + def test_LBCPM0(self): + """Test the LBCPM0 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LBCPM0 $C1, ($2+), 8", "f1254808") + + def test_LHCPM0(self): + """Test the LHCPM0 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LHCPM0 $C1, ($2+), 8", "f1255808") + + def test_LWCPM0(self): + """Test the LWCPM0 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LWCPM0 $C1, ($2+), 8", "f1256808") + + def test_LMCPM0(self): + """Test the LMCPM0 instruction""" + + # Top instructions + check_instruction("LMCPM0 $C3, ($12+), 8", "f3c57808") + check_instruction("LMCPM0 $C1, ($11+), -32", "f1b578e0") + check_instruction("LMCPM0 $C3, ($TP+), 48", "f3d57830") + check_instruction("LMCPM0 $C3, ($GP+), -96", "f3e578a0") + check_instruction("LMCPM0 $C3, ($SP+), -40", "f3f578d8") + + def test_SBCPM1(self): + """Test the SBCPM1 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SBCPM1 $C1, ($2+), 8", "f1250c08") + + def test_SHCPM1(self): + """Test the SHCPM1 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SHCPM1 $C1, ($2+), 8", "f1251c08") + + def test_SWCPM1(self): + """Test the SWCPM1 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SWCPM1 $C1, ($2+), 8", "f1252c08") + + def test_SMCPM1(self): + """Test the SMCPM1 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("SMCPM1 $C1, ($2+), 8", "f1253c08") + + def test_LBCPM1(self): + """Test the LBCPM1 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LBCPM1 $C1, ($2+), 8", "f1254c08") + + def test_LHCPM1(self): + """Test the LHCPM1 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LHCPM1 $C1, ($2+), 8", "f1255c08") + + def test_LWCPM1(self): + """Test the LWCPM1 instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("LWCPM1 $C1, ($2+), 8", "f1256c08") + + def test_LMCPM1(self): + """Test the LMCPM1 instruction""" + + # Top instructions + check_instruction("LMCPM1 $C9, ($4+), 48", "f9457c30") + check_instruction("LMCPM1 $C4, ($10+), 64", "f4a57c40") + check_instruction("LMCPM1 $C4, ($TP+), -72", "f4d57cb8") + check_instruction("LMCPM1 $C4, ($GP+), -32", "f4e57ce0") + + def test_CP(self): + """Test the CP instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + #check_instruction("CP 0x280780", "f2870780") + + def test_CMOV(self): + """Test the CMOV instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("CMOV $C0, $1", "f017f000") + check_instruction("CMOV $1, $C0", "f017f001") + check_instruction("CMOV $C28, $1", "fc17f008") + check_instruction("CMOV $1, $C28", "fc17f009") + + def test_CMOVC(self): + """Test the CMOVC instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("CMOVC $C0, $1", "f017f002") + check_instruction("CMOVC $2, $C3", "f327f003") + + def test_CMOVH(self): + """Test the CMOVH instruction""" + + # No samples were found + assert(True) + + # Manually generated instruction + check_instruction("CMOVH $C0, $1", "f017f100") + check_instruction("CMOVH $2, $C3", "f327f101") + check_instruction("CMOVH $C29, $12", "fdc7f108") + check_instruction("CMOVH $SP, $C30", "fef7f109") + + def test_SWCP(self): + """Test the SWCP instruction""" + + # Top instructions + check_instruction("SWCP $C7, 197($12)", "f7cc00c5") + check_instruction("SWCP $C1, 194($7)", "f17c00c2") + check_instruction("SWCP $C14, -16690($10)", "feacbece") + check_instruction("SWCP $C2, 24658($5)", "f25c6052") + check_instruction("SWCP $C0, 27132($9)", "f09c69fc") + + # Randomly choosen instructions + check_instruction("SWCP $C9, 195($10)", "f9ac00c3") + check_instruction("SWCP $C5, -25704($5)", "f55c9b98") + check_instruction("SWCP $C2, -31068($11)", "f2bc86a4") + check_instruction("SWCP $C6, -27760($12)", "f6cc9390") + check_instruction("SWCP $C4, -28337($SP)", "f4fc914f") + + def test_LWCP(self): + """Test the LWCP instruction""" + + # Top instructions + check_instruction("LWCP $C9, 9890($1)", "f91d26a2") + check_instruction("LWCP $C1, 10757($6)", "f16d2a05") + check_instruction("LWCP $C4, -14058($8)", "f48dc916") + check_instruction("LWCP $C15, -26720($8)", "ff8d97a0") + check_instruction("LWCP $C15, 26934($4)", "ff4d6936") + + # Randomly choosen instructions + check_instruction("LWCP $C11, -25049($5)", "fb5d9e27") + check_instruction("LWCP $C6, -25560($8)", "f68d9c28") + check_instruction("LWCP $C7, -24867($GP)", "f7ed9edd") + check_instruction("LWCP $C0, 30229($SP)", "f0fd7615") + check_instruction("LWCP $C7, -25527($4)", "f74d9c49") + + def test_SMCP(self): + """Test the SMCP instruction""" + + # Top instructions + check_instruction("SMCP $C15, 2047($SP)", "fffe07ff") + check_instruction("SMCP $C15, -1($SP)", "fffeffff") + check_instruction("SMCP $C4, 17362($9)", "f49e43d2") + check_instruction("SMCP $C3, 6490($4)", "f34e195a") + check_instruction("SMCP $C2, -11232($10)", "f2aed420") + + # Randomly choosen instructions + check_instruction("SMCP $C6, 201($7)", "f67e00c9") + check_instruction("SMCP $C3, -25912($6)", "f36e9ac8") + check_instruction("SMCP $C9, -25215($7)", "f97e9d81") + check_instruction("SMCP $C0, -26294($7)", "f07e994a") + check_instruction("SMCP $C3, 32566($11)", "f3be7f36") + + def test_LMCP(self): + """Test the LMCP instruction""" + + # Top instructions + check_instruction("LMCP $C9, 6994($11)", "f9bf1b52") + check_instruction("LMCP $C12, -8368($3)", "fc3fdf50") + check_instruction("LMCP $C4, -13277($GP)", "f4efcc23") + check_instruction("LMCP $C15, 4095($SP)", "ffff0fff") + check_instruction("LMCP $C15, -1($SP)", "ffffffff") + + # Randomly choosen instructions + check_instruction("LMCP $C7, -24863($GP)", "f7ef9ee1") + check_instruction("LMCP $C14, 16674($SP)", "feff4122") + check_instruction("LMCP $C13, 1023($SP)", "fdff03ff") + check_instruction("LMCP $C1, -32729($GP)", "f1ef8027") + check_instruction("LMCP $C15, 30719($SP)", "ffff77ff") diff --git a/test/arch/mep/asm/test_major_opcode_2.py b/test/arch/mep/asm/test_major_opcode_2.py new file mode 100644 index 00000000..913d8756 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_2.py @@ -0,0 +1,194 @@ +# Toshiba MeP-c4 - Major Opcode #2 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor2: + + def test_BSETM(self): + """Test the BSETM instruction""" + + # Top instructions + check_instruction("BSETM ($0), 0x0", "2000") + check_instruction("BSETM ($0), 0x5", "2500") + check_instruction("BSETM ($3), 0x0", "2030") + check_instruction("BSETM ($2), 0x5", "2520") + check_instruction("BSETM ($2), 0x0", "2020") + + # Randomly choosen instructions + check_instruction("BSETM ($8), 0x4", "2480") + check_instruction("BSETM ($5), 0x5", "2550") + check_instruction("BSETM ($5), 0x0", "2050") + check_instruction("BSETM ($0), 0x7", "2700") + check_instruction("BSETM ($TP), 0x0", "20d0") + + def test_BCLRM(self): + """Test the BCLRM instruction""" + + # Top instructions + check_instruction("BCLRM ($3), 0x0", "2031") + check_instruction("BCLRM ($2), 0x0", "2021") + check_instruction("BCLRM ($1), 0x2", "2211") + check_instruction("BCLRM ($2), 0x1", "2121") + check_instruction("BCLRM ($0), 0x0", "2001") + + # Randomly choosen instructions + check_instruction("BCLRM ($6), 0x4", "2461") + check_instruction("BCLRM ($7), 0x4", "2471") + check_instruction("BCLRM ($6), 0x5", "2561") + check_instruction("BCLRM ($0), 0x2", "2201") + check_instruction("BCLRM ($0), 0x1", "2101") + + def test_BNOTM(self): + """Test the BNOTM instruction""" + + # Top instructions + check_instruction("BNOTM ($7), 0x1", "2172") + check_instruction("BNOTM ($2), 0x1", "2122") + check_instruction("BNOTM ($SP), 0x0", "20f2") + check_instruction("BNOTM ($3), 0x0", "2032") + check_instruction("BNOTM ($7), 0x0", "2072") + + # Randomly choosen instructions + check_instruction("BNOTM ($6), 0x4", "2462") + check_instruction("BNOTM ($2), 0x2", "2222") + check_instruction("BNOTM ($0), 0x1", "2102") + check_instruction("BNOTM ($2), 0x0", "2022") + check_instruction("BNOTM ($1), 0x2", "2212") + + def test_BTSTM(self): + """Test the BTSTM instruction""" + + # Top instructions + check_instruction("BTSTM $0, ($12), 0x3", "23c3") + check_instruction("BTSTM $0, ($6), 0x0", "2063") + check_instruction("BTSTM $0, ($3), 0x0", "2033") + check_instruction("BTSTM $0, ($0), 0x0", "2003") + check_instruction("BTSTM $0, ($7), 0x0", "2073") + + # Randomly choosen instructions + check_instruction("BTSTM $0, ($2), 0x4", "2423") + check_instruction("BTSTM $0, ($12), 0x6", "26c3") + check_instruction("BTSTM $0, ($4), 0x5", "2543") + check_instruction("BTSTM $0, ($9), 0x1", "2193") + check_instruction("BTSTM $0, ($0), 0x4", "2403") + + def test_TAS(self): + """Test the TAS instruction""" + + # Top instructions + check_instruction("TAS $GP, ($6)", "2e64") + check_instruction("TAS $12, ($TP)", "2cd4") + check_instruction("TAS $9, ($6)", "2964") + check_instruction("TAS $0, ($7)", "2074") + check_instruction("TAS $0, ($6)", "2064") + + # Randomly choosen instructions + check_instruction("TAS $1, ($6)", "2164") + check_instruction("TAS $11, ($3)", "2b34") + check_instruction("TAS $1, ($0)", "2104") + check_instruction("TAS $8, ($7)", "2874") + check_instruction("TAS $8, ($4)", "2844") + + def test_SL1AD3(self): + """Test the SL1AD3 instruction""" + + # Top instructions + check_instruction("SL1AD3 $0, $1, $4", "2146") + check_instruction("SL1AD3 $0, $11, $11", "2bb6") + check_instruction("SL1AD3 $0, $4, $4", "2446") + check_instruction("SL1AD3 $0, $3, $3", "2336") + check_instruction("SL1AD3 $0, $12, $12", "2cc6") + + # Randomly choosen instructions + check_instruction("SL1AD3 $0, $5, $4", "2546") + check_instruction("SL1AD3 $0, $11, $4", "2b46") + check_instruction("SL1AD3 $0, $GP, $3", "2e36") + check_instruction("SL1AD3 $0, $6, $3", "2636") + check_instruction("SL1AD3 $0, $3, $4", "2346") + + def test_SL2AD3(self): + """Test the SL2AD3 instruction""" + + # Top instructions + check_instruction("SL2AD3 $0, $0, $4", "2047") + check_instruction("SL2AD3 $0, $12, $7", "2c77") + check_instruction("SL2AD3 $0, $7, $4", "2747") + check_instruction("SL2AD3 $0, $12, $0", "2c07") + check_instruction("SL2AD3 $0, $11, $4", "2b47") + + # Randomly choosen instructions + check_instruction("SL2AD3 $0, $10, $SP", "2af7") + check_instruction("SL2AD3 $0, $4, $8", "2487") + check_instruction("SL2AD3 $0, $10, $12", "2ac7") + check_instruction("SL2AD3 $0, $9, $TP", "29d7") + check_instruction("SL2AD3 $0, $5, $10", "25a7") + + def test_SRL(self): + """Test the SRL instruction""" + + # Top instructions + check_instruction("SRL $0, $4", "204c") + check_instruction("SRL $3, $7", "237c") + check_instruction("SRL $0, $2", "202c") + check_instruction("SRL $0, $6", "206c") + check_instruction("SRL $SP, $3", "2f3c") + + # Randomly choosen instructions + check_instruction("SRL $9, $6", "296c") + check_instruction("SRL $2, $7", "227c") + check_instruction("SRL $9, $12", "29cc") + check_instruction("SRL $12, $9", "2c9c") + check_instruction("SRL $12, $2", "2c2c") + + def test_SRA(self): + """Test the SRA instruction""" + + # Top instructions + check_instruction("SRA $0, $6", "206d") + check_instruction("SRA $TP, $1", "2d1d") + check_instruction("SRA $5, $3", "253d") + check_instruction("SRA $0, $3", "203d") + check_instruction("SRA $0, $5", "205d") + + # Randomly choosen instructions + check_instruction("SRA $11, $2", "2b2d") + check_instruction("SRA $9, $6", "296d") + check_instruction("SRA $4, $8", "248d") + check_instruction("SRA $8, $3", "283d") + check_instruction("SRA $3, $0", "230d") + + def test_SLL(self): + """Test the SLL instruction""" + + # Top instructions + check_instruction("SLL $10, $1", "2a1e") + check_instruction("SLL $12, $9", "2c9e") + check_instruction("SLL $0, $3", "203e") + check_instruction("SLL $5, $2", "252e") + check_instruction("SLL $0, $6", "206e") + + # Randomly choosen instructions + check_instruction("SLL $4, $0", "240e") + check_instruction("SLL $SP, $10", "2fae") + check_instruction("SLL $0, $4", "204e") + check_instruction("SLL $7, $2", "272e") + check_instruction("SLL $3, $2", "232e") + + def test_FSFT(self): + """Test the FSFT instruction""" + + # Top instructions + check_instruction("FSFT $0, $2", "202f") + check_instruction("FSFT $0, $1", "201f") + check_instruction("FSFT $9, $SP", "29ff") + check_instruction("FSFT $SP, $2", "2f2f") + check_instruction("FSFT $0, $6", "206f") + + # Randomly choosen instructions + check_instruction("FSFT $SP, $6", "2f6f") + check_instruction("FSFT $0, $9", "209f") + check_instruction("FSFT $5, $9", "259f") + check_instruction("FSFT $0, $TP", "20df") + check_instruction("FSFT $0, $GP", "20ef") diff --git a/test/arch/mep/asm/test_major_opcode_3.py b/test/arch/mep/asm/test_major_opcode_3.py new file mode 100644 index 00000000..6802e752 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_3.py @@ -0,0 +1,143 @@ +# Toshiba MeP-c4 - Major Opcode #3 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor3: + + def test_SWCPI(self): + """Test the SWCPI instruction""" + + # Top instructions + check_instruction("SWCPI $C0, ($2+)", "3020") + check_instruction("SWCPI $C3, ($2+)", "3320") + check_instruction("SWCPI $C3, ($3+)", "3330") + check_instruction("SWCPI $C2, ($3+)", "3230") + check_instruction("SWCPI $C0, ($3+)", "3030") + + # Randomly choosen instructions + check_instruction("SWCPI $C2, ($2+)", "3220") + check_instruction("SWCPI $C6, ($10+)", "36a0") + check_instruction("SWCPI $C15, ($SP+)", "3ff0") + check_instruction("SWCPI $C15, ($9+)", "3f90") + check_instruction("SWCPI $C10, ($3+)", "3a30") + + def test_LWCPI(self): + """Test the LWCPI instruction""" + + # Top instructions + check_instruction("LWCPI $C10, ($3+)", "3a31") + check_instruction("LWCPI $C7, ($2+)", "3721") + check_instruction("LWCPI $C15, ($12+)", "3fc1") + check_instruction("LWCPI $C1, ($3+)", "3131") + check_instruction("LWCPI $C10, ($4+)", "3a41") + + # Randomly choosen instructions + check_instruction("LWCPI $C0, ($1+)", "3011") + check_instruction("LWCPI $C0, ($11+)", "30b1") + check_instruction("LWCPI $C3, ($10+)", "33a1") + check_instruction("LWCPI $C0, ($5+)", "3051") + check_instruction("LWCPI $C2, ($3+)", "3231") + + def test_SMCPI(self): + """Test the SMCPI instruction""" + + # Top instructions + check_instruction("SMCPI $C10, ($SP+)", "3af2") + check_instruction("SMCPI $C14, ($7+)", "3e72") + check_instruction("SMCPI $C3, ($3+)", "3332") + check_instruction("SMCPI $C8, ($10+)", "38a2") + check_instruction("SMCPI $C0, ($3+)", "3032") + + # Randomly choosen instructions + check_instruction("SMCPI $C5, ($10+)", "35a2") + check_instruction("SMCPI $C9, ($3+)", "3932") + check_instruction("SMCPI $C11, ($5+)", "3b52") + check_instruction("SMCPI $C0, ($9+)", "3092") + check_instruction("SMCPI $C10, ($5+)", "3a52") + + def test_LMCPI(self): + """Test the LMCPI instruction""" + + # Top instructions + check_instruction("LMCPI $C2, ($3+)", "3233") + check_instruction("LMCPI $C0, ($3+)", "3033") + check_instruction("LMCPI $C10, ($7+)", "3a73") + check_instruction("LMCPI $C3, ($3+)", "3333") + check_instruction("LMCPI $C0, ($0+)", "3003") + + # Randomly choosen instructions + check_instruction("LMCPI $C0, ($SP+)", "30f3") + check_instruction("LMCPI $C1, ($1+)", "3113") + check_instruction("LMCPI $C3, ($0+)", "3303") + check_instruction("LMCPI $C3, ($2+)", "3323") + check_instruction("LMCPI $C13, ($9+)", "3d93") + + def test_SWCP(self): + """Test the SWCP instruction""" + + # Top instructions + check_instruction("SWCP $C1, ($4)", "3148") + check_instruction("SWCP $C13, ($1)", "3d18") + check_instruction("SWCP $C0, ($6)", "3068") + check_instruction("SWCP $C10, ($7)", "3a78") + check_instruction("SWCP $C0, ($10)", "30a8") + + # Randomly choosen instructions + check_instruction("SWCP $C7, ($12)", "37c8") + check_instruction("SWCP $C1, ($1)", "3118") + check_instruction("SWCP $C10, ($5)", "3a58") + check_instruction("SWCP $C8, ($11)", "38b8") + check_instruction("SWCP $C11, ($3)", "3b38") + + def test_LWCP(self): + """Test the LWCP instruction""" + + # Top instructions + check_instruction("LWCP $C14, ($7)", "3e79") + check_instruction("LWCP $C2, ($3)", "3239") + check_instruction("LWCP $C14, ($5)", "3e59") + check_instruction("LWCP $C6, ($10)", "36a9") + check_instruction("LWCP $C6, ($TP)", "36d9") + + # Randomly choosen instructions + check_instruction("LWCP $C11, ($9)", "3b99") + check_instruction("LWCP $C1, ($1)", "3119") + check_instruction("LWCP $C7, ($3)", "3739") + check_instruction("LWCP $C2, ($4)", "3249") + check_instruction("LWCP $C2, ($6)", "3269") + + def test_SMCP(self): + """Test the SMCP instruction""" + + # Top instructions + check_instruction("SMCP $C14, ($11)", "3eba") + check_instruction("SMCP $C12, ($GP)", "3cea") + check_instruction("SMCP $C4, ($GP)", "34ea") + check_instruction("SMCP $C0, ($GP)", "30ea") + check_instruction("SMCP $C12, ($0)", "3c0a") + + # Randomly choosen instructions + check_instruction("SMCP $C3, ($4)", "334a") + check_instruction("SMCP $C13, ($0)", "3d0a") + check_instruction("SMCP $C3, ($3)", "333a") + check_instruction("SMCP $C15, ($1)", "3f1a") + check_instruction("SMCP $C13, ($SP)", "3dfa") + + def test_LMCP(self): + """Test the LMCP instruction""" + + # Top instructions + check_instruction("LMCP $C14, ($6)", "3e6b") + check_instruction("LMCP $C14, ($4)", "3e4b") + check_instruction("LMCP $C5, ($6)", "356b") + check_instruction("LMCP $C9, ($4)", "394b") + check_instruction("LMCP $C15, ($6)", "3f6b") + + # Randomly choosen instructions + check_instruction("LMCP $C0, ($4)", "304b") + check_instruction("LMCP $C0, ($GP)", "30eb") + check_instruction("LMCP $C13, ($6)", "3d6b") + check_instruction("LMCP $C11, ($6)", "3b6b") + check_instruction("LMCP $C0, ($SP)", "30fb") diff --git a/test/arch/mep/asm/test_major_opcode_4.py b/test/arch/mep/asm/test_major_opcode_4.py new file mode 100644 index 00000000..c5de257e --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_4.py @@ -0,0 +1,118 @@ +# Toshiba MeP-c4 - Major Opcode #4 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor4: + + def test_ADD3(self): + """Test the ADD3 instruction""" + + # Top instructions + check_instruction("ADD3 $2, $SP, 0x20", "4220", multi=2) + check_instruction("ADD3 $1, $SP, 0x14", "4114", multi=2) + check_instruction("ADD3 $SP, $SP, 0x2C", "4f2c", multi=2) + check_instruction("ADD3 $1, $SP, 0x20", "4120", multi=2) + check_instruction("ADD3 $SP, $SP, 0x24", "4f24", multi=2) + check_instruction("ADD3 $2, $SP, 0x4", "4204", multi=2) + check_instruction("ADD3 $2, $SP, 0x8", "4208", multi=2) + check_instruction("ADD3 $1, $SP, 0x8", "4108", multi=2) + check_instruction("ADD3 $SP, $SP, 0x20", "4f20", multi=2) + check_instruction("ADD3 $1, $SP, 0x4", "4104", multi=2) + + # Randomly choosen instructions + check_instruction("ADD3 $11, $SP, 0x38", "4b38", multi=2) + check_instruction("ADD3 $5, $SP, 0x30", "4530", multi=2) + check_instruction("ADD3 $TP, $SP, 0x38", "4d38", multi=2) + check_instruction("ADD3 $4, $SP, 0x70", "4470", multi=2) + check_instruction("ADD3 $SP, $SP, 0xC", "4f0c", multi=2) + check_instruction("ADD3 $10, $SP, 0x10", "4a10", multi=2) + check_instruction("ADD3 $6, $SP, 0x7C", "467c", multi=2) + check_instruction("ADD3 $11, $SP, 0x14", "4b14", multi=2) + check_instruction("ADD3 $7, $SP, 0x3C", "473c", multi=2) + check_instruction("ADD3 $SP, $SP, 0x48", "4f48", multi=2) + + def test_SW(self): + """Test the SW instruction""" + + # Top instructions + check_instruction("SW $6, 0x4($SP)", "4606", multi=2) + check_instruction("SW $0, 0x4($SP)", "4006", multi=2) + check_instruction("SW $8, 0x10($SP)", "4812", multi=2) + check_instruction("SW $7, 0x8($SP)", "470a", multi=2) + check_instruction("SW $8, 0x8($SP)", "480a", multi=2) + check_instruction("SW $7, 0x4($SP)", "4706", multi=2) + check_instruction("SW $8, 0xC($SP)", "480e", multi=2) + check_instruction("SW $TP, 0x4($SP)", "4d06", multi=2) + check_instruction("SW $8, 0x4($SP)", "4806", multi=2) + check_instruction("SW $4, 0x40($SP)", "4442", multi=2) + + # Randomly choosen instructions + check_instruction("SW $4, 0x30($SP)", "4432", multi=2) + check_instruction("SW $9, 0x3C($SP)", "493e", multi=2) + check_instruction("SW $6, 0x68($SP)", "466a", multi=2) + check_instruction("SW $0, 0x40($TP)", "40c2", multi=2) + check_instruction("SW $9, 0x68($SP)", "496a", multi=2) + check_instruction("SW $4, 0x4($SP)", "4406", multi=2) + check_instruction("SW $2, 0x18($SP)", "421a", multi=2) + check_instruction("SW $10, 0x60($SP)", "4a62", multi=2) + check_instruction("SW $GP, 0x14($SP)", "4e16", multi=2) + check_instruction("SW $1, 0x20($SP)", "4122", multi=2) + + def test_LW(self): + """Test the LW instruction""" + + # Top instructions + check_instruction("LW $1, 0x8($SP)", "410b", multi=2) + check_instruction("LW $6, 0x4($SP)", "4607", multi=2) + check_instruction("LW $8, 0x10($SP)", "4813", multi=2) + check_instruction("LW $1, 0x4($SP)", "4107", multi=2) + check_instruction("LW $7, 0x8($SP)", "470b", multi=2) + check_instruction("LW $8, 0x8($SP)", "480b", multi=2) + check_instruction("LW $7, 0x4($SP)", "4707", multi=2) + check_instruction("LW $8, 0xC($SP)", "480f", multi=2) + check_instruction("LW $TP, 0x4($SP)", "4d07", multi=2) + check_instruction("LW $8, 0x4($SP)", "4807", multi=2) + + # Randomly choosen instructions + check_instruction("LW $9, 0x4C($SP)", "494f", multi=2) + check_instruction("LW $2, 0x44($TP)", "42c7", multi=2) + check_instruction("LW $6, 0x58($SP)", "465b", multi=2) + check_instruction("LW $SP, 0x74($SP)", "4f77", multi=2) + check_instruction("LW $4, 0x68($TP)", "44eb", multi=2) + check_instruction("LW $3, 0x34($TP)", "43b7", multi=2) + check_instruction("LW $6, 0x28($SP)", "462b", multi=2) + check_instruction("LW $1, 0x68($TP)", "41eb", multi=2) + check_instruction("LW $9, 0x28($SP)", "492b", multi=2) + check_instruction("LW $12, 0x30($SP)", "4c33", multi=2) + + def test_LBU(self): + """Test the LBU instruction""" + + # Top instructions + check_instruction("LBU $1, 0x3F($TP)", "49bf", multi=2) + check_instruction("LBU $2, 0x3F($TP)", "4abf", multi=2) + check_instruction("LBU $4, 0x3F($TP)", "4cbf", multi=2) + check_instruction("LBU $4, 0x9($TP)", "4c89", multi=2) + check_instruction("LBU $4, 0x25($TP)", "4ca5", multi=2) + check_instruction("LBU $4, 0xA($TP)", "4c8a", multi=2) + check_instruction("LBU $4, 0x2($TP)", "4c82", multi=2) + check_instruction("LBU $4, 0x1($TP)", "4c81", multi=2) + check_instruction("LBU $4, 0x5($TP)", "4c85", multi=2) + check_instruction("LBU $4, 0x6($TP)", "4c86", multi=2) + + # Randomly choosen instructions + check_instruction("LBU $4, 0x21($TP)", "4ca1", multi=2) + check_instruction("LBU $4, 0x22($TP)", "4ca2", multi=2) + # Note: the following instruction can not be easily manipulated due to + # expressions simplifications performed by miasm at assembly and + # dissassembly, i.e. ExprMem($TP + 0) is simplified into ExprMem($TP) + #check_instruction("LBU $6, 0x0($TP)", "4e80", multi=2) + check_instruction("LBU $7, 0x3C($TP)", "4fbc", multi=2) + check_instruction("LBU $2, 0x4($TP)", "4a84", multi=2) + check_instruction("LBU $7, 0x57($TP)", "4fd7", multi=2) + check_instruction("LBU $3, 0x66($TP)", "4be6", multi=2) + check_instruction("LBU $4, 0x31($TP)", "4cb1", multi=2) + check_instruction("LBU $6, 0x59($TP)", "4ed9", multi=2) + check_instruction("LBU $5, 0x66($TP)", "4de6", multi=2) diff --git a/test/arch/mep/asm/test_major_opcode_5.py b/test/arch/mep/asm/test_major_opcode_5.py new file mode 100644 index 00000000..dc984420 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_5.py @@ -0,0 +1,24 @@ +# Toshiba MeP-c4 - Major Opcode #5 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor5: + + def test_MOV(self): + """Test the MOV instruction""" + + # Top instructions + check_instruction("MOV $2, 0", "5200", multi=2) + check_instruction("MOV $12, 0", "5c00", multi=2) + check_instruction("MOV $4, 0", "5400", multi=2) + check_instruction("MOV $0, 0", "5000", multi=2) + check_instruction("MOV $0, 3", "5003", multi=2) + + # Randomly choosen instructions + check_instruction("MOV $8, 84", "5854", multi=2) + check_instruction("MOV $SP, 108", "5f6c", multi=2) + check_instruction("MOV $12, 80", "5c50", multi=2) + check_instruction("MOV $TP, 59", "5d3b", multi=2) + check_instruction("MOV $9, 89", "5959", multi=2) diff --git a/test/arch/mep/asm/test_major_opcode_6.py b/test/arch/mep/asm/test_major_opcode_6.py new file mode 100644 index 00000000..be7858b5 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_6.py @@ -0,0 +1,126 @@ +# Toshiba MeP-c4 - Major Opcode #6 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor6: + + def test_ADD(self): + """Test the ADD instruction""" + + # Top instructions + check_instruction("ADD $SP, 12", "6f30") + check_instruction("ADD $SP, -12", "6fd0") + check_instruction("ADD $SP, 8", "6f20") + check_instruction("ADD $SP, -8", "6fe0") + check_instruction("ADD $4, 1", "6404") + + # Randomly choosen instructions + check_instruction("ADD $2, -26", "6298") + check_instruction("ADD $TP, 7", "6d1c") + check_instruction("ADD $SP, 26", "6f68") + check_instruction("ADD $8, -9", "68dc") + check_instruction("ADD $6, 16", "6640") + + def test_SLT3(self): + """Test the SLT3 instruction""" + + # Top instructions + check_instruction("SLT3 $0, $4, 0xC", "6461", multi=2) + check_instruction("SLT3 $0, $9, 0xC", "6961", multi=2) + check_instruction("SLT3 $0, $12, 0xC", "6c61", multi=2) + check_instruction("SLT3 $0, $GP, 0xC", "6e61", multi=2) + check_instruction("SLT3 $0, $GP, 0xD", "6e69", multi=2) + + # Randomly choosen instructions + check_instruction("SLT3 $0, $8, 0x14", "68a1", multi=2) + check_instruction("SLT3 $0, $6, 0x0", "6601", multi=2) + check_instruction("SLT3 $0, $2, 0xB", "6259", multi=2) + check_instruction("SLT3 $0, $SP, 0x15", "6fa9", multi=2) + check_instruction("SLT3 $0, $7, 0x14", "67a1", multi=2) + + def test_SRL(self): + """Test the SRL instruction""" + + # Top instructions + check_instruction("SRL $SP, 0xE", "6f72") + check_instruction("SRL $12, 0x4", "6c22") + check_instruction("SRL $12, 0x8", "6c42") + check_instruction("SRL $12, 0x2", "6c12") + check_instruction("SRL $5, 0xE", "6572") + + # Randomly choosen instructions + check_instruction("SRL $3, 0x16", "63b2") + check_instruction("SRL $0, 0x1F", "60fa") + check_instruction("SRL $5, 0xF", "657a") + check_instruction("SRL $6, 0xE", "6672") + check_instruction("SRL $6, 0x1B", "66da") + + def test_SRA(self): + """Test the SRA instruction""" + + # Top instructions + check_instruction("SRA $1, 0xC", "6163") + check_instruction("SRA $SP, 0xC", "6f63") + check_instruction("SRA $5, 0xE", "6573") + check_instruction("SRA $4, 0x1", "640b") + check_instruction("SRA $12, 0x8", "6c43") + + # Randomly choosen instructions + check_instruction("SRA $0, 0x1B", "60db") + check_instruction("SRA $10, 0x17", "6abb") + check_instruction("SRA $GP, 0xB", "6e5b") + check_instruction("SRA $SP, 0x17", "6fbb") + check_instruction("SRA $7, 0x17", "67bb") + + def test_SLTU3(self): + """Test the SLTU3 instruction""" + + # Top instructions + check_instruction("SLTU3 $0, $0, 0x1", "600d", multi=2) + check_instruction("SLTU3 $0, $5, 0xD", "656d", multi=2) + check_instruction("SLTU3 $0, $12, 0x1", "6c0d", multi=2) + check_instruction("SLTU3 $0, $GP, 0xC", "6e65", multi=2) + check_instruction("SLTU3 $0, $4, 0x4", "6425", multi=2) + + # Randomly choosen instructions + check_instruction("SLTU3 $0, $9, 0x9", "694d", multi=2) + check_instruction("SLTU3 $0, $TP, 0xF", "6d7d", multi=2) + check_instruction("SLTU3 $0, $10, 0x1D", "6aed", multi=2) + check_instruction("SLTU3 $0, $6, 0x10", "6685", multi=2) + check_instruction("SLTU3 $0, $10, 0x1C", "6ae5", multi=2) + + def test_SLL(self): + """Test the SLL instruction""" + + # Top instructions + check_instruction("SLL $6, 0xC", "6666") + check_instruction("SLL $SP, 0xD", "6f6e") + check_instruction("SLL $0, 0x5", "602e") + check_instruction("SLL $0, 0x2", "6016") + check_instruction("SLL $0, 0x3", "601e") + + # Randomly choosen instructions + check_instruction("SLL $8, 0x16", "68b6") + check_instruction("SLL $SP, 0x4", "6f26") + check_instruction("SLL $4, 0x19", "64ce") + check_instruction("SLL $12, 0xA", "6c56") + check_instruction("SLL $12, 0x17", "6cbe") + + def test_SLL3(self): + """Test the SLL3 instruction""" + + # Top instructions + check_instruction("SLL3 $0, $4, 0x5", "642f") + check_instruction("SLL3 $0, $4, 0x3", "641f") + check_instruction("SLL3 $0, $10, 0x8", "6a47") + check_instruction("SLL3 $0, $GP, 0xD", "6e6f") + check_instruction("SLL3 $0, $1, 0x3", "611f") + + # Randomly choosen instructions + check_instruction("SLL3 $0, $11, 0x16", "6bb7") + check_instruction("SLL3 $0, $TP, 0xD", "6d6f") + check_instruction("SLL3 $0, $10, 0xB", "6a5f") + check_instruction("SLL3 $0, $7, 0x6", "6737") + check_instruction("SLL3 $0, $2, 0xF", "627f") diff --git a/test/arch/mep/asm/test_major_opcode_7.py b/test/arch/mep/asm/test_major_opcode_7.py new file mode 100644 index 00000000..fcd5e1f9 --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_7.py @@ -0,0 +1,133 @@ +# Toshiba MeP-c4 - Major Opcode #7 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor7: + + def test_DI(self): + """Test the DI instruction""" + + # Top instructions + check_instruction("DI", "7000") + + def test_EI(self): + """Test the EI instruction""" + + # Top instructions + check_instruction("EI", "7010") + + def test_SYNCM(self): + """Test the SYNCM instruction""" + + # Top instructions + check_instruction("SYNCM", "7011") + + def test_SYNCCP(self): + """Test the SYNCCP instruction""" + + # Top instructions + check_instruction("SYNCCP", "7021") + + def test_RET(self): + """Test the RET instruction""" + + # Top instructions + check_instruction("RET", "7002") + + def test_RETI(self): + """Test the RETI instruction""" + + # Top instructions + check_instruction("RETI", "7012") + + def test_HALT(self): + """Test the HALT instruction""" + + # Top instructions + check_instruction("HALT", "7022") + + def test_BREAK(self): + """Test the BREAK instruction""" + + # Top instructions + check_instruction("BREAK", "7032") + + def test_SLEEP(self): + """Test the SLEEP instruction""" + + # Top instructions + check_instruction("SLEEP", "7062") + + def test_DRET(self): + """Test the DRET instruction""" + + # Top instructions + check_instruction("DRET", "7013") + + def test_DBREAK(self): + """Test the DBREAK instruction""" + + # Top instructions + check_instruction("DBREAK", "7033") + + def test_CACHE(self): + """Test the CACHE instruction""" + + # Top instructions + check_instruction("CACHE 0x0, ($11)", "70b4") + check_instruction("CACHE 0x2, ($7)", "7274") + check_instruction("CACHE 0x4, ($7)", "7474") + check_instruction("CACHE 0x9, ($7)", "7974") + check_instruction("CACHE 0x2, ($6)", "7264") + + # Randomly choosen instructions + check_instruction("CACHE 0x5, ($8)", "7584") + check_instruction("CACHE 0xC, ($6)", "7c64") + check_instruction("CACHE 0x2, ($1)", "7214") + check_instruction("CACHE 0x3, ($1)", "7314") + check_instruction("CACHE 0x1, ($8)", "7184") + + def test_SWI(self): + """Test the SWI instruction""" + + # Top instructions + check_instruction("SWI 0x0", "7006") + check_instruction("SWI 0x2", "7026") + check_instruction("SWI 0x1", "7016") + check_instruction("SWI 0x3", "7036") + + def test_STC(self): + """Test the STC instruction""" + + # Top instructions + check_instruction("STC $4, $S22", "7469") # the documentation & objsdump disagree + check_instruction("STC $3, $S22", "7369") # the documentation & objsdump disagree + check_instruction("STC $1, $CFG", "7159") + check_instruction("STC $8, $LO", "7888") + check_instruction("STC $0, $LP", "7018") + + # Randomly choosen instructions + check_instruction("STC $9, $DBG", "7989") + check_instruction("STC $2, $DBG", "7289") + check_instruction("STC $9, $LO", "7988") + check_instruction("STC $11, $DEPC", "7b99") + check_instruction("STC $1, $S29", "71d9") + + def test_LDC(self): + """Test the LDC instruction""" + + # Top instructions + check_instruction("LDC $1, $CFG", "715b") + check_instruction("LDC $9, $HI", "797a") + check_instruction("LDC $11, $LO", "7b8a") + check_instruction("LDC $12, $LO", "7c8a") + check_instruction("LDC $0, $LP", "701a") + + # Randomly choosen instructions + check_instruction("LDC $11, $RPC", "7b6a") + check_instruction("LDC $10, $CFG", "7a5b") + check_instruction("LDC $2, $NPC", "727b") + check_instruction("LDC $6, $MB1", "76ea") + check_instruction("LDC $TP, $RPC", "7d6a") diff --git a/test/arch/mep/asm/test_major_opcode_8.py b/test/arch/mep/asm/test_major_opcode_8.py new file mode 100644 index 00000000..c4a8505f --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_8.py @@ -0,0 +1,92 @@ +# Toshiba MeP-c4 - Major Opcode #8 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor8: + + def test_SB(self): + """Test the SB instruction""" + + # Top instructions + check_instruction("SB $4, 0x2($TP)", "8402", multi=2) + check_instruction("SB $4, 0x4B($TP)", "844b", multi=2) + check_instruction("SB $4, 0x3($TP)", "8403", multi=2) + check_instruction("SB $4, 0x1($TP)", "8401", multi=2) + check_instruction("SB $0, 0x3($TP)", "8003", multi=2) + + # Randomly choosen instructions + check_instruction("SB $2, 0x65($TP)", "8265", multi=2) + check_instruction("SB $5, 0x48($TP)", "8548", multi=2) + check_instruction("SB $7, 0x77($TP)", "8777", multi=2) + check_instruction("SB $1, 0x49($TP)", "8149", multi=2) + check_instruction("SB $4, 0x20($TP)", "8420", multi=2) + + def test_SH(self): + """Test the SH instruction""" + + # Top instructions + check_instruction("SH $0, 0x18($TP)", "8098", multi=2) + check_instruction("SH $4, 0x10($TP)", "8490", multi=2) + check_instruction("SH $4, 0xE($TP)", "848e", multi=2) + check_instruction("SH $4, 0x4($TP)", "8484", multi=2) + check_instruction("SH $4, 0xC($TP)", "848c", multi=2) + + # Randomly choosen instructions + check_instruction("SH $7, 0x3A($TP)", "87ba", multi=2) + check_instruction("SH $2, 0x36($TP)", "82b6", multi=2) + check_instruction("SH $1, 0x76($TP)", "81f6", multi=2) + check_instruction("SH $7, 0x74($TP)", "87f4", multi=2) + check_instruction("SH $7, 0x7E($TP)", "87fe", multi=2) + + def test_LB(self): + """Test the LB instruction""" + + # Top instructions + check_instruction("LB $4, 0x1($TP)", "8c01", multi=2) + check_instruction("LB $4, 0x27($TP)", "8c27", multi=2) + check_instruction("LB $4, 0x4($TP)", "8c04", multi=2) + check_instruction("LB $4, 0x1A($TP)", "8c1a", multi=2) + check_instruction("LB $4, 0x6($TP)", "8c06", multi=2) + + # Randomly choosen instructions + check_instruction("LB $4, 0x59($TP)", "8c59", multi=2) + check_instruction("LB $7, 0x53($TP)", "8f53", multi=2) + check_instruction("LB $6, 0x62($TP)", "8e62", multi=2) + check_instruction("LB $6, 0x53($TP)", "8e53", multi=2) + check_instruction("LB $0, 0x34($TP)", "8834", multi=2) + + def test_LH(self): + """Test the LH instruction""" + + # Top instructions + check_instruction("LH $4, 0x18($TP)", "8c98", multi=2) + check_instruction("LH $4, 0x10($TP)", "8c90", multi=2) + check_instruction("LH $4, 0x28($TP)", "8ca8", multi=2) + check_instruction("LH $4, 0x6($TP)", "8c86", multi=2) + check_instruction("LH $4, 0x4($TP)", "8c84", multi=2) + + # Randomly choosen instructions + check_instruction("LH $7, 0x28($TP)", "8fa8", multi=2) + check_instruction("LH $4, 0x16($TP)", "8c96", multi=2) + check_instruction("LH $0, 0x56($TP)", "88d6", multi=2) + check_instruction("LH $4, 0x40($TP)", "8cc0", multi=2) + check_instruction("LH $7, 0x2A($TP)", "8faa", multi=2) + + def test_LHU(self): + """Test the LHU instruction""" + + # Top instructions + check_instruction("LHU $4, 0x4($TP)", "8c85", multi=2) + check_instruction("LHU $4, 0x28($TP)", "8ca9", multi=2) + check_instruction("LHU $4, 0xC($TP)", "8c8d", multi=2) + check_instruction("LHU $4, 0x10($TP)", "8c91", multi=2) + check_instruction("LHU $3, 0xC($TP)", "8b8d", multi=2) + + # Randomly choosen instructions + check_instruction("LHU $3, 0x54($TP)", "8bd5", multi=2) + check_instruction("LHU $7, 0x66($TP)", "8fe7", multi=2) + check_instruction("LHU $2, 0x6E($TP)", "8aef", multi=2) + check_instruction("LHU $2, 0x36($TP)", "8ab7", multi=2) + check_instruction("LHU $3, 0x78($TP)", "8bf9", multi=2) diff --git a/test/arch/mep/asm/test_major_opcode_9.py b/test/arch/mep/asm/test_major_opcode_9.py new file mode 100644 index 00000000..822f3b6a --- /dev/null +++ b/test/arch/mep/asm/test_major_opcode_9.py @@ -0,0 +1,24 @@ +# Toshiba MeP-c4 - Major Opcode #9 unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_asm import check_instruction + + +class TestMajor9: + + def test_ADD3(self): + """Test the ADD3 instruction""" + + # Top instructions + check_instruction("ADD3 $10, $4, $0", "940a") + check_instruction("ADD3 $3, $0, $0", "9003") + check_instruction("ADD3 $12, $4, $0", "940c") + check_instruction("ADD3 $7, $12, $0", "9c07") + check_instruction("ADD3 $TP, $4, $0", "940d") + + # Randomly choosen instructions + check_instruction("ADD3 $4, $1, $9", "9194") + check_instruction("ADD3 $7, $12, $9", "9c97") + check_instruction("ADD3 $12, $9, $SP", "99fc") + check_instruction("ADD3 $12, $TP, $7", "9d7c") + check_instruction("ADD3 $4, $8, $SP", "98f4") diff --git a/test/arch/mep/asm/ut_helpers_asm.py b/test/arch/mep/asm/ut_helpers_asm.py new file mode 100644 index 00000000..af010afc --- /dev/null +++ b/test/arch/mep/asm/ut_helpers_asm.py @@ -0,0 +1,92 @@ +# Toshiba MeP-c4 - unit tests helpers +# Guillaume Valadon <guillaume@valadon.net> + +from miasm2.arch.mep.arch import mn_mep +from miasm2.core.cpu import Disasm_Exception +from miasm2.core.locationdb import LocationDB +from miasm2.expression.expression import ExprId, ExprInt, ExprLoc + +import re + + +def dis(mn_hex): + """Disassembly helper""" + mn_bin = mn_hex.decode("hex") + try: + return mn_mep.dis(mn_bin, "b") + except Disasm_Exception: + assert(False) # miasm don't know what to do + + +def check_instruction(mn_str, mn_hex, multi=None, offset=0): + """Try to disassemble and assemble this instruction""" + + # Rename objdump registers names + mn_str = re.sub("\$([0-9]+)", lambda m: "R"+m.group(1), mn_str) + mn_str = mn_str.replace("$", "") + + # Disassemble + mn = dis(mn_hex) + mn.offset = offset + if mn.dstflow(): + + # Remember ExprInt arguments sizes + args_size = list() + for i in range(len(mn.args)): + if isinstance(mn.args[i], ExprInt): + args_size.append(mn.args[i].size) + else: + args_size.append(None) + + # Adjust arguments values using the instruction offset + loc_db = LocationDB() + mn.dstflow2label(loc_db) + + # Convert ExprLoc to ExprInt + for i in range(len(mn.args)): + if args_size[i] is None: + continue + if isinstance(mn.args[i], ExprLoc): + addr = loc_db.get_location_offset(mn.args[i].loc_key) + mn.args[i] = ExprInt(addr, args_size[i]) + + print "dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20)) + assert(str(mn) == mn_str) # disassemble assertion + + # Assemble and return all possible candidates + instr = mn_mep.fromstring(mn_str, "b") + instr.offset = offset + instr.mode = "b" + if instr.offset: + instr.fixDstOffset() + asm_list = [i.encode("hex") for i in mn_mep.asm(instr)] + + # Check instructions variants + if multi: + print "Instructions count:", len(asm_list) + assert(len(asm_list) == multi) + + # Ensure that variants correspond to the same disassembled instruction + for mn_hex in asm_list: + mn = dis(mn_hex) + print "dis: %s -> %s" % (mn_hex.rjust(20), str(mn).rjust(20)) + + # Check the assembly result + print "asm: %s -> %s" % (mn_str.rjust(20), + ", ".join(asm_list).rjust(20)) + assert(mn_hex in asm_list) # assemble assertion + + +def launch_tests(obj): + """Call test methods by name""" + + test_methods = [name for name in dir(obj) if name.startswith("test")] + + for method in test_methods: + print method + try: + getattr(obj, method)() + except AttributeError as e: + print "Method not found: %s" % method + assert(False) + print '-' * 42 diff --git a/test/arch/mep/ir/launch.py b/test/arch/mep/ir/launch.py new file mode 100644 index 00000000..44a8db52 --- /dev/null +++ b/test/arch/mep/ir/launch.py @@ -0,0 +1,22 @@ +# Toshiba MeP-c4 - pytest unit tests wrapper +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import launch_tests + +from test_arithmetic import TestArithmetic; launch_tests(TestArithmetic()) +from test_bitmanipulation import TestBitManipulation; launch_tests(TestBitManipulation()) +from test_branchjump import TestBranchJump; launch_tests(TestBranchJump()) +from test_control import TestControl; launch_tests(TestControl()) +from test_coprocessor import TestCoprocessor; launch_tests(TestCoprocessor()) +from test_datacache import TestDataCache; launch_tests(TestDataCache()) +from test_debug import TestDebug; launch_tests(TestDebug()) +from test_divide import TestDivide; launch_tests(TestDivide()) +from test_extension import TestExtension; launch_tests(TestExtension()) +from test_ldz import TestLdz; launch_tests(TestLdz()) +from test_loadstore import TestLoadStore; launch_tests(TestLoadStore()) +from test_logical import TestLogical; launch_tests(TestLogical()) +from test_move import TestMove; launch_tests(TestMove()) +from test_multiply import TestMultiply; launch_tests(TestMultiply()) +from test_repeat import TestRepeat; launch_tests(TestRepeat()) +from test_shift import TestShift; launch_tests(TestShift()) +from test_ir import TestMisc; launch_tests(TestMisc()) diff --git a/test/arch/mep/ir/test_arithmetic.py b/test/arch/mep/ir/test_arithmetic.py new file mode 100644 index 00000000..6da938e9 --- /dev/null +++ b/test/arch/mep/ir/test_arithmetic.py @@ -0,0 +1,185 @@ +# Toshiba MeP-c4 - Arithmetic instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp + + +class TestArithmetic: + + def test_add3(self): + """Test ADD3 execution""" + + # ADD3 Rl,Rn,Rm + exec_instruction("ADD3 R1, R2, R3", + [(ExprId("R2", 32), ExprInt(0x40, 32)), (ExprId("R3", 32), ExprInt(0x2, 32))], + [(ExprId("R1", 32), ExprInt(0x42, 32))]) + + # ADD3 Rn,SP,imm7.align4 + exec_instruction("ADD3 R1, SP, 0x8", + [(ExprId("SP", 32), ExprInt(0x20, 32))], + [(ExprId("R1", 32), ExprInt(0x28, 32))]) + + # ADD3 Rn,Rm,imm16 + exec_instruction("ADD3 R7, R5, -31912", + [(ExprId("R5", 32), ExprInt(0x20, 32))], + [(ExprId("R7", 32), ExprInt(-31880, 32))]) + + def test_add(self): + """Test ADD execution""" + + # ADD Rn,imm6 + exec_instruction("ADD R1, 0x10", + [(ExprId("R1", 32), ExprInt(0x32, 32))], + [(ExprId("R1", 32), ExprInt(0x42, 32))]) + + exec_instruction("ADD R1, -5", + [(ExprId("R1", 32), ExprInt(0x32, 32))], + [(ExprId("R1", 32), ExprInt(45, 32))]) + + exec_instruction("ADD R1, -16", + [(ExprId("R1", 32), ExprInt(0xFFFF, 32))], + [(ExprId("R1", 32), ExprInt(0xFFEF, 32))]) + + exec_instruction("ADD R1, -28", + [(ExprId("R1", 32), ExprInt(0, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFE4, 32))]) + + def test_advck3(self): + """Test ADVCK3 execution""" + + # ADVCK3 R0,Rn,Rm + exec_instruction("ADVCK3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(1, 32)), + (ExprId("R2", 32), ExprInt(2, 32))], + [(ExprId("R0", 32), ExprInt(0, 32))]) + + exec_instruction("ADVCK3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(1, 32)), + (ExprId("R2", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + def test_sub(self): + """Test SUB execution""" + + # SUB Rn,Rm + exec_instruction("SUB R1, R2", + [(ExprId("R1", 32), ExprInt(0x28, 32)), + (ExprId("R2", 32), ExprInt(0x7, 32))], + [(ExprId("R1", 32), ExprInt(0x21, 32))]) + + def test_sbvck3(self): + """Test SBVCK3 execution""" + + # SBVCK3 R0,Rn,Rm + exec_instruction("SBVCK3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(2, 32)), + (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R0", 32), ExprCond(ExprOp(">", + ExprInt(3, 32), + ExprCond(ExprOp(">", ExprInt(0x2, 32), ExprInt(0x1, 32)), + ExprInt(0x2, 32), + ExprInt(0x1, 32))), + ExprInt(1, 32), + ExprInt(0, 32)))]) + + exec_instruction("SBVCK3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(0, 32)), + (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R0", 32), ExprCond(ExprOp(">", + ExprInt(1, 32), + ExprCond(ExprOp(">", ExprInt(0, 32), ExprInt(1, 32)), + ExprInt(0, 32), + ExprInt(1, 32))), + ExprInt(1, 32), + ExprInt(0, 32)))]) + + def test_neg(self): + """Test NEG execution""" + + # NEG Rn,Rm + exec_instruction("NEG R1, R2", + [(ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))]) + + exec_instruction("NEG R1, R2", + [(ExprId("R2", 32), ExprInt(0x42, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFBE, 32))]) + + def test_slt3(self): + """Test SLT3 execution""" + + # SLT3 R0,Rn,Rm + exec_instruction("SLT3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(0x2, 32)), + (ExprId("R2", 32), ExprInt(0x1, 32))], + [(ExprId("R0", 32), ExprInt(0, 32))]) + + r1 = 0x80000000 + r2 = 0x80000001 + exec_instruction("SLT3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(r1, 32)), + (ExprId("R2", 32), ExprInt(r2, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + r1 = 0x80000000 + r2 = 0x00000001 + exec_instruction("SLT3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(r1, 32)), + (ExprId("R2", 32), ExprInt(r2, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + r1 = 0x00000001 + r2 = 0x80000000 + exec_instruction("SLT3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(r1, 32)), + (ExprId("R2", 32), ExprInt(r2, 32))], + [(ExprId("R0", 32), ExprInt(0, 32))]) + + # SLT3 R0,Rn,imm5 + exec_instruction("SLT3 R0, R1, 12", + [(ExprId("R1", 32), ExprInt(0x1, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + r1 = 0x80000000 + exec_instruction("SLT3 R0, R1, 12", + [(ExprId("R1", 32), ExprInt(0x80000000, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + def test_sltu3(self): + """Test SLTU3 execution""" + + # SLTU3 R0,Rn,Rm + exec_instruction("SLTU3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(0x1, 32)), + (ExprId("R2", 32), ExprInt(0x2, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + exec_instruction("SLTU3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(0x2, 32)), + (ExprId("R2", 32), ExprInt(0x1, 32))], + [(ExprId("R0", 32), ExprInt(0, 32))]) + + # SLTU3 R0,Rn,imm5 + exec_instruction("SLTU3 R0, R1, 12", + [(ExprId("R1", 32), ExprInt(0x1, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + def test_sl1ad3(self): + """Test SL2AD3 execution""" + + # SL1AD3 R0,Rn,Rm + exec_instruction("SL1AD3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(0x2, 32)), + (ExprId("R2", 32), ExprInt(0x20, 32))], + [(ExprId("R0", 32), ExprInt(0x24, 32))]) + + def test_sl2ad3(self): + """Test SL2AD3 execution""" + + # SL2AD3 R0,Rn,Rm + exec_instruction("SL2AD3 R0, R1, R2", + [(ExprId("R1", 32), ExprInt(0x2, 32)), + (ExprId("R2", 32), ExprInt(0x20, 32))], + [(ExprId("R0", 32), ExprInt(0x28, 32))]) diff --git a/test/arch/mep/ir/test_bitmanipulation.py b/test/arch/mep/ir/test_bitmanipulation.py new file mode 100644 index 00000000..06466f9d --- /dev/null +++ b/test/arch/mep/ir/test_bitmanipulation.py @@ -0,0 +1,55 @@ +# Toshiba MeP-c4 - Bit manipulation instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprMem + + +class TestBitManipulation: + + def test_bsetm(self): + """Test BSETM execution""" + + # BSETM (Rm),imm3 + exec_instruction("BSETM (R1), 1", + [(ExprId("R1", 32), ExprInt(0x28, 32)), + (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))], + [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x3, 8))]) + + def test_bclrm(self): + """Test BCLRM execution""" + + # BCLRM (Rm),imm3 + exec_instruction("BCLRM (R1), 1", + [(ExprId("R1", 32), ExprInt(0x28, 32)), + (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x3, 8))], + [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))]) + + def test_bnotm(self): + """Test BNOTM execution""" + + # BNOTM (Rm),imm3 + exec_instruction("BNOTM (R1), 1", + [(ExprId("R1", 32), ExprInt(0x28, 32)), + (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))], + [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x3, 8))]) + + def test_btstm(self): + """Test BTSTM execution""" + + # BTSTM R0,(Rm),imm3 + exec_instruction("BTSTM R0, (R1), 1", + [(ExprId("R1", 32), ExprInt(0x28, 32)), + (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x2, 8))], + [(ExprId("R0", 32), ExprInt(0x2, 32))]) + + def test_tas(self): + """Test TAS execution""" + + # TAS Rn,(Rm) + exec_instruction("TAS R0, (R1)", + [(ExprId("R1", 32), ExprInt(0x28, 32)), + (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x2, 8))], + [(ExprId("R0", 32), ExprInt(0x2, 32)), + (ExprMem(ExprInt(0x28, 32), 8), ExprInt(0x1, 8))]) diff --git a/test/arch/mep/ir/test_branchjump.py b/test/arch/mep/ir/test_branchjump.py new file mode 100644 index 00000000..48feb54d --- /dev/null +++ b/test/arch/mep/ir/test_branchjump.py @@ -0,0 +1,191 @@ +# Toshiba MeP-c4 - Branch/Jump instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprCond, ExprOp, ExprInt + + +class TestBranchJump: + + def test_bra(self): + """Test BRA execution""" + + # BRA disp12.align2 + exec_instruction("BRA 0x28", + [], + [(ExprId("PC", 32), ExprInt(0x28, 32))]) + + exec_instruction("BRA 0x800", + [], + [(ExprId("PC", 32), ExprInt(0xFFFFF800, 32))]) + + exec_instruction("BRA 0x28", + [], + [(ExprId("PC", 32), ExprInt(0x1028, 32))], offset=0x1000) + + def test_beqz(self): + """Test BEQZ execution""" + + # BEQZ Rn,disp8.align2 + exec_instruction("BEQZ R1, 0x10", + [(ExprId("R1", 32), ExprInt(0, 32))], + [(ExprId("PC", 32), ExprInt(0x20, 32))], offset=0x10) + + exec_instruction("BEQZ R1, 0x10", + [(ExprId("R1", 32), ExprInt(1, 32))], + [(ExprId("PC", 32), ExprInt(0x2, 32))]) + + exec_instruction("BEQZ R1, 0x80", + [(ExprId("R1", 32), ExprInt(0, 32))], + [(ExprId("PC", 32), ExprInt(0xFFFFFF90, 32))], offset=0x10) + + def test_bnez(self): + """Test BNEZ execution""" + + # BNEZ Rn,disp8.align2 + exec_instruction("BNEZ R1, 0x10", + [(ExprId("R1", 32), ExprInt(0, 32))], + [(ExprId("PC", 32), ExprInt(0x2, 32))]) + + exec_instruction("BNEZ R1, 0x10", + [(ExprId("R1", 32), ExprInt(1, 32))], + [(ExprId("PC", 32), ExprInt(0x20, 32))], offset=0x10) + + exec_instruction("BNEZ R1, 0x80", + [(ExprId("R1", 32), ExprInt(0, 32))], + [(ExprId("PC", 32), ExprInt(0x2, 32))]) + + def test_beqi(self): + """Test BEQI execution""" + + # BEQI Rn,imm4,disp17.align2 + exec_instruction("BEQI R1, 0x8, 0x28", + [(ExprId("R1", 32), ExprInt(0, 32))], + [(ExprId("PC", 32), ExprInt(0x4, 32))]) + + exec_instruction("BEQI R1, 0x1, 0x28", + [(ExprId("R1", 32), ExprInt(1, 32))], + [(ExprId("PC", 32), ExprInt(0x38, 32))], offset=0x10) + + exec_instruction("BEQI R1, 0x6, 0x10000", + [(ExprId("R1", 32), ExprInt(6, 32))], + [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))], offset=0x10) + + def test_bnei(self): + """Test BNEI execution""" + + # BNEI Rn,imm4,disp17.align2 + exec_instruction("BNEI R1, 0x5, 0x28", + [(ExprId("R1", 32), ExprInt(0, 32))], + [(ExprId("PC", 32), ExprInt(0x38, 32))], offset=0x10) + + exec_instruction("BNEI R1, 0x7, 0xFF00", + [(ExprId("R1", 32), ExprInt(7, 32)), + (ExprId("PC", 32), ExprInt(0x1, 32))], + [(ExprId("PC", 32), ExprInt(0x4, 32))]) + + def test_blti(self): + """Test BLTI execution""" + + # BLTI Rn,imm4,disp17.align2 + exec_instruction("BLTI R1, 0x5, 0x10000", + [(ExprId("R1", 32), ExprInt(0x10, 32))], + [(ExprId("PC", 32), ExprInt(0x14, 32))], + offset=0x10) + + exec_instruction("BLTI R1, 0x5, 0x10000", + [(ExprId("R1", 32), ExprInt(0x1, 32))], + [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))], + offset=0x10) + + def test_bgei(self): + """Test BGEI execution""" + + # BGEI Rn,imm4,disp17.align2 + exec_instruction("BGEI R1, 0x5, 0x10000", + [(ExprId("R1", 32), ExprInt(0x10, 32))], + [(ExprId("PC", 32), ExprCond(ExprOp(">=", ExprInt(0x10, 32), ExprInt(0x5, 32)), ExprInt(0xFFFF0010, 32), ExprInt(0x14, 32)))], + offset=0x10) + + def test_beq(self): + """Test BEQ execution""" + + # BEQ Rn,Rm,disp17.align2 + exec_instruction("BEQ R1, R2, 0x10000", + [(ExprId("R1", 32), ExprInt(0x10, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))], offset=0x10) + + exec_instruction("BEQ R1, R2, 0x8000", + [(ExprId("R1", 32), ExprInt(0x09, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprId("PC", 32), ExprInt(0x10, 32))], + [(ExprId("PC", 32), ExprInt(0x4, 32))]) + + def test_bne(self): + """Test BNE execution""" + + # BNE Rn,Rm,disp17.align2 + exec_instruction("BNE R1, R2, 0x8000", + [(ExprId("R1", 32), ExprInt(0x10, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprId("PC", 32), ExprInt(0x4, 32))]) + + exec_instruction("BNE R1, R2, 0x8000", + [(ExprId("R1", 32), ExprInt(0x09, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprId("PC", 32), ExprInt(0x8010, 32))], offset=0x10) + + exec_instruction("BNE R1, R2, 0x10000", + [(ExprId("R1", 32), ExprInt(0x09, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprId("PC", 32), ExprInt(0xFFFF0010, 32))], offset=0x10) + + def test_bsr(self): + """Test BSR execution""" + + # BSR disp12.align2 + exec_instruction("BSR 0x800", + [(ExprId("PC", 32), ExprInt(2, 32))], + [(ExprId("PC", 32), ExprInt(0xFFFFF800, 32)), + (ExprId("LP", 32), ExprInt(2, 32))], index=0) + + # BSR disp24.align2 + exec_instruction("BSR 0x101015", + [(ExprId("PC", 32), ExprInt(4, 32))], + [(ExprId("PC", 32), ExprInt(0x101014, 32)), + (ExprId("LP", 32), ExprInt(4, 32))], index=1) + + def test_jmp(self): + """Test JMP execution""" + + # JMP Rm + exec_instruction("JMP R1", + [(ExprId("R1", 32), ExprInt(0x101015, 32))], + [(ExprId("PC", 32), ExprInt(0x101015, 32))]) + + # JMP target24.align2 + exec_instruction("JMP 0x2807", + [(ExprId("PC", 32), ExprInt(0, 32))], + [(ExprId("PC", 32), ExprInt(0x2806, 32))], offset=0x42) + exec_instruction("JMP 0x2807", + [(ExprId("PC", 32), ExprInt(0xB0000000, 32))], + [(ExprId("PC", 32), ExprInt(0xB0002806, 32))], offset=0xB0000000) + + def test_jsr(self): + """Test JSR execution""" + + # JSR Rm + exec_instruction("JSR R1", + [(ExprId("R1", 32), ExprInt(0x2807, 32))], + [(ExprId("PC", 32), ExprInt(0x2807, 32)), + (ExprId("LP", 32), ExprInt(0x2, 32))]) + + def test_ret(self): + """Test RET execution""" + + # RET + exec_instruction("RET", + [(ExprId("LP", 32), ExprInt(0x28, 32))], + [(ExprId("PC", 32), ExprInt(0x28, 32))]) diff --git a/test/arch/mep/ir/test_control.py b/test/arch/mep/ir/test_control.py new file mode 100644 index 00000000..a1b3c7c7 --- /dev/null +++ b/test/arch/mep/ir/test_control.py @@ -0,0 +1,105 @@ +# Toshiba MeP-c4 - Control instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp + + +class TestControl: + + def test_stc(self): + """Test STC execution""" + + # STC Rn,imm5 + exec_instruction("STC R1, SAR", + [(ExprId("R1", 32), ExprInt(0x28, 32))], + [(ExprId("SAR", 32), ExprInt(0x28, 32))]) + + def test_ldc(self): + """Test LDC execution""" + + # LDC Rn,imm5 + exec_instruction("LDC R1, SAR", + [(ExprId("SAR", 32), ExprInt(0x28, 32))], + [(ExprId("R1", 32), ExprInt(0x28, 32))]) + + def test_di(self): + """Test DI execution""" + + # DI + exec_instruction("DI", + [(ExprId("PSW", 32), ExprInt(1, 32))], + [(ExprId("PSW", 32), ExprInt(0, 32))]) + + def test_ei(self): + """Test EI execution""" + + # EI + exec_instruction("EI", + [(ExprId("PSW", 32), ExprInt(0, 32))], + [(ExprId("PSW", 32), ExprInt(1, 32))]) + + def test_reti(self): + """Test RETI execution""" + + # RETI + exec_instruction("RETI", + [(ExprId("PSW", 32), ExprInt(0xF0000201, 32)), # PSW_NMI = 1 + (ExprId("NPC", 32), ExprInt(0x43, 32))], + [(ExprId("PSW", 32), ExprInt(0xF0000001, 32)), + (ExprId("PC", 32), ExprInt(0x42, 32))]) + + exec_instruction("RETI", + [(ExprId("PSW", 32), ExprInt(0b1010, 32)), # PSW_UMP = 1 & PSW_IEP = 1 + (ExprId("EPC", 32), ExprInt(0x29, 32))], + [(ExprId("PSW", 32), ExprInt(0b1111, 32)), # PSW_UMC = 1 & PSW_IEC = 1 + (ExprId("PC", 32), ExprInt(0x28, 32))]) + + def test_swi(self): + """Test SWI execution""" + + # SWI + exec_instruction("SWI 0", + [(ExprId("EXC", 32), ExprInt(0xF0000001, 32))], + [(ExprId("EXC", 32), ExprInt(0xF0000001 + (1 << 4), 32))]) + + exec_instruction("SWI 1", + [(ExprId("EXC", 32), ExprInt(0xF0000001, 32))], + [(ExprId("EXC", 32), ExprInt(0xF0000001 + (1 << 5), 32))]) + + def test_halt(self): + """Test HALT execution""" + + # HALT + exec_instruction("HALT", [], []) + + def test_sleep(self): + """Test SLEEP execution""" + + # SLEEP + exec_instruction("SLEEP", [], []) + + def test_break(self): + """Test BREAK execution""" + + # BREAK + exec_instruction("BREAK", [], []) + + def test_syncm(self): + """Test SYNCM execution""" + + # SYNCM + exec_instruction("SYNCM", [], []) + + def test_stcb(self): + """Test STCB execution""" + + # STCB Rn,abs16 + exec_instruction("STCB R0, 0x0", [], []) + + def test_ldcb(self): + """Test LDCB execution""" + + # LDCB Rn,abs16 + exec_instruction("LDCB R0, 0x0", [], []) diff --git a/test/arch/mep/ir/test_coprocessor.py b/test/arch/mep/ir/test_coprocessor.py new file mode 100644 index 00000000..e9b745ff --- /dev/null +++ b/test/arch/mep/ir/test_coprocessor.py @@ -0,0 +1,109 @@ +# Toshiba MeP-c4 - Coprocessor instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprMem, ExprInt + + +class TestCoprocessor: + + def test_swcp(self): + """Test SWCP execution""" + + # SWCP CRn,(Rm) + exec_instruction("SWCP C1, (R2)", + [(ExprId("C1", 32), ExprInt(0x28071010, 32)), + (ExprId("R2", 32), ExprInt(0x11, 32))], + [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32))]) + + # SWCP CRn,disp16(Rm) + exec_instruction("SWCP C10, 0xF800(R2)", + [(ExprId("C10", 32), ExprInt(0xABC7, 32)), + (ExprId("R2", 32), ExprInt(0x11, 32))], + [(ExprMem(ExprInt(0xFFFFF810, 32), 32), ExprInt(0xABC7, 32))]) + + def test_lwcp(self): + """Test LWCP execution""" + + # LWCP CRn[0-15],(Rm) + exec_instruction("LWCP C1, (R2)", + [(ExprId("R2", 32), ExprInt(0x11, 32)), + (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))], + [(ExprId("C1", 32), ExprInt(0xABCD, 32))]) + + # LWCP CRn[0-15],disp16(Rm) + exec_instruction("LWCP C9, 0xF000(R2)", + [(ExprId("R2", 32), ExprInt(0x42, 32)), + (ExprMem(ExprInt(0xFFFFF040, 32), 32), ExprInt(0x10, 32))], + [(ExprId("C9", 32), ExprInt(0x10, 32))]) + + def test_smcp(self): + """Test SMCP execution""" + + # SMCP CRn,(Rm) + exec_instruction("SMCP C1, (R2)", + [(ExprId("C1", 32), ExprInt(0x28071010, 32)), + (ExprId("R2", 32), ExprInt(0x17, 32))], + [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32))]) + + # SMCP CRn,disp16(Rm) + exec_instruction("SMCP C10, 0xF800(R2)", + [(ExprId("C10", 32), ExprInt(0xABC7, 32)), + (ExprId("R2", 32), ExprInt(0x17, 32))], + [(ExprMem(ExprInt(0xFFFFF810, 32), 32), ExprInt(0xABC7, 32))]) + + def test_lmcp(self): + """Test LMCP execution""" + + # LMCP CRn[0-15],(Rm) + exec_instruction("LMCP C1, (R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))], + [(ExprId("C1", 32), ExprInt(0xABCD, 32))]) + + # LMCP CRn[0-15],disp16(Rm) + exec_instruction("LMCP C9, 0xF000(R2)", + [(ExprId("R2", 32), ExprInt(0x17, 32)), + (ExprMem(ExprInt(0xFFFFF010, 32), 32), ExprInt(0x10, 32))], + [(ExprId("C9", 32), ExprInt(0x10, 32))]) + + def test_swcpi(self): + """Test SWCPI execution""" + + # SWCPI CRn[0-15],(Rm+) + exec_instruction("SWCPI C1, (R2+)", + [(ExprId("C1", 32), ExprInt(0x28071010, 32)), + (ExprId("R2", 32), ExprInt(0x11, 32))], + [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32)), + (ExprId("R2", 32), ExprInt(0x15, 32))]) + + def test_lwcpi(self): + """Test LWCPI execution""" + + # LWCPI CRn[0-15],(Rm+) + exec_instruction("LWCPI C1, (R2+)", + [(ExprId("R2", 32), ExprInt(0x11, 32)), + (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))], + [(ExprId("C1", 32), ExprInt(0xABCD, 32)), + (ExprId("R2", 32), ExprInt(0x15, 32))]) + + def test_smcpi(self): + """Test SMCPI execution""" + + # SMCPI CRn[0-15],(Rm+) + exec_instruction("SMCPI C1, (R2+)", + [(ExprId("C1", 32), ExprInt(0x28071010, 32)), + (ExprId("R2", 32), ExprInt(0x17, 32))], + [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32)), + (ExprId("R2", 32), ExprInt(0x1F, 32))]) + + def test_lmcpi(self): + """Test LMCPI execution""" + + # LMCPI CRn[0-15],(Rm+) + exec_instruction("LMCPI C1, (R2+)", + [(ExprId("R2", 32), ExprInt(0x11, 32)), + (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))], + [(ExprId("C1", 32), ExprInt(0xABCD, 32)), + (ExprId("R2", 32), ExprInt(0x19, 32))]) diff --git a/test/arch/mep/ir/test_datacache.py b/test/arch/mep/ir/test_datacache.py new file mode 100644 index 00000000..a462315d --- /dev/null +++ b/test/arch/mep/ir/test_datacache.py @@ -0,0 +1,13 @@ +# Toshiba MeP-c4 - Data cache instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + + +class TestDataCache: + + def test_cache(self): + """Test CACHE execution""" + + # CACHE imm4, (Rm) + exec_instruction("CACHE 0x0, (R0)", [], []) diff --git a/test/arch/mep/ir/test_debug.py b/test/arch/mep/ir/test_debug.py new file mode 100644 index 00000000..53f4064d --- /dev/null +++ b/test/arch/mep/ir/test_debug.py @@ -0,0 +1,33 @@ +# Toshiba MeP-c4 - Debug instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp + + +class TestDebug: + + def test_dret(self): + """Test DRET execution""" + + # DRET + exec_instruction("DRET", + [(ExprId("DEPC", 32), ExprInt(2, 32)), + (ExprId("DBG", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("PC", 32), ExprInt(2, 32)), + (ExprId("DBG", 32), ExprInt(0xFFFFBFFF, 32))]) + + exec_instruction("DRET", + [(ExprId("DEPC", 32), ExprInt(2, 32)), + (ExprId("DBG", 32), ExprInt(2**15, 32))], + [(ExprId("PC", 32), ExprInt(2, 32)), + (ExprId("DBG", 32), ExprInt(2**15, 32))]) + + def test_dbreak(self): + """Test DBREAK execution""" + + # DBREAK + exec_instruction("DBREAK", + [(ExprId("DBG", 32), ExprInt(0, 32))], + [(ExprId("DBG", 32), ExprInt(0b10, 32))]) diff --git a/test/arch/mep/ir/test_divide.py b/test/arch/mep/ir/test_divide.py new file mode 100644 index 00000000..04d5f6c5 --- /dev/null +++ b/test/arch/mep/ir/test_divide.py @@ -0,0 +1,99 @@ +# Toshiba MeP-c4 - Divide instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO + + +class TestDivide: + + def test_div(self): + """Test DIV execution""" + + # DIV Rn,Rm + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0x0, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32)), + (ExprId("exception_flags", 32), ExprInt(EXCEPT_DIV_BY_ZERO, 32))]) + + # Negative numbers + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(-4, 32)), + (ExprId("R1", 32), ExprInt(-2, 32))], + [(ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(2, 32))]) + + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(-5, 32)), + (ExprId("R1", 32), ExprInt(-2, 32))], + [(ExprId("HI", 32), ExprInt(1, 32)), + (ExprId("LO", 32), ExprInt(2, 32))]) + + # Positive numbers + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(4, 32)), + (ExprId("R1", 32), ExprInt(2, 32))], + [(ExprId("HI", 32), ExprCond(ExprOp("==", + ExprInt(0, 32), + ExprInt(0x80000000, 32)), + ExprInt(0, 32), + ExprInt(0xFFFFFFFC, 32))), + (ExprId("LO", 32), ExprCond(ExprOp("==", + ExprInt(0, 32), + ExprInt(0x80000000, 32)), + ExprInt(2, 32), + ExprInt(0, 32)))]) + + # Negative & positive numbers + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(-5, 32)), + (ExprId("R1", 32), ExprInt(2, 32))], + [(ExprId("HI", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(1, 32), ExprInt(0xFFFFFFFF, 32))), + (ExprId("LO", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(0x7FFFFFFD, 32), ExprInt(0xFFFFFFFE, 32)))]) + + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(5, 32)), + (ExprId("R1", 32), ExprInt(-2, 32))], + [(ExprId("HI", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(5, 32), ExprInt(0xFFFFFFFF, 32))), + (ExprId("LO", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(0, 32), ExprInt(0xFFFFFFFE, 32)))]) + + def test_divu(self): + """Test DIVU execution""" + + # DIVU Rn,Rm + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0x0, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32)), + (ExprId("exception_flags", 32), ExprInt(EXCEPT_DIV_BY_ZERO, 32))]) + + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0x2, 32))], + [(ExprId("HI", 32), ExprInt(0x0, 32)), + (ExprId("LO", 32), ExprInt(0x40, 32))]) + + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x83, 32)), + (ExprId("R1", 32), ExprInt(0x2, 32))], + [(ExprId("HI", 32), ExprInt(0x1, 32)), + (ExprId("LO", 32), ExprInt(0x41, 32))]) + + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x80000000, 32)), + (ExprId("R1", 32), ExprInt(-1, 32))], + [(ExprId("HI", 32), ExprInt(0x80000000, 32)), + (ExprId("LO", 32), ExprInt(0x0, 32))]) diff --git a/test/arch/mep/ir/test_extension.py b/test/arch/mep/ir/test_extension.py new file mode 100644 index 00000000..72423220 --- /dev/null +++ b/test/arch/mep/ir/test_extension.py @@ -0,0 +1,57 @@ +# Toshiba MeP-c4 - Byte/Halfword extension instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprMem, ExprInt + + +class TestExtension: + + def test_extb(self): + """Test EXTB execution""" + + # EXTB Rn + exec_instruction("EXTB R1", + [(ExprId("R1", 32), ExprInt(0xFE, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))]) + + exec_instruction("EXTB R2", + [(ExprId("R2", 32), ExprInt(0x80, 32))], + [(ExprId("R2", 32), ExprInt(0xFFFFFF80, 32))]) + + def test_exth(self): + """Test EXTH execution""" + + # EXTH Rn + exec_instruction("EXTH R1", + [(ExprId("R1", 32), ExprInt(0xFFFE, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))]) + + exec_instruction("EXTH R2", + [(ExprId("R2", 32), ExprInt(0x8000, 32))], + [(ExprId("R2", 32), ExprInt(0xFFFF8000, 32))]) + + def test_extub(self): + """Test EXTUB execution""" + + # EXTUB Rn + exec_instruction("EXTUB R1", + [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))], + [(ExprId("R1", 32), ExprInt(0xFE, 32))]) + + exec_instruction("EXTUB R2", + [(ExprId("R2", 32), ExprInt(0xFFFFFF80, 32))], + [(ExprId("R2", 32), ExprInt(0x80, 32))]) + + def test_extuh(self): + """Test EXTUH execution""" + + # EXTUH Rn + exec_instruction("EXTUH R1", + [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFE, 32))]) + + exec_instruction("EXTUH R2", + [(ExprId("R2", 32), ExprInt(0xFFFF8000, 32))], + [(ExprId("R2", 32), ExprInt(0x8000, 32))]) diff --git a/test/arch/mep/ir/test_ir.py b/test/arch/mep/ir/test_ir.py new file mode 100644 index 00000000..3fec9ec9 --- /dev/null +++ b/test/arch/mep/ir/test_ir.py @@ -0,0 +1,56 @@ +# Toshiba MeP-c4 - Misc unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from miasm2.arch.mep.arch import mn_mep +from miasm2.arch.mep.regs import regs_init +from miasm2.arch.mep.ira import ir_mepb, ir_a_mepb +from miasm2.expression.expression import ExprId, ExprInt, ExprMem +from miasm2.ir.symbexec import SymbolicExecutionEngine +from miasm2.core.locationdb import LocationDB + + +class TestMisc: + + def test(self): + + """Simple symbolic execution examples""" + + def exec_instruction(hex_asm, init_values): + """Symbolically execute an instruction""" + + print "Hex:", hex_asm + + # Disassemble an instruction + mn = mn_mep.dis(hex_asm.decode("hex"), "b") + print "Dis:", mn + + # Get the IR + im = ir_mepb() + iir, eiir, = im.get_ir(mn) + print "\nInternal representation:", iir + + # Symbolic execution + loc_db = LocationDB() + sb = SymbolicExecutionEngine(ir_a_mepb(loc_db), regs_init) + + # Assign register values before symbolic evaluation + for reg_expr_id, reg_expr_value in init_values: + sb.symbols[reg_expr_id] = reg_expr_value + + print "\nModified registers:", [reg for reg in sb.modified(mems=False)] + print "Modified memories:", [mem for mem in sb.modified()] + + print "\nFinal registers:" + sb.dump(mems=False) + + print "\nFinal mems:" + sb.dump() + + for hex_asm, init_values in [("6108", [(ExprId("R1", 32), ExprInt(0x40, 32))]), + ("08a2", [(ExprId("R8", 32), ExprInt(0x40, 32)), + (ExprId("R10", 32), ExprInt(0x41, 32))]), + ("0948", [(ExprId("R4", 32), ExprInt(0x41, 32)), + (ExprId("R9", 32), ExprInt(0x28, 32)), + (ExprMem(ExprInt(0x41, 32), 8), ExprInt(0, 8))])]: + print "-" * 49 # Tests separation + exec_instruction(hex_asm, init_values) diff --git a/test/arch/mep/ir/test_ldz.py b/test/arch/mep/ir/test_ldz.py new file mode 100644 index 00000000..02960b60 --- /dev/null +++ b/test/arch/mep/ir/test_ldz.py @@ -0,0 +1,41 @@ +# Toshiba MeP-c4 - Leading zero instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp + + +class TestLdz: + + def test_ldz(self): + """Test LDZ execution""" + + # LDZ Rn,Rm + exec_instruction("LDZ R0, R1", + [(ExprId("R1", 32), ExprInt(0x80000000, 32))], + [(ExprId("R0", 32), ExprInt(0, 32))]) + + exec_instruction("LDZ R0, R1", + [(ExprId("R1", 32), ExprInt(0x40000000, 32))], + [(ExprId("R0", 32), ExprInt(1, 32))]) + + exec_instruction("LDZ R0, R1", + [(ExprId("R1", 32), ExprInt(0b1111, 32))], + [(ExprId("R0", 32), ExprInt(28, 32))]) + + exec_instruction("LDZ R0, R1", + [(ExprId("R1", 32), ExprInt(0b0100, 32))], + [(ExprId("R0", 32), ExprInt(29, 32))]) + + exec_instruction("LDZ R0, R1", + [(ExprId("R1", 32), ExprInt(0b0010, 32))], + [(ExprId("R0", 32), ExprInt(30, 32))]) + + exec_instruction("LDZ R0, R1", + [(ExprId("R1", 32), ExprInt(0b0001, 32))], + [(ExprId("R0", 32), ExprInt(31, 32))]) + + exec_instruction("LDZ R0, R1", + [(ExprId("R1", 32), ExprInt(0b0000, 32))], + [(ExprId("R0", 32), ExprInt(32, 32))]) diff --git a/test/arch/mep/ir/test_loadstore.py b/test/arch/mep/ir/test_loadstore.py new file mode 100644 index 00000000..c6b40d55 --- /dev/null +++ b/test/arch/mep/ir/test_loadstore.py @@ -0,0 +1,209 @@ +# Toshiba MeP-c4 - Load/Store instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprMem, ExprInt + + +class TestLoadStore: + + def test_sb(self): + """Test SB execution""" + + # SB Rn,(Rm) + exec_instruction("SB R1, (R2)", + [(ExprId("R1", 32), ExprInt(0x28, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0x10, 32), 8), ExprInt(0x28, 8))]) + + # SB Rn[0-7], disp7(TP) + exec_instruction("SB R1, 0x18(R2)", + [(ExprId("R1", 32), ExprInt(0xABC7, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0x28, 32), 8), ExprInt(0xC7, 8))]) + + # SB Rn,disp16(Rm) + exec_instruction("SB R10, 0xF800(R2)", + [(ExprId("R10", 32), ExprInt(0xABC7, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0xFFFFF810, 32), 8), ExprInt(0xC7, 8))]) + + def test_sh(self): + """Test SH execution""" + + # SH Rn,(Rm) + exec_instruction("SH R1, (R2)", + [(ExprId("R1", 32), ExprInt(0x2807, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0x10, 32), 16), ExprInt(0x2807, 16))]) + + # SH Rn[0-7],disp7.align2(TP) + exec_instruction("SH R1, 0x18(R2)", + [(ExprId("R1", 32), ExprInt(0xABC7, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0x28, 32), 16), ExprInt(0xABC7, 16))]) + + # SH Rn,disp16(Rm) + exec_instruction("SH R10, 0xF800(R2)", + [(ExprId("R10", 32), ExprInt(0xABC7, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0xFFFFF810, 32), 16), ExprInt(0xABC7, 16))]) + + def test_sw(self): + """Test SW execution""" + + # SW Rn,(Rm) + exec_instruction("SW R1, (R2)", + [(ExprId("R1", 32), ExprInt(0x28071010, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0x10, 32), 32), ExprInt(0x28071010, 32))]) + + # SW Rn,disp7.align4(SP) + exec_instruction("SW R1, 4(SP)", + [(ExprId("R1", 32), ExprInt(0x28071010, 32)), + (ExprId("SP", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0x14, 32), 32), ExprInt(0x28071010, 32))]) + + # SW Rn,disp7.align4(TP) + exec_instruction("SW R1, 12(TP)", + [(ExprId("R1", 32), ExprInt(0x28071010, 32)), + (ExprId("TP", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0x1c, 32), 32), ExprInt(0x28071010, 32))]) + + # SW Rn,disp16(Rm) + exec_instruction("SW R10, 0xF800(R2)", + [(ExprId("R10", 32), ExprInt(0xABC7, 32)), + (ExprId("R2", 32), ExprInt(0x10, 32))], + [(ExprMem(ExprInt(0xFFFFF810, 32), 32), ExprInt(0xABC7, 32))]) + + # SW Rn,(abs24.align4) + exec_instruction("SW R10, (0x1010)", + [(ExprId("R10", 32), ExprInt(0xABC7, 32))], + [(ExprMem(ExprInt(0x1010, 32), 32), ExprInt(0xABC7, 32))]) + + def test_lb(self): + """Test LB executon""" + + # LB Rn,(Rm) + exec_instruction("LB R1, (R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x10, 32), 8), ExprInt(0xF0, 8))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFF0, 32))]) + + # LB Rn[0-7],disp7(TP) + exec_instruction("LB R7, 0x3(TP)", + [(ExprId("TP", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x13, 32), 8), ExprInt(0xF0, 8))], + [(ExprId("R7", 32), ExprInt(0xFFFFFFF0, 32))]) + + # LB Rn,disp16(Rm) + exec_instruction("LB R10, 0xF800(R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0xFFFFF810, 32), 8), ExprInt(0x4, 8))], + [(ExprId("R10", 32), ExprInt(0x4, 32))]) + + exec_instruction("LB R10, 0xF800(R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0xFFFFF810, 32), 8), ExprInt(0xFE, 8))], + [(ExprId("R10", 32), ExprInt(0xFFFFFFFE, 32))]) + + def test_lh(self): + """Test lh execution""" + + # LH Rn,(Rm) + exec_instruction("LH R1, (R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x10, 32), 16), ExprInt(0xF517, 16))], + [(ExprId("R1", 32), ExprInt(0xFFFFF517, 32))]) + + # LH Rn[0-7],disp7.align2(TP) + exec_instruction("LH R1, 0x18(R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x28, 32), 16), ExprInt(0xF517, 16))], + [(ExprId("R1", 32), ExprInt(0xFFFFF517, 32))]) + + # LH Rn,disp16(Rm) + exec_instruction("LH R9, 0xF000(R2)", + [(ExprId("R2", 32), ExprInt(0x42, 32)), + (ExprMem(ExprInt(0xFFFFF042, 32), 16), ExprInt(0x10, 16))], + [(ExprId("R9", 32), ExprInt(0x10, 32))]) + + exec_instruction("LH R9, 0xF000(R2)", + [(ExprId("R2", 32), ExprInt(0x42, 32)), + (ExprMem(ExprInt(0xFFFFF042, 32), 16), ExprInt(0xABCD, 16))], + [(ExprId("R9", 32), ExprInt(0xFFFFABCD, 32))]) + + def test_lw(self): + """Test SW execution""" + + # LW Rn,(Rm) + exec_instruction("LW R1, (R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x10, 32), 32), ExprInt(0xABCD, 32))], + [(ExprId("R1", 32), ExprInt(0xABCD, 32))]) + + # LW Rn,disp7.align4(SP) + exec_instruction("LW R1, 0x18(SP)", + [(ExprId("SP", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x28, 32), 32), ExprInt(0x01234567, 32))], + [(ExprId("R1", 32), ExprInt(0x01234567, 32))]) + + # LW Rn[0-7],disp7.align4(TP) + exec_instruction("LW R1, 0x18(TP)", + [(ExprId("TP", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x28, 32), 32), ExprInt(0x1010, 32))], + [(ExprId("R1", 32), ExprInt(0x1010, 32))]) + + # LW Rn,disp16(Rm) + exec_instruction("LW R9, 0xF000(R2)", + [(ExprId("R2", 32), ExprInt(0x42, 32)), + (ExprMem(ExprInt(0xFFFFF040, 32), 32), ExprInt(0x10, 32))], + [(ExprId("R9", 32), ExprInt(0x10, 32))]) + + # LW Rn,(abs24.align4) + exec_instruction("LW R10, (0x1010)", + [(ExprMem(ExprInt(0x1010, 32), 32), ExprInt(0xABC7, 32))], + [(ExprId("R10", 32), ExprInt(0xABC7, 32))]) + + def test_lbu(self): + """Test LBU execution""" + + # LBU Rn,(Rm) + exec_instruction("LBU R1, (R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x10, 32), 8), ExprInt(0xA, 8))], + [(ExprId("R1", 32), ExprInt(0xA, 32))]) + + # LBU Rn[0-7],disp7(TP) + exec_instruction("LBU R1, 0x22(R3)", + [(ExprId("R3", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x32, 32), 8), ExprInt(0xA, 8))], + [(ExprId("R1", 32), ExprInt(0xA, 32))]) + + # LBU Rn,disp16(Rm) + exec_instruction("LBU R10, 0xF000(R2)", + [(ExprId("R2", 32), ExprInt(0x42, 32)), + (ExprMem(ExprInt(0xFFFFF042, 32), 32), ExprInt(0x10, 32))], + [(ExprId("R10", 32), ExprInt(0x10, 32))]) + + def test_lhu(self): + """Test LHU execution""" + + # LHU Rn,(Rm) + exec_instruction("LHU R1, (R2)", + [(ExprId("R2", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x10, 32), 16), ExprInt(0xEF, 16))], + [(ExprId("R1", 32), ExprInt(0xEF, 32))]) + + # LHU Rn[0-7],disp7.align2(TP) + exec_instruction("LHU R1, 0x22(R3)", + [(ExprId("R3", 32), ExprInt(0x10, 32)), + (ExprMem(ExprInt(0x32, 32), 16), ExprInt(0xFEDC, 16))], + [(ExprId("R1", 32), ExprInt(0xFEDC, 32))]) + + # LHU Rn,disp16(Rm) + exec_instruction("LHU R10, 0xF000(R2)", + [(ExprId("R2", 32), ExprInt(0x42, 32)), + (ExprMem(ExprInt(0xFFFFF042, 32), 16), ExprInt(0x1234, 16))], + [(ExprId("R10", 32), ExprInt(0x1234, 32))]) diff --git a/test/arch/mep/ir/test_logical.py b/test/arch/mep/ir/test_logical.py new file mode 100644 index 00000000..61cbbf0a --- /dev/null +++ b/test/arch/mep/ir/test_logical.py @@ -0,0 +1,65 @@ +# Toshiba MeP-c4 - Logical instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp + + +class TestLogical: + + def test_or(self): + """Test OR execution""" + + # OR Rn, Rm + exec_instruction("OR R1, R2", + [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(1, 32))]) + + def test_or3(self): + """Test OR3 execution""" + + # OR3 Rn,Rm,imm16 + exec_instruction("OR3 R1, R2, 1", + [(ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(1, 32))]) + + def test_and(self): + """Test AND execution""" + + # AND Rn, Rm + exec_instruction("AND R1, R2", + [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(0, 32))], + [(ExprId("R1", 32), ExprInt(0, 32))]) + + def test_and3(self): + """Test AND3 execution""" + + # AND3 Rn,Rm,imm16 + exec_instruction("AND3 R1, R2, 0", + [(ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(0, 32))]) + + def test_xor(self): + """Test XOR execution""" + + # XOR Rn, Rm + exec_instruction("XOR R1, R2", + [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(0, 32))], + [(ExprId("R1", 32), ExprInt(1, 32))]) + + def test_xor3(self): + """Test XOR3 execution""" + + # XOR3 Rn,Rm,imm16 + exec_instruction("XOR3 R1, R2, 1", + [(ExprId("R2", 32), ExprInt(0, 32))], + [(ExprId("R1", 32), ExprInt(1, 32))]) + + def test_nor(self): + """Test NOR execution""" + + # NOR Rn, Rm + exec_instruction("NOR R1, R2", + [(ExprId("R1", 32), ExprInt(1, 32)), (ExprId("R2", 32), ExprInt(0, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))]) diff --git a/test/arch/mep/ir/test_move.py b/test/arch/mep/ir/test_move.py new file mode 100644 index 00000000..56a4225e --- /dev/null +++ b/test/arch/mep/ir/test_move.py @@ -0,0 +1,58 @@ +# Toshiba MeP-c4 - Move instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprMem, ExprInt + + +class TestMove: + + def test_mov(self): + """Test MOV execution""" + + # MOV Rn,Rm + exec_instruction("MOV R1, R2", + [(ExprId("R2", 32), ExprInt(0x2807, 32))], + [(ExprId("R1", 32), ExprInt(0x2807, 32))]) + + # MOV Rn,imm8 + exec_instruction("MOV R1, 0x28", + [], + [(ExprId("R1", 32), ExprInt(0x28, 32))]) + + exec_instruction("MOV R1, 0x80", + [], + [(ExprId("R1", 32), ExprInt(0xFFFFFF80, 32))]) + + # MOV Rn,imm16 + exec_instruction("MOV R1, 0x2807", + [], + [(ExprId("R1", 32), ExprInt(0x2807, 32))], + index=1) + + def test_movu(self): + """Test MOVU execution""" + + # MOVU Rn[0-7],imm24 + exec_instruction("MOVU R1, 0xFF2807", + [], + [(ExprId("R1", 32), ExprInt(0xFF2807, 32))], + index=1) + + # MOVU Rn,imm16 + exec_instruction("MOVU R10, 0x2807", + [], + [(ExprId("R10", 32), ExprInt(0x2807, 32))]) + + def test_movh(self): + """Test MOVH execution""" + + # MOVH Rn,imm16 + exec_instruction("MOVH R1, 1", + [], + [(ExprId("R1", 32), ExprInt(0x10000, 32))]) + + exec_instruction("MOVH R1, 0xFFFF", + [], + [(ExprId("R1", 32), ExprInt(0xFFFF0000, 32))]) diff --git a/test/arch/mep/ir/test_multiply.py b/test/arch/mep/ir/test_multiply.py new file mode 100644 index 00000000..0618f69f --- /dev/null +++ b/test/arch/mep/ir/test_multiply.py @@ -0,0 +1,138 @@ +# Toshiba MeP-c4 - Multiply instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp + + +class TestMultiply: + + def test_mul(self): + """Test MUL execution""" + + # MUL Rn,Rm + exec_instruction("MUL R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32))]) + + exec_instruction("MUL R0, R1", + [(ExprId("R0", 32), ExprInt(0x80000000, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("HI", 32), ExprInt(0x00000000, 32)), + (ExprId("LO", 32), ExprInt(0x80000000, 32))]) + + def test_mulu(self): + """Test MULU execution""" + + # MULU Rn,Rm + exec_instruction("MULU R0, R1", + [(ExprId("R0", 32), ExprInt(0x2, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("HI", 32), ExprInt(0x1, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32))]) + + exec_instruction("MULU R0, R1", + [(ExprId("R0", 32), ExprInt(0x80000000, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("HI", 32), ExprInt(0x7FFFFFFF, 32)), + (ExprId("LO", 32), ExprInt(0x80000000, 32))]) + + def test_mulr(self): + """Test MULR execution""" + + # MULR Rn,Rm + exec_instruction("MULR R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32)), + (ExprId("R0", 32), ExprInt(0xFFFFFF80, 32))]) + + def test_mulru(self): + """Test MULRU execution""" + + # MULRU Rn,Rm + exec_instruction("MULRU R0, R1", + [(ExprId("R0", 32), ExprInt(0x2, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32))], + [(ExprId("HI", 32), ExprInt(0x1, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32)), + (ExprId("R0", 32), ExprInt(0xFFFFFFFE, 32))]) + + def test_madd(self): + """Test MADD execution""" + + # MADD Rn,Rm + exec_instruction("MADD R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32))]) + + exec_instruction("MADD R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("HI", 32), ExprInt(1, 32)), + (ExprId("LO", 32), ExprInt(1, 32))], + [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFF81, 32))]) + + def test_maddu(self): + """Test MADDU execution""" + + # MADDU Rn,Rm + exec_instruction("MADDU R0, R1", + [(ExprId("R0", 32), ExprInt(0x2, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0x1, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32))]) + + exec_instruction("MADDU R0, R1", + [(ExprId("R0", 32), ExprInt(0x2, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("HI", 32), ExprInt(1, 32)), + (ExprId("LO", 32), ExprInt(1, 32))], + [(ExprId("HI", 32), ExprInt(0x1, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFFFF, 32))]) + + def test_maddr(self): + """Test MADDR execution""" + + # MADDR Rn,Rm + exec_instruction("MADDR R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFF80, 32)), + (ExprId("R0", 32), ExprInt(0xFFFFFF80, 32))]) + + exec_instruction("MADDR R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("HI", 32), ExprInt(1, 32)), + (ExprId("LO", 32), ExprInt(1, 32))], + [(ExprId("HI", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFF81, 32)), + (ExprId("R0", 32), ExprInt(0xFFFFFF81, 32))]) + + def test_maddru(self): + """Test MADDRU execution""" + + # MADDRU Rn,Rm + exec_instruction("MADDRU R0, R1", + [(ExprId("R0", 32), ExprInt(0x2, 32)), + (ExprId("R1", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0x1, 32)), + (ExprId("LO", 32), ExprInt(0xFFFFFFFE, 32)), + (ExprId("R0", 32), ExprInt(0xFFFFFFFE, 32))]) diff --git a/test/arch/mep/ir/test_repeat.py b/test/arch/mep/ir/test_repeat.py new file mode 100644 index 00000000..252764b1 --- /dev/null +++ b/test/arch/mep/ir/test_repeat.py @@ -0,0 +1,29 @@ +# Toshiba MeP-c4 - Repeat instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp + + +class TestRepeat: + + def test_repeat(self): + """Test REPEAT execution""" + + # REPEAT Rn, disp17.align2 + exec_instruction("REPEAT R0, 0x42", + [(ExprId("PC", 32), ExprInt(2, 32)), + (ExprId("R0", 32), ExprInt(0x28, 32))], + [(ExprId("RPB", 32), ExprInt(6, 32)), + (ExprId("RPE", 32), ExprInt(0x44, 32)), + (ExprId("RPC", 32), ExprInt(0x28, 32))]) + + def test_erepeat(self): + """Test EREPEAT execution""" + + # EREPEAT disp17.align2 + exec_instruction("EREPEAT 0x42", + [(ExprId("PC", 32), ExprInt(0, 32))], + [(ExprId("RPB", 32), ExprInt(4, 32)), + (ExprId("RPE", 32), ExprInt(0x43, 32))]) diff --git a/test/arch/mep/ir/test_shift.py b/test/arch/mep/ir/test_shift.py new file mode 100644 index 00000000..b63f9ed7 --- /dev/null +++ b/test/arch/mep/ir/test_shift.py @@ -0,0 +1,108 @@ +# Toshiba MeP-c4 - Shift instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm2.core.cpu import sign_ext + + +class TestShift: + + def test_sra(self): + """Test SRA execution""" + + # SRA Rn, Rm + exec_instruction("SRA R1, R2", + [(ExprId("R1", 32), ExprInt(4, 32)), (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(2, 32))]) + + exec_instruction("SRA R1, R2", + [(ExprId("R1", 32), ExprInt(sign_ext(4, 3, 32), 32)), (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(0xFFFFFFFE, 32))]) + + exec_instruction("SRA R1, R2", + [(ExprId("R1", 32), ExprInt(0xF0000000, 32)), (ExprId("R2", 32), ExprInt(4, 32))], + [(ExprId("R1", 32), ExprInt(0xFF000000, 32))]) + + # SRA Rn,imm5 + exec_instruction("SRA R1, 1", + [(ExprId("R1", 32), ExprInt(4, 32))], + [(ExprId("R1", 32), ExprInt(2, 32))]) + + # SRA Rn,imm5 + exec_instruction("SRA R1, 1", + [(ExprId("R1", 32), ExprInt(0x80000000, 32))], + [(ExprId("R1", 32), ExprInt(0xC0000000, 32))]) + + exec_instruction("SRA R1, 1", + [(ExprId("R1", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(0, 32))]) + + def test_srl(self): + """Test SRL execution""" + + # SRL Rn, Rm + exec_instruction("SRL R1, R2", + [(ExprId("R1", 32), ExprInt(4, 32)), (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(2, 32))]) + + # SRL Rn,imm5 + exec_instruction("SRL R1, 1", + [(ExprId("R1", 32), ExprInt(4, 32))], + [(ExprId("R1", 32), ExprInt(2, 32))]) + + exec_instruction("SRL R1, 1", + [(ExprId("R1", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(0, 32))]) + + def test_sll(self): + """Test SLL execution""" + + # SLL Rn, Rm + exec_instruction("SLL R1, R2", + [(ExprId("R1", 32), ExprInt(4, 32)), (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(8, 32))]) + + exec_instruction("SLL R1, R2", + [(ExprId("R1", 32), ExprInt(0x80000000, 32)), (ExprId("R2", 32), ExprInt(1, 32))], + [(ExprId("R1", 32), ExprInt(0, 32))]) + + # SLL Rn,imm5 + exec_instruction("SLL R1, 1", + [(ExprId("R1", 32), ExprInt(4, 32))], + [(ExprId("R1", 32), ExprInt(8, 32))]) + + def test_sll3(self): + """Test SLL3 execution""" + + # SLL3 R0,Rn,imm5 + exec_instruction("SLL3 R0, R1, 2", + [(ExprId("R1", 32), ExprInt(4, 32))], + [(ExprId("R0", 32), ExprInt(16, 32))]) + + exec_instruction("SLL3 R0, R1, 2", + [(ExprId("R1", 32), ExprInt(0xC0000000, 32))], + [(ExprId("R0", 32), ExprInt(0, 32))]) + + def test_fsft(self): + """Test FSFT execution""" + + # FSFT Rn,Rm + exec_instruction("FSFT R0, R1", + [(ExprId("SAR", 32), ExprInt(0x00000001, 32)), + (ExprId("R0", 32), ExprInt(0x00000001, 32)), + (ExprId("R1", 32), ExprInt(0x80000000, 32))], + [(ExprId("R0", 32), ExprInt(0x00000003, 32))]) + + exec_instruction("FSFT R0, R1", + [(ExprId("SAR", 32), ExprInt(0x00000004, 32)), + (ExprId("R0", 32), ExprInt(0xFFFFFFFF, 32)), + (ExprId("R1", 32), ExprInt(0xF0000000, 32))], + [(ExprId("R0", 32), ExprInt(0xFFFFFFFF, 32))]) + + exec_instruction("FSFT R0, R1", + [(ExprId("SAR", 32), ExprInt(0x00000004, 32)), + (ExprId("R0", 32), ExprInt(0xF0000000, 32)), + (ExprId("R1", 32), ExprInt(0x0F000000, 32))], + [(ExprId("R0", 32), ExprInt(0, 32))]) diff --git a/test/arch/mep/ir/ut_helpers_ir.py b/test/arch/mep/ir/ut_helpers_ir.py new file mode 100644 index 00000000..fcf31764 --- /dev/null +++ b/test/arch/mep/ir/ut_helpers_ir.py @@ -0,0 +1,87 @@ +# Toshiba MeP-c4 - unit tests helpers +# Guillaume Valadon <guillaume@valadon.net> + +from miasm2.arch.mep.arch import mn_mep +from miasm2.arch.mep.sem import ir_mepb +from miasm2.arch.mep.regs import regs_init + +from miasm2.ir.symbexec import SymbolicExecutionEngine +from miasm2.core.locationdb import LocationDB +from miasm2.core.utils import Disasm_Exception +from miasm2.ir.ir import AssignBlock +from miasm2.arch.mep.ira import ir_a_mepb +from miasm2.expression.expression import ExprId, ExprInt, ExprOp, ExprMem, ExprAff, ExprLoc + + +def exec_instruction(mn_str, init_values, results, index=0, offset=0): + """Symbolically execute an instruction and check the expected results.""" + + # Assemble and disassemble the instruction + instr = mn_mep.fromstring(mn_str, "b") + instr.mode = "b" + mn_bin = mn_mep.asm(instr)[index] + try: + instr = mn_mep.dis(mn_bin, "b") + except Disasm_Exception: + assert(False) # miasm don't know what to do + + # Specify the instruction offset and compute the destination label + instr.offset = offset + loc_db = LocationDB() + if instr.dstflow(): + instr.dstflow2label(loc_db) + + # Get the IR + im = ir_mepb(loc_db) + iir, eiir = im.get_ir(instr) + + # Filter out IRDst + iir = [ir for ir in iir if not (isinstance(ir, ExprAff) and + isinstance(ir.dst, ExprId) and + ir.dst.name == "IRDst")] + + # Prepare symbolic execution + sb = SymbolicExecutionEngine(ir_a_mepb(loc_db), regs_init) + + # Assign int values before symbolic evaluation + for expr_id, expr_value in init_values: + sb.symbols[expr_id] = expr_value + + # Execute the IR + ab = AssignBlock(iir) + sb.eval_updt_assignblk(ab) + + # Check if expected expr_id were modified + matched_results = 0 + for expr_id, expr_value in results: + + result = sb.eval_expr(expr_id) + if isinstance(result, ExprLoc): + addr = loc_db.get_location_offset(result.loc_key) + if expr_value.arg == addr: + matched_results += 1 + continue + elif result == expr_value: + matched_results += 1 + continue + + # Ensure that all expected results were verified + if len(results) is not matched_results: + print "Expected:", results + print "Modified:", [r for r in sb.modified(mems=False)] + assert(False) + + +def launch_tests(obj): + """Call test methods by name""" + + test_methods = [name for name in dir(obj) if name.startswith("test")] + + for method in test_methods: + print method + try: + getattr(obj, method)() + except AttributeError as e: + print "Method not found: %s" % method + assert(False) + print '-' * 42 diff --git a/test/arch/mep/jit/launch.py b/test/arch/mep/jit/launch.py new file mode 100644 index 00000000..8c67e072 --- /dev/null +++ b/test/arch/mep/jit/launch.py @@ -0,0 +1,7 @@ +# Toshiba MeP-c4 - pytest unit tests wrapper +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_jit import launch_tests + +from test_jit_branchjump import TestBranchJump; launch_tests(TestBranchJump()) +from test_jit_repeat import TestRepeat; launch_tests(TestRepeat()) diff --git a/test/arch/mep/jit/test_jit_branchjump.py b/test/arch/mep/jit/test_jit_branchjump.py new file mode 100644 index 00000000..baf602d8 --- /dev/null +++ b/test/arch/mep/jit/test_jit_branchjump.py @@ -0,0 +1,23 @@ +# Toshiba MeP-c4 - Branch/Jump instructions JIT unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_jit import jit_instructions + + +class TestBranchJump: + + def test_blti(self): + """Test BLTI jit""" + + # Instructions that will be jitted + instructions = "MOV R0, 1\n" + instructions += "BLTI R0, 0x2, 0x6\n" + instructions += "MOV R0, 0\n" + instructions += "MOV R1, 1" + + # Jit + jitter = jit_instructions(instructions) + + # Check expected results + assert(jitter.cpu.R0 == 1) + assert(jitter.cpu.R1 == 1) diff --git a/test/arch/mep/jit/test_jit_repeat.py b/test/arch/mep/jit/test_jit_repeat.py new file mode 100644 index 00000000..9fa64fa5 --- /dev/null +++ b/test/arch/mep/jit/test_jit_repeat.py @@ -0,0 +1,99 @@ +# Toshiba MeP-c4 - *REPEAT instructions JIT unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_jit import jit_instructions + + +class TestRepeat: + def test_repeat(self): + """Test REPEAT jit""" + + # Instructions that will be jitted + instructions = "MOV R0, 8\n" + instructions += "REPEAT R0, 0x6\n" + instructions += "ADD R1, 1\n" + instructions += "ADD R2, 1\n" # <-RPE + instructions += "ADD R3, 1" + + # Jit + jitter = jit_instructions(instructions) + + # Check expected results + assert(jitter.cpu.R0 == 8) + assert(jitter.cpu.R1 == 8) + assert(jitter.cpu.R2 == 8) + assert(jitter.cpu.R3 == 8) + + def test_erepeat_0(self): + """Test EREPEAT jit""" + + # Instructions that will be jitted + instructions = "EREPEAT 0xA\n" + instructions += "ADD R1, 1\n" + instructions += "BEQI R1, 0x6, 0x8\n" + instructions += "ADD R2, 1\n" + instructions += "ADD R3, 1" # <- RPE + + # Jit + jitter = jit_instructions(instructions) + + # Check expected results + assert(jitter.cpu.R1 == 6) + assert(jitter.cpu.R2 == 5) + assert(jitter.cpu.R3 == 5) + + def test_erepeat_1(self): + """Test EREPEAT jit""" + + # Instructions that will be jitted + instructions = "EREPEAT 0x8\n" + instructions += "ADD R1, 1\n" + instructions += "ADD R2, 1\n" + instructions += "ADD R3, 1\n" + instructions += "BEQI R1, 0x6, 0x4\n" # <- RPE + instructions += "ADD R2, 1\n" + instructions += "ADD R3, 1" + + # Jit + jitter = jit_instructions(instructions) + + # Check expected results + assert(jitter.cpu.R1 == 6) + assert(jitter.cpu.R2 == 7) + assert(jitter.cpu.R3 == 7) + + def test_erepeat_2(self): + """Test EREPEAT jit""" + + # Instructions that will be jitted + instructions = "EREPEAT 0x8\n" + instructions += "ADD R1, 1\n" + instructions += "ADD R2, 1\n" + instructions += "ADD R3, 1\n" # <- RPE + instructions += "BEQI R3, 0x6, 0x4" + + # Jit + jitter = jit_instructions(instructions) + + # Check expected results + assert(jitter.cpu.R1 == 6) + assert(jitter.cpu.R2 == 6) + assert(jitter.cpu.R3 == 6) + + def test_erepeat_3(self): + """Test EREPEAT jit""" + + # Instructions that will be jitted + instructions = "EREPEAT 0x8\n" + instructions += "ADD R1, 1\n" + instructions += "ADD R2, 1\n" + instructions += "BEQI R1, 0x6, 0x6\n" # <- RPE + instructions += "ADD R3, 1" + + # Jit + jitter = jit_instructions(instructions) + + # Check expected results + assert(jitter.cpu.R1 == 6) + assert(jitter.cpu.R2 == 6) + assert(jitter.cpu.R3 == 5) diff --git a/test/arch/mep/jit/ut_helpers_jit.py b/test/arch/mep/jit/ut_helpers_jit.py new file mode 100644 index 00000000..590c534f --- /dev/null +++ b/test/arch/mep/jit/ut_helpers_jit.py @@ -0,0 +1,49 @@ +# Toshiba MeP-c4 - unit tests helpers +# Guillaume Valadon <guillaume@valadon.net> + +from miasm2.analysis.machine import Machine +from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE + + +def jit_instructions(mn_str): + """JIT instructions and return the jitter object.""" + + # Get the miasm2 Machine + machine = Machine("mepb") + mn_mep = machine.mn() + + # Assemble the instructions + asm = "" + for instr_str in mn_str.split("\n"): + instr = mn_mep.fromstring(instr_str, "b") + instr.mode = "b" + asm += mn_mep.asm(instr)[0] + + # Init the jitter and add the assembled instructions to memory + jitter = machine.jitter(jit_type="gcc") + jitter.vm.add_memory_page(0, PAGE_READ | PAGE_WRITE, asm) + + # Set the breakpoint + jitter.add_breakpoint(len(asm), lambda x: False) + + # Jit the instructions + #jitter.init_stack() + jitter.init_run(0) + jitter.continue_run() + + return jitter + + +def launch_tests(obj): + """Call test methods by name""" + + test_methods = [name for name in dir(obj) if name.startswith("test")] + + for method in test_methods: + print method + try: + getattr(obj, method)() + except AttributeError as e: + print "Method not found: %s" % method + assert(False) + print '-' * 42 diff --git a/test/test_all.py b/test/test_all.py index 665fc3a5..07210f01 100755 --- a/test/test_all.py +++ b/test/test_all.py @@ -724,6 +724,11 @@ testset += ExampleJitter(["example_types.py"]) testset += ExampleJitter(["trace.py", Example.get_sample("md5_arm"), "-a", "0xA684"]) +## Toshiba MeP +testset = TestSet("../") +testset += RegressionTest(["launch.py"], base_dir="arch/mep/asm") +testset += RegressionTest(["launch.py"], base_dir="arch/mep/ir") +testset += RegressionTest(["launch.py"], base_dir="arch/mep/jit") if __name__ == "__main__": # Argument parsing |