about summary refs log tree commit diff stats
path: root/example/asm/shellcode.py (unfollow)
Commit message (Expand)AuthorFilesLines
2017-08-01Avoid potential (but unlikely) hash collisionAjax1-2/+2
2017-07-27Asmblock: remove disasm engine job_done attributeFabrice Desclaux6-24/+30
2017-07-25Jitter: fix shifter macroFabrice Desclaux3-94/+22
2017-07-24Add null pointer check after reallocWilliam Bruneau2-8/+15
2017-07-24Aarch64: complete DecodeBitMasks test for full branch coverageAjax1-0/+4
2017-07-24Aarch64: remove useless codeAjax1-11/+0
2017-07-24Aarch64: decode ORR/AND/... imm according to ARM ASLAjax1-16/+206
2017-07-24x86: fix MOVSD semanticAjax1-8/+12
2017-07-21Aarch64: mask ROR/ROL result to avoid overflowAjax1-2/+4
2017-07-21DSE: use registers from the real arch, not the jitter emulated oneAjax1-3/+15
2017-07-21Complete attrib_to_regs with IP/EIP (was present in 64)Ajax1-2/+2
2017-07-21Aarch64: add semantic for BLRAjax1-0/+5
2017-07-21Add support for multi-ret on cdecl / systemV x86 ABIAjax1-3/+5
2017-07-21Add support for multi-ret on stdcall / systemV ARM ABIAjax1-3/+5
2017-07-21Add arch-desc in hash, avoiding multi-arch collisionAjax1-4/+6
2017-07-21Jit: merge duplicate hash codeAjax3-26/+15
2017-07-20Add null pointer check after reallocWilliam Bruneau1-0/+10
2017-07-20Fix typo in /test/core/asmblock.pyWilliam Bruneau1-1/+1
2017-07-20Remove unecessary assertWilliam Bruneau1-1/+0
2017-07-20Fix typoWilliam Bruneau1-6/+6
2017-07-07Asmblock: rename blocFabrice Desclaux18-40/+57
2017-07-07IR: rename post_add_blocFabrice Desclaux2-4/+12
2017-07-07IR: rename add_blocFabrice Desclaux16-21/+29
2017-07-07IR: rename get_blocFabrice Desclaux5-6/+14