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path: root/example/expression/expr_translate.py (unfollow)
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2017-08-04TypeMngr: generate name for unnamed structs/unionsFabrice Desclaux1-4/+27
2017-08-04Objc: fix tipoFabrice Desclaux1-4/+4
2017-08-03A defined 'size' is mandatory for `Expr` to workAjax1-24/+16
2017-08-03Avoid breaking potential overriding of ExprIntAjax1-1/+1
2017-08-03Avoid racing ._size assignment in ExprIntAjax1-3/+6
2017-08-03Remove now useless propertyAjax1-8/+0
2017-08-03Expr: move class-dependent attributes to protected oneAjax1-187/+187
2017-08-02fix atomic_mode leakcoco1-1/+5
2017-08-01Avoid potential (but unlikely) hash collisionAjax1-2/+2
2017-07-27Asmblock: remove disasm engine job_done attributeFabrice Desclaux6-24/+30
2017-07-25Jitter: fix shifter macroFabrice Desclaux3-94/+22
2017-07-24Add null pointer check after reallocWilliam Bruneau2-8/+15
2017-07-24Aarch64: complete DecodeBitMasks test for full branch coverageAjax1-0/+4
2017-07-24Aarch64: remove useless codeAjax1-11/+0
2017-07-24Aarch64: decode ORR/AND/... imm according to ARM ASLAjax1-16/+206
2017-07-24x86: fix MOVSD semanticAjax1-8/+12
2017-07-21Aarch64: mask ROR/ROL result to avoid overflowAjax1-2/+4
2017-07-21DSE: use registers from the real arch, not the jitter emulated oneAjax1-3/+15
2017-07-21Complete attrib_to_regs with IP/EIP (was present in 64)Ajax1-2/+2
2017-07-21Aarch64: add semantic for BLRAjax1-0/+5
2017-07-21Add support for multi-ret on cdecl / systemV x86 ABIAjax1-3/+5
2017-07-21Add support for multi-ret on stdcall / systemV ARM ABIAjax1-3/+5
2017-07-21Add arch-desc in hash, avoiding multi-arch collisionAjax1-4/+6
2017-07-21