| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename miasm2 to miasm | Fabrice Desclaux | 2019-03-05 | 1 | -499/+0 |
| | | |||||
| * | Support python2/python3 | Fabrice Desclaux | 2019-03-05 | 1 | -78/+97 |
| | | |||||
| * | Code cleaning: remove useless / commented code | Ajax | 2018-06-21 | 1 | -1/+1 |
| | | |||||
| * | Fix memory breakpoint name | Fabrice Desclaux | 2018-03-28 | 1 | -1/+1 |
| | | |||||
| * | Jitter: fix single step | Fabrice Desclaux | 2015-11-15 | 1 | -2/+2 |
| | | |||||
| * | In interactive use, allow C-like prefixes to choose the base of integers | Aymeric Vincent | 2015-10-27 | 1 | -20/+5 |
| | | | | | | | | Use Python's int(s, 0) to allow string "s" to specify its base where addresses and offsets can be supplied. This change makes the situation homogeneous among the various examples and interactive usage. | ||||
| * | Debugging: handle breakpoint stop with a proper state | Camille Mougey | 2015-10-19 | 1 | -2/+13 |
| | | |||||
| * | Debugging: propagate status on breakpoint stop | Camille Mougey | 2015-10-19 | 1 | -3/+5 |
| | | |||||
| * | Jitter: get/set mem is now wrapped in cpu | serpilliere | 2015-04-22 | 1 | -1/+3 |
| | | | | | | The get/set mem used during jit is wrapped by cpu. This allows cpu object to callback (or not, depending on arch) a cache update. | ||||
| * | PyLint: Import errors, pointless statements (`fds`), bad indentation | Camille Mougey | 2015-02-18 | 1 | -1/+1 |
| | | |||||
| * | PyLint: Debugging: Invalid name | Camille Mougey | 2015-02-16 | 1 | -6/+6 |
| | | |||||
| * | Remove vm_ prefix /!\ API MODIF | Fabrice Desclaux | 2014-10-07 | 1 | -7/+7 |
| | | | | | | | | The jitter cpu/vm modules used an unecessary vm_ prefix for various api. jitter.cpu.vm_get_gpreg() => jitter.cpu.get_gpreg() jitter.vm.vm_get_mem... => jitter.vm.get_mem... | ||||
| * | Modify irbloc destination mecanism. Rework API in consequence. | Fabrice Desclaux | 2014-09-05 | 1 | -1/+1 |
| | | | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon. | ||||
| * | Debugging: fix watchmem second arg | ajax | 2014-06-04 | 1 | -4/+5 |
| | | |||||
| * | Miasm v2 | serpilliere | 2014-06-03 | 1 | -0/+479 |
| * API has changed, so old scripts need updates * See example for API usage * Use tcc or llvm for jit emulation * Go to test and run test_all.py to check install Enjoy ! | |||||