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* Rename miasm2 to miasmFabrice Desclaux2019-03-051-151/+0
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* Support python2/python3Fabrice Desclaux2019-03-051-3/+4
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* All: updt apiFabrice Desclaux2018-10-121-2/+2
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* Update symbol_pool's deprecated API -> LocationDBAjax2018-07-031-1/+1
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* symbol_pool -> loc_dbAjax2018-07-031-4/+4
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* Jitters: use loc_key instead of names or offset for basic block labelingAjax2018-06-221-1/+1
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* Jitter: rename jitter class into JitterFabrice Desclaux2018-06-211-5/+5
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* Core: replace AsmLabel by LocKeyFabrice Desclaux2018-06-091-6/+7
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* Expr: Add new word ExprLocFabrice Desclaux2018-06-081-2/+2
| | | | | This word represents a location in the binary. Thus, the hack of ExprId containing an AsmLabel ends here.
* Update Mips runtimeFabrice Desclaux2018-05-021-1/+37
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* Expression: no default size for ExprIdFabrice Desclaux2018-02-091-5/+5
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* IRBlock: irblock iterates on its assignblksFabrice Desclaux2018-02-091-2/+2
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* IRBlock: replace irs by assignblksFabrice Desclaux2018-02-091-2/+2
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* IR: Make IRBlock immutableFabrice Desclaux2017-05-241-14/+17
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* IRBlock: move lines in AssignBlockFabrice Desclaux2017-04-201-1/+1
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* Ir: make AssignBlock immutableFabrice Desclaux2017-04-201-4/+8
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* Jitter: fix symb cache name (#525)serpilliere2017-04-181-1/+1
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* Core/asmbloc: move asmbloc to asmblockFabrice Desclaux2017-03-131-3/+3
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* Asmbloc: rename asm_symbol_pool to AsmSymbolPoolFabrice Desclaux2017-03-131-2/+2
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* Arch: clean ira/jitFabrice Desclaux2017-03-131-10/+9
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* Jitter: suport mips32Fabrice Desclaux2016-08-301-0/+63
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* Jitter: code generator reworkFabrice Desclaux2016-08-301-4/+3
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* Arch/jit: add endianess support jittersFabrice Desclaux2014-10-091-4/+12
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* Remove vm_ prefix /!\ API MODIFFabrice Desclaux2014-10-071-5/+5
| | | | | | | The jitter cpu/vm modules used an unecessary vm_ prefix for various api. jitter.cpu.vm_get_gpreg() => jitter.cpu.get_gpreg() jitter.vm.vm_get_mem... => jitter.vm.get_mem...
* Modify irbloc destination mecanism. Rework API in consequence.Fabrice Desclaux2014-09-051-2/+2
| | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
* Jitter: add mips32l jitserpilliere2014-08-221-0/+37