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* Rename miasm2 to miasmFabrice Desclaux2019-03-051-509/+0
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* Support python2/python3Fabrice Desclaux2019-03-051-2/+2
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* MSP430: Explicit flagsFabrice Desclaux2019-01-111-100/+152
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* Expresion: use ExprAssign instead of ExprAffFabrice Desclaux2018-10-011-63/+63
| | | | | | ExprAff stands for (in french) "Expression affectation" We will now use ExprAssign (for Expression Assignment) (instead of ExprAss)
* symbol_pool -> loc_dbAjax2018-07-031-2/+2
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* Code cleaning: remove useless / commented codeAjax2018-06-211-1/+0
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* Core: replace AsmLabel by LocKeyFabrice Desclaux2018-06-091-27/+27
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* Expr: Add new word ExprLocFabrice Desclaux2018-06-081-20/+29
| | | | | This word represents a location in the binary. Thus, the hack of ExprId containing an AsmLabel ends here.
* Symbexec: use hashtable for mem symbolsFabrice Desclaux2018-03-151-0/+1
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* MSP430:fix apiFabrice Desclaux2017-06-131-2/+2
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* Replace ExprInt[num](x) -> ExprInt(x, num)Ajax2017-03-301-15/+15
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* IR/ir: rename ir to IntermediateRepresentationFabrice Desclaux2017-03-131-3/+3
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* remove #! command line on files not supposed to be run at top levelAymeric Vincent2017-01-051-1/+0
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* Expr: Remove exprint_fromFabrice Desclaux2016-12-231-4/+4
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* ExprCompose: add new apiFabrice Desclaux2016-11-041-18/+4
| | | | | | | The ExprComposes uses directly its arguments sizes to guess the slices locations. Old api: ExprCompose([(a, 0, 32), (b, 32, 64)]) becomes: ExprCompose(a, b)
* Expression: fix apiFabrice Desclaux2015-10-291-1/+1
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* MSP430: add semantic for `add.b`Pierre LALET2015-03-121-0/+16
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* MSP430 semantic: fix SR affectationPierre LALET2015-03-101-1/+1
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* msp430 semantic: fix carry and overflow flags for cmp.* mnemonicsPierre LALET2015-02-271-4/+4
| | | | Thanks serpilliere & kamoul0x
* Arch: remove code which uses expression modificationsserpilliere2015-02-221-2/+3
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* PyLint: Remove relative importsCamille Mougey2015-02-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | miasm2/jitter/jitload.py:17: [W0403(relative-import), ] Relative import 'jitcore_tcc', should be 'miasm2.jitter.jitcore_tcc' miasm2/jitter/jitload.py:22: [W0403(relative-import), ] Relative import 'jitcore_llvm', should be 'miasm2.jitter.jitcore_llvm' miasm2/jitter/jitload.py:27: [W0403(relative-import), ] Relative import 'jitcore_python', should be 'miasm2.jitter.jitcore_python' miasm2/jitter/jitcore.py:20: [W0403(relative-import), ] Relative import 'csts', should be 'miasm2.jitter.csts' miasm2/jitter/jitcore_tcc.py:7: [W0403(relative-import), ] Relative import 'jitcore', should be 'miasm2.jitter.jitcore' miasm2/jitter/jitcore_llvm.py:4: [W0403(relative-import), ] Relative import 'llvmconvert', should be 'miasm2.jitter.llvmconvert' miasm2/jitter/jitcore_llvm.py:5: [W0403(relative-import), ] Relative import 'jitcore', should be 'miasm2.jitter.jitcore' miasm2/jitter/loader/elf.py:7: [W0403(relative-import), ] Relative import 'utils', should be 'miasm2.jitter.loader.utils' miasm2/core/cpu.py:11: [W0403(relative-import), ] Relative import 'bin_stream', should be 'miasm2.core.bin_stream' miasm2/core/cpu.py:12: [W0403(relative-import), ] Relative import 'utils', should be 'miasm2.core.utils' miasm2/arch/sh4/arch.py:9: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.sh4.regs' miasm2/arch/msp430/sem.py:8: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.msp430.arch' miasm2/arch/arm/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.arm.regs' miasm2/arch/arm/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.arm.regs' miasm2/arch/arm/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.arm.arch' miasm2/arch/x86/sem.py:26: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/arch.py:9: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/disasm.py:3: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.x86.arch' miasm2/arch/mips32/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.mips32.regs' miasm2/arch/mips32/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.mips32.regs' miasm2/arch/mips32/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.mips32.arch'
* Modify irbloc destination mecanism. Rework API in consequence.Fabrice Desclaux2014-09-051-32/+39
| | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
* Miasm v2serpilliere2014-06-031-0/+440
* API has changed, so old scripts need updates * See example for API usage * Use tcc or llvm for jit emulation * Go to test and run test_all.py to check install Enjoy !