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* Rename miasm2 to miasmFabrice Desclaux2019-03-0516-4806/+0
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* Support python2/python3Fabrice Desclaux2019-03-057-248/+210
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* X86: makes tsc 64 bit instead of 2 32bits regsFabrice Desclaux2019-02-202-14/+7
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* Jitter/python: use correct dump gpregsFabrice Desclaux2019-01-146-4/+64
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* Fix typos & add codespellPierre LALET2018-12-236-12/+12
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* Jit/Arch: init regs size for all archFabrice Desclaux2018-09-196-263/+265
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* JitCore: Fix bn to reg convertionFabrice Desclaux2018-09-191-5/+2
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* Jitter: Fix memory leakFabrice Desclaux2018-09-191-1/+11
| | | | | | References on PyLong where lost. Memory exhaustion may hapen in python jitter because of high usage of get/set register.
* Adds Windows support and AppVeyor CI (#835)Axel Souchet2018-09-098-10/+50
| | | | | | | | | | | | | | | | | | | | | | | | * Get miasm to work on Windows, also add AppVeyor CI * Fix gcc jitter on Linux * Make the dse_crackme tests work on Windows * calling build and then install is less confusing than install twice * fix os.rename race condition on Windows * clean it up * Clean up after the unused cl.exe's artifacts * Use is_win instead of an additional check * Fix issue on Windows where 'w' and 'wb' modes are different * Address review feedback * setuptools is actually not required, so reverting
* Support of ARM SVC in the Miasm VMAdrien Guinet2018-07-172-1/+34
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* Jitter: use bignumFabrice Desclaux2018-07-138-167/+222
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* Toshiba MeP supportGuillaume Valadon2018-07-122-0/+695
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* JitCore x86: use uint64_t instead of double to store float_st*Ajax2018-07-101-8/+8
| | | | This avoid C cast when just saving and loading from the structure
* Add XMM0-15 to gpreg_dict[]acru3l2018-06-091-0/+17
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* Add support for XMM0-15 registers in x86Ajax2018-05-172-0/+87
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* MSP430: remove duplicate or unused operations implemAjax2018-05-161-12/+0
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* ARM 'clz' op is actually 'cntleadzeros', replace itAjax2018-05-162-18/+0
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* Move umod/udiv/imod/idiv operations to op_semanticsAjax2018-05-1610-159/+0
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* udiv/umod/idiv/imod: remove unused 'vmcpu' argumentAjax2018-05-166-50/+50
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* Extract operation semantics from 'vm_mngr' to dedicated 'op_semantics'Ajax2018-05-154-0/+4
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* Update Mips runtimeFabrice Desclaux2018-05-022-0/+35
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* Arm: add armt jitterFabrice Desclaux2018-04-182-0/+17
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* Arm: add some arm t2 instructionsFabrice Desclaux2018-04-182-0/+31
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* Add support for PowerPC 32bit big-endian processors: "ppc32b"Aymeric Vincent2018-02-263-0/+486
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* Jitter: fix exit return codeFabrice Desclaux2018-02-135-5/+5
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* Aarch64: add interrupt num & cpu accessesFabrice Desclaux2018-02-092-0/+11
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* X86: fix cdq/cbw...Fabrice Desclaux2018-02-021-0/+23
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* Fix BSR / BSL / CLZ implementation to avoid signed overflowAjax2018-01-261-1/+1
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* Merge pull request #538 from serpilliere/fix_cpu_reg_intCamille Mougey2017-04-271-2/+2
|\ | | | | Jitter: Error on reg set not int
| * Jitter: Error on reg set not intFabrice Desclaux2017-04-251-2/+2
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* | Jitter: sanitize codeFabrice Desclaux2017-04-245-27/+23
|/ | | | | Don't return 1337 on void python wrappers Add input sanity checks on python wrappers
* Jitter/arm: dump gpregs 32 bit outputFabrice Desclaux2017-04-041-4/+4
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* Add missing x86 offset for floatAjax2017-01-051-0/+3
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* Add missing offset for x86 archAjax2017-01-041-0/+5
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* Arm: fix bkptserpilliere2016-09-121-0/+1
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* Arm: add clz/uxtabserpilliere2016-09-122-0/+13
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* Code cleanupserpilliere2016-09-118-11/+11
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* Add interrupt_num to JitCore_x86_CPU attributesAjax2016-09-011-0/+3
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* Add exception_flags attribute to JitCore_CPU_x86 objectAjax2016-09-011-0/+5
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* Jitter: avoid vmmngr castingFabrice Desclaux2016-08-315-5/+5
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* Jitter: use mem read/write for memory breakpoint/automodFabrice Desclaux2016-08-301-8/+0
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* Jitter: automod callback CFabrice Desclaux2016-08-301-12/+1
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* Jitter: use local vars for prefetch/updtFabrice Desclaux2016-08-3010-1568/+3
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* Jitter/x86: custom dump_gpregsFabrice Desclaux2016-08-302-7/+37
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* Jitter: suport mips32Fabrice Desclaux2016-08-301-0/+1
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* X86/jitter: fix tsc reg gpregFabrice Desclaux2016-02-082-8/+8
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* X86/jitter: add tsc accessorsFabrice Desclaux2016-01-311-0/+17
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* Jitter/x86: add mmx helperFabrice Desclaux2015-12-231-0/+37
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* x86: add a new "register" named interrupt_numAjax2015-11-092-0/+22
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* Mips32: consider CPR0 as registers, able to JITCamille Mougey2015-10-271-0/+514
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