| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename miasm2 to miasm | Fabrice Desclaux | 2019-03-05 | 1 | -134/+0 |
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| * | Support python2/python3 | Fabrice Desclaux | 2019-03-05 | 1 | -17/+28 |
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| * | Fix typos & add codespell | Pierre LALET | 2018-12-23 | 1 | -3/+3 |
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| * | Adds Windows support and AppVeyor CI (#835) | Axel Souchet | 2018-09-09 | 1 | -8/+9 |
| | | | | | | | | | | | | | | | | | | | | | | | | | * Get miasm to work on Windows, also add AppVeyor CI * Fix gcc jitter on Linux * Make the dse_crackme tests work on Windows * calling build and then install is less confusing than install twice * fix os.rename race condition on Windows * clean it up * Clean up after the unused cl.exe's artifacts * Use is_win instead of an additional check * Fix issue on Windows where 'w' and 'wb' modes are different * Address review feedback * setuptools is actually not required, so reverting | ||||
| * | Update symbol_pool's deprecated API -> LocationDB | Ajax | 2018-07-03 | 1 | -1/+1 |
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| * | symbol_pool -> loc_db | Ajax | 2018-07-03 | 1 | -1/+1 |
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| * | Jitcore: remove useless strucs and rename for more meaningful names | Ajax | 2018-06-22 | 1 | -5/+5 |
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| * | Jitters: use loc_key instead of names or offset for basic block labeling | Ajax | 2018-06-22 | 1 | -3/+2 |
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| * | Core: replace AsmLabel by LocKey | Fabrice Desclaux | 2018-06-09 | 1 | -3/+5 |
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| * | Expr: Add new word ExprLoc | Fabrice Desclaux | 2018-06-08 | 1 | -2/+3 |
| | | | | | | This word represents a location in the binary. Thus, the hack of ExprId containing an AsmLabel ends here. | ||||
| * | PPC32: integration | Fabrice Desclaux | 2018-03-04 | 1 | -0/+1 |
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| * | Jit: merge duplicate hash code | Ajax | 2017-07-21 | 1 | -13/+1 |
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| * | Jitter: fix symb cache name (#525) | serpilliere | 2017-04-18 | 1 | -2/+2 |
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| * | Core/asmbloc: move asmbloc to asmblock | Fabrice Desclaux | 2017-03-13 | 1 | -1/+1 |
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| * | LLVM: handle max_exec_per_call option | Ajax | 2017-01-05 | 1 | -9/+0 |
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| * | LLVM: get rid of vm_mngr argument | Ajax | 2017-01-05 | 1 | -1/+1 |
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| * | LLVM: enable final object caching | Ajax | 2017-01-05 | 1 | -22/+59 |
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| * | LLVM: avoid going back to Python while next block are already jitted | Ajax | 2017-01-05 | 1 | -1/+2 |
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| * | Clean-up LLVM ModuleRef manipulation | Ajax | 2017-01-04 | 1 | -8/+2 |
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| * | Add support for aarch64 in LLVM | Ajax | 2017-01-04 | 1 | -1/+3 |
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| * | Adapt codegen.CGen principles to LLVM | Ajax | 2017-01-04 | 1 | -6/+10 |
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| * | LLVM Cache no more handled | Ajax | 2017-01-04 | 1 | -61/+0 |
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| * | Ugly modification to have llvm work again | Ajax | 2017-01-04 | 1 | -1/+9 |
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| * | PyLint: Remove relative imports | Camille Mougey | 2015-02-16 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | miasm2/jitter/jitload.py:17: [W0403(relative-import), ] Relative import 'jitcore_tcc', should be 'miasm2.jitter.jitcore_tcc' miasm2/jitter/jitload.py:22: [W0403(relative-import), ] Relative import 'jitcore_llvm', should be 'miasm2.jitter.jitcore_llvm' miasm2/jitter/jitload.py:27: [W0403(relative-import), ] Relative import 'jitcore_python', should be 'miasm2.jitter.jitcore_python' miasm2/jitter/jitcore.py:20: [W0403(relative-import), ] Relative import 'csts', should be 'miasm2.jitter.csts' miasm2/jitter/jitcore_tcc.py:7: [W0403(relative-import), ] Relative import 'jitcore', should be 'miasm2.jitter.jitcore' miasm2/jitter/jitcore_llvm.py:4: [W0403(relative-import), ] Relative import 'llvmconvert', should be 'miasm2.jitter.llvmconvert' miasm2/jitter/jitcore_llvm.py:5: [W0403(relative-import), ] Relative import 'jitcore', should be 'miasm2.jitter.jitcore' miasm2/jitter/loader/elf.py:7: [W0403(relative-import), ] Relative import 'utils', should be 'miasm2.jitter.loader.utils' miasm2/core/cpu.py:11: [W0403(relative-import), ] Relative import 'bin_stream', should be 'miasm2.core.bin_stream' miasm2/core/cpu.py:12: [W0403(relative-import), ] Relative import 'utils', should be 'miasm2.core.utils' miasm2/arch/sh4/arch.py:9: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.sh4.regs' miasm2/arch/msp430/sem.py:8: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.msp430.arch' miasm2/arch/arm/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.arm.regs' miasm2/arch/arm/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.arm.regs' miasm2/arch/arm/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.arm.arch' miasm2/arch/x86/sem.py:26: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/arch.py:9: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/disasm.py:3: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.x86.arch' miasm2/arch/mips32/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.mips32.regs' miasm2/arch/mips32/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.mips32.regs' miasm2/arch/mips32/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.mips32.arch' | ||||
| * | Jitter: unify import error | Fabrice Desclaux | 2014-12-03 | 1 | -4/+1 |
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| * | Modify irbloc destination mecanism. Rework API in consequence. | Fabrice Desclaux | 2014-09-05 | 1 | -7/+8 |
| | | | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon. | ||||
| * | mips: fix all_regs_ids_no_alias; fix llvm so | serpilliere | 2014-08-25 | 1 | -1/+2 |
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| * | Jitter: merge jitcoreARCH and vm_mngr | serpilliere | 2014-08-22 | 1 | -7/+5 |
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| * | Jitter LLVM: Add architecture dependent libs for ARM | ajax | 2014-06-13 | 1 | -1/+2 |
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| * | Miasm v2 | serpilliere | 2014-06-03 | 1 | -0/+157 |
| * API has changed, so old scripts need updates * See example for API usage * Use tcc or llvm for jit emulation * Go to test and run test_all.py to check install Enjoy ! | |||||