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* Rename miasm2 to miasmFabrice Desclaux2019-03-051-134/+0
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* Support python2/python3Fabrice Desclaux2019-03-051-17/+28
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* Fix typos & add codespellPierre LALET2018-12-231-3/+3
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* Adds Windows support and AppVeyor CI (#835)Axel Souchet2018-09-091-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | * Get miasm to work on Windows, also add AppVeyor CI * Fix gcc jitter on Linux * Make the dse_crackme tests work on Windows * calling build and then install is less confusing than install twice * fix os.rename race condition on Windows * clean it up * Clean up after the unused cl.exe's artifacts * Use is_win instead of an additional check * Fix issue on Windows where 'w' and 'wb' modes are different * Address review feedback * setuptools is actually not required, so reverting
* Update symbol_pool's deprecated API -> LocationDBAjax2018-07-031-1/+1
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* symbol_pool -> loc_dbAjax2018-07-031-1/+1
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* Jitcore: remove useless strucs and rename for more meaningful namesAjax2018-06-221-5/+5
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* Jitters: use loc_key instead of names or offset for basic block labelingAjax2018-06-221-3/+2
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* Core: replace AsmLabel by LocKeyFabrice Desclaux2018-06-091-3/+5
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* Expr: Add new word ExprLocFabrice Desclaux2018-06-081-2/+3
| | | | | This word represents a location in the binary. Thus, the hack of ExprId containing an AsmLabel ends here.
* PPC32: integrationFabrice Desclaux2018-03-041-0/+1
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* Jit: merge duplicate hash codeAjax2017-07-211-13/+1
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* Jitter: fix symb cache name (#525)serpilliere2017-04-181-2/+2
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* Core/asmbloc: move asmbloc to asmblockFabrice Desclaux2017-03-131-1/+1
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* LLVM: handle max_exec_per_call optionAjax2017-01-051-9/+0
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* LLVM: get rid of vm_mngr argumentAjax2017-01-051-1/+1
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* LLVM: enable final object cachingAjax2017-01-051-22/+59
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* LLVM: avoid going back to Python while next block are already jittedAjax2017-01-051-1/+2
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* Clean-up LLVM ModuleRef manipulationAjax2017-01-041-8/+2
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* Add support for aarch64 in LLVMAjax2017-01-041-1/+3
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* Adapt codegen.CGen principles to LLVMAjax2017-01-041-6/+10
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* LLVM Cache no more handledAjax2017-01-041-61/+0
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* Ugly modification to have llvm work againAjax2017-01-041-1/+9
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* PyLint: Remove relative importsCamille Mougey2015-02-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | miasm2/jitter/jitload.py:17: [W0403(relative-import), ] Relative import 'jitcore_tcc', should be 'miasm2.jitter.jitcore_tcc' miasm2/jitter/jitload.py:22: [W0403(relative-import), ] Relative import 'jitcore_llvm', should be 'miasm2.jitter.jitcore_llvm' miasm2/jitter/jitload.py:27: [W0403(relative-import), ] Relative import 'jitcore_python', should be 'miasm2.jitter.jitcore_python' miasm2/jitter/jitcore.py:20: [W0403(relative-import), ] Relative import 'csts', should be 'miasm2.jitter.csts' miasm2/jitter/jitcore_tcc.py:7: [W0403(relative-import), ] Relative import 'jitcore', should be 'miasm2.jitter.jitcore' miasm2/jitter/jitcore_llvm.py:4: [W0403(relative-import), ] Relative import 'llvmconvert', should be 'miasm2.jitter.llvmconvert' miasm2/jitter/jitcore_llvm.py:5: [W0403(relative-import), ] Relative import 'jitcore', should be 'miasm2.jitter.jitcore' miasm2/jitter/loader/elf.py:7: [W0403(relative-import), ] Relative import 'utils', should be 'miasm2.jitter.loader.utils' miasm2/core/cpu.py:11: [W0403(relative-import), ] Relative import 'bin_stream', should be 'miasm2.core.bin_stream' miasm2/core/cpu.py:12: [W0403(relative-import), ] Relative import 'utils', should be 'miasm2.core.utils' miasm2/arch/sh4/arch.py:9: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.sh4.regs' miasm2/arch/msp430/sem.py:8: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.msp430.regs' miasm2/arch/msp430/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.msp430.arch' miasm2/arch/arm/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.arm.regs' miasm2/arch/arm/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.arm.regs' miasm2/arch/arm/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.arm.arch' miasm2/arch/x86/sem.py:26: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/arch.py:9: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.x86.regs' miasm2/arch/x86/disasm.py:3: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.x86.arch' miasm2/arch/mips32/arch.py:10: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.mips32.regs' miasm2/arch/mips32/arch.py:11: [W0403(relative-import), ] Relative import 'regs', should be 'miasm2.arch.mips32.regs' miasm2/arch/mips32/disasm.py:2: [W0403(relative-import), ] Relative import 'arch', should be 'miasm2.arch.mips32.arch'
* Jitter: unify import errorFabrice Desclaux2014-12-031-4/+1
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* Modify irbloc destination mecanism. Rework API in consequence.Fabrice Desclaux2014-09-051-7/+8
| | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
* mips: fix all_regs_ids_no_alias; fix llvm soserpilliere2014-08-251-1/+2
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* Jitter: merge jitcoreARCH and vm_mngrserpilliere2014-08-221-7/+5
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* Jitter LLVM: Add architecture dependent libs for ARMajax2014-06-131-1/+2
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* Miasm v2serpilliere2014-06-031-0/+157
* API has changed, so old scripts need updates * See example for API usage * Use tcc or llvm for jit emulation * Go to test and run test_all.py to check install Enjoy !