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* Remove vm_ prefix /!\ API MODIFFabrice Desclaux2014-10-071-5/+5
| | | | | | | The jitter cpu/vm modules used an unecessary vm_ prefix for various api. jitter.cpu.vm_get_gpreg() => jitter.cpu.get_gpreg() jitter.vm.vm_get_mem... => jitter.vm.get_mem...
* JitCore Python: Handle log_regs, log_mnajax2014-09-261-0/+9
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* jitcore_python: fix reg initFabrice Desclaux2014-09-051-2/+2
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* Modify irbloc destination mecanism. Rework API in consequence.Fabrice Desclaux2014-09-051-7/+8
| | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
* Jitter Python: check all memory exceptions only on new instruction (in assembly)ajax2014-06-161-5/+13
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* Jitter Python: Init without alias (fix CPU update bug), manage memory exceptionsajax2014-06-161-1/+13
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* Jitter Python: Reorganize the Jit function builderajax2014-06-161-19/+48
| | | | | - Rewrite updates (engine and JitCpu) in subfunctions - Explode eval block in an eval_ir loop to gain more control
* Jit python: handle jump to ExprId (asm_label)serpilliere2014-06-161-2/+5
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* Jitter: Add basic write handling in Python Jitterajax2014-06-141-1/+39
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* Jitter: Add PoC jitter engine based on Miasm2 Symbolic execution engineajax2014-06-141-0/+100
This way, we hope to: - make symbexec more reliable - provide a full Python based Jitter (but *very* slow) Currently, memory writes, self-modiying code and exceptions aren't handled