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* Make python version explicitValentin Brandl2018-12-251-1/+1
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* Adds Windows support and AppVeyor CI (#835)Axel Souchet2018-09-091-45/+77
| | | | | | | | | | | | | | | | | | | | | | | | * Get miasm to work on Windows, also add AppVeyor CI * Fix gcc jitter on Linux * Make the dse_crackme tests work on Windows * calling build and then install is less confusing than install twice * fix os.rename race condition on Windows * clean it up * Clean up after the unused cl.exe's artifacts * Use is_win instead of an additional check * Fix issue on Windows where 'w' and 'wb' modes are different * Address review feedback * setuptools is actually not required, so reverting
* Add a module for Linux environment simulation + syscallsAjax2018-07-241-0/+1
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* Jitter: use bignumFabrice Desclaux2018-07-131-4/+19
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* Toshiba MeP supportGuillaume Valadon2018-07-121-0/+5
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* Remove TCC jitter engineAjax2018-05-161-86/+2
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* Extract operation semantics from 'vm_mngr' to dedicated 'op_semantics'Ajax2018-05-151-0/+12
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* Add support for PowerPC 32bit big-endian processors: "ppc32b"Aymeric Vincent2018-02-261-0/+13
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* Jitter: add gcc backendserpilliere2016-04-261-0/+4
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* Add arch aarch64Fabrice Desclaux2015-08-081-0/+9
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* Jitter: Factorize common cpu attributes in JitCpu; Update APIs in consequenceserpilliere2015-04-221-8/+8
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* Jitter: get/set mem is now wrapped in cpuserpilliere2015-04-221-0/+8
| | | | | The get/set mem used during jit is wrapped by cpu. This allows cpu object to callback (or not, depending on arch) a cache update.
* Jitter: split VmMngr from JitCpuserpilliere2015-03-101-24/+14
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* IR: Introduce Translators, an abstraction for IR translationCamille Mougey2014-12-141-0/+1
| | | | Translators exposes method to convert Miasm IR to others languages
* Jitter: move loader specific code to a submoduleFabrice Desclaux2014-12-031-0/+1
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* Move os_dep out of the jitter moduleFabrice Desclaux2014-10-071-1/+1
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* Modify irbloc destination mecanism. Rework API in consequence.Fabrice Desclaux2014-09-051-0/+8
| | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
* Jitter: add mips32l jitserpilliere2014-08-221-27/+18
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* Jitter: merge jitcoreARCH and vm_mngrserpilliere2014-08-221-3/+24
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* Add mips32 archserpilliere2014-08-061-0/+1
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* Miasm v2serpilliere2014-06-031-0/+135
| | | | | | | | | * API has changed, so old scripts need updates * See example for API usage * Use tcc or llvm for jit emulation * Go to test and run test_all.py to check install Enjoy !
* Send miasm v1 to hellserpilliere2014-06-031-62/+0
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* enable miasm installation without tccserpilliere2012-01-171-25/+58
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* realease commitserpilliere2011-07-271-0/+29