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* Add tests for MOVS and isThumb utility functionwoni2023-09-131-0/+51
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* Fix disassembly bugwoni2023-09-131-2/+2
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* Rename examples lifterFabrice Desclaux2020-12-251-6/+6
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* Rename arm lifterFabrice Desclaux2020-12-241-1/+1
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* Update api according to loc_db updateFabrice Desclaux2020-08-311-1/+2
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* Rename miasm2 to miasmFabrice Desclaux2019-03-051-6/+6
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* Support python2/python3Fabrice Desclaux2019-03-051-284/+287
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* Test: fix arm regression testsFabrice Desclaux2018-08-061-267/+267
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* IR: gen ircfg from ir_archFabrice Desclaux2018-07-051-5/+6
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* IR: remove default regs_init for symbexecFabrice Desclaux2018-07-051-1/+1
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* symbol_pool -> loc_dbAjax2018-07-031-3/+3
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* Expr: Add new word ExprLocFabrice Desclaux2018-06-081-2/+2
| | | | | This word represents a location in the binary. Thus, the hack of ExprId containing an AsmLabel ends here.
* Core: updt parser structureFabrice Desclaux2018-05-141-1/+3
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* Symbexec: use hashtable for mem symbolsFabrice Desclaux2018-03-151-1/+1
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* IR/Symbexec: rename symbexec to SymbolicExecutionEngineFabrice Desclaux2017-03-131-2/+2
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* use python2 as executable name, give adequate permissionsAymeric Vincent2017-01-051-1/+1
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* Expr: Remove exprint_fromFabrice Desclaux2016-12-231-1/+1
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* ExprCompose: add new apiFabrice Desclaux2016-11-041-1/+1
| | | | | | | The ExprComposes uses directly its arguments sizes to guess the slices locations. Old api: ExprCompose([(a, 0, 32), (b, 32, 64)]) becomes: ExprCompose(a, b)
* Symbexec: new api for emul_ir_*Fabrice Desclaux2016-11-041-1/+1
| | | | | | | | | | | | | | Replacement: emul_ir_bloc(self, myir, addr, step=False) by: emul_ir_block(self, addr, step=False) and: emul_ir_blocs(self, myir, addr, lbl_stop=None, step=False) by: emul_ir_blocks(self, addr, lbl_stop=None, step=False) The 'myir' was already given in the symbolexec creation.
* Expression: fix apiFabrice Desclaux2015-10-291-2/+2
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* arm: Add umull,umlal,smull,smlal to semWladimir J. van der Laan2015-01-261-0/+24
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* Arm: Fix cf in logical mnemonicsFabrice Desclaux2014-12-111-59/+170
| | | | /!\ TODO: CF is invalid in case of rotation in second argument.
* Arch/jit: add endianess support jittersFabrice Desclaux2014-10-091-4/+4
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* Arm: fix carry flag in sub operation; update reg testsFabrice Desclaux2014-10-061-24/+62
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* Modify irbloc destination mecanism. Rework API in consequence.Fabrice Desclaux2014-09-051-4/+4
| | | | | | | | | | Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
* Miasm v2serpilliere2014-06-031-0/+321
* API has changed, so old scripts need updates * See example for API usage * Use tcc or llvm for jit emulation * Go to test and run test_all.py to check install Enjoy !