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* Add MOV and MOVS tests for [AL]SRwoni2024-03-141-1/+6
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* Add tests for MOVS and isThumb utility functionwoni2023-09-131-0/+51
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* Fix disassembly bugwoni2023-09-131-2/+2
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* Fix html; Add reg testFabrice Desclaux2021-12-061-0/+2
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* Rename examples lifterFabrice Desclaux2020-12-251-6/+6
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* Rename arm lifterFabrice Desclaux2020-12-241-1/+1
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* Update api according to loc_db updateFabrice Desclaux2020-08-311-1/+2
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* Wrong conditional prefix for MRC/MCR (#1233)IridiumXOR2020-05-281-0/+5
| | | | | | | * Wrong conditional prefix for MRC/MCR Sorry, I have wrongly implemented the conditional code for MRC/MCR, now I have fix them. * Add test units for conditional MRC/MCR
* Add test units for MCR/MRCIridiumXOR2020-05-191-0/+4
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* pkhbtFabrice Desclaux2019-03-071-0/+10
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* Rename miasm2 to miasmFabrice Desclaux2019-03-052-9/+9
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* Support python2/python3Fabrice Desclaux2019-03-052-305/+311
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* Armt: fix cmnFabrice Desclaux2019-01-171-0/+2
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* ARM: add mnemonicsFabrice Desclaux2019-01-111-0/+12
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* Merge pull request #861 from jetsecurity/eor_immediateserpilliere2018-10-011-0/+3
|\ | | | | ARM Thumb: Add EOR (immediate) instruction
| * ARM Thumb: Add test for EOR (immediate) instructionjetsecurity2018-09-271-0/+3
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* | ARM Thumb: Add test for BLX Rd where Rd > R7jetsecurity2018-09-271-0/+3
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* Test: fix arm regression testsFabrice Desclaux2018-08-061-267/+267
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* Merge pull request #738 from marilafo/fix_offset_branch_armtlserpilliere2018-07-051-0/+3
|\ | | | | armtl change branch pc offset
| * armtl change branch pc offsetMarion Lafon2018-05-241-0/+3
| | | | | | | | Modify some armtl instr to match with documentation
* | IR: gen ircfg from ir_archFabrice Desclaux2018-07-051-5/+6
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* | IR: remove default regs_init for symbexecFabrice Desclaux2018-07-051-1/+1
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* | symbol_pool -> loc_dbAjax2018-07-032-7/+7
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* | Code cleaning: remove useless / commented codeAjax2018-06-211-62/+0
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* | Expr: Add new word ExprLocFabrice Desclaux2018-06-081-2/+2
|/ | | | | This word represents a location in the binary. Thus, the hack of ExprId containing an AsmLabel ends here.
* Core: updt parser structureFabrice Desclaux2018-05-142-3/+8
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* Arm: add dsbFabrice Desclaux2018-04-181-0/+3
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* Fix arm T32ExpandImmFabrice Desclaux2018-04-181-1/+2
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* Arm: add some arm t2 instructionsFabrice Desclaux2018-04-181-1/+213
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* Symbexec: use hashtable for mem symbolsFabrice Desclaux2018-03-151-1/+1
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* Armt: add instr nop/cps/wfiFabrice Desclaux2017-09-241-0/+11
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* Remove PYTHONSTARTUP in end-user scriptsAjax2017-04-241-5/+0
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* IR/Symbexec: rename symbexec to SymbolicExecutionEngineFabrice Desclaux2017-03-131-2/+2
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* use python2 as executable name, give adequate permissionsAymeric Vincent2017-01-051-1/+1
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* Expr: Remove exprint_fromFabrice Desclaux2016-12-231-1/+1
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* ExprCompose: add new apiFabrice Desclaux2016-11-041-1/+1
| | | | | | | The ExprComposes uses directly its arguments sizes to guess the slices locations. Old api: ExprCompose([(a, 0, 32), (b, 32, 64)]) becomes: ExprCompose(a, b)
* Symbexec: new api for emul_ir_*Fabrice Desclaux2016-11-041-1/+1
| | | | | | | | | | | | | | Replacement: emul_ir_bloc(self, myir, addr, step=False) by: emul_ir_block(self, addr, step=False) and: emul_ir_blocs(self, myir, addr, lbl_stop=None, step=False) by: emul_ir_blocks(self, addr, lbl_stop=None, step=False) The 'myir' was already given in the symbolexec creation.
* Arm: fix bkptserpilliere2016-09-121-2/+2
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* Arm: add clz/uxtabserpilliere2016-09-121-0/+6
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* Arch/armt: add pld instructionFabrice Desclaux2016-06-051-0/+5
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* Expression: fix apiFabrice Desclaux2015-10-291-2/+2
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* Arch/arm: add rev mnemonic;Fabrice Desclaux2015-10-071-0/+3
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* Cpu: modify instructions' offset relative encodingFabrice Desclaux2015-04-011-9/+9
| | | | | | | | | | | | | | | | | | | The assembler will automatically use instruction len in offset computation In the following instruction: 0x10: EB 02 JMP 0x14 If we assemble this instruction, the requested instruction send to the assembler engine will be: JMP +0x4 And will be encoded to: EB 02 Previously, the assembly of: JMP +0x4 was: EB 04
* arm: Add umull,umlal,smull,smlal to semWladimir J. van der Laan2015-01-261-0/+24
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* arm: Add instruction umlalWladimir J. van der Laan2015-01-241-0/+2
| | | | | umull, smull, smull and smlal are there, but not umlal (unsigned multiply and accumulate long)
* Arm: add instruction bfcFabrice Desclaux2015-01-121-0/+3
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* Arm: Fix cf in logical mnemonicsFabrice Desclaux2014-12-111-59/+170
| | | | /!\ TODO: CF is invalid in case of rotation in second argument.
* Arm: add mnemonic smullFabrice Desclaux2014-12-081-0/+5
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* Arch/jit: add endianess support jittersFabrice Desclaux2014-10-092-13/+13
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* Arm: fix carry flag in sub operation; update reg testsFabrice Desclaux2014-10-061-24/+62
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