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* Rename ir_arch for jitterFabrice Desclaux2020-12-252-25/+25
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* Update api according to loc_db updateFabrice Desclaux2020-08-312-3/+2
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* Avoid generate default locationdbFabrice Desclaux2020-08-314-23/+30
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* Rename elfesteem loaderFabrice Desclaux2019-03-051-1/+1
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* Include elfesteem fork in miasmPierre LALET2019-03-051-1/+1
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* Rename miasm2 to miasmFabrice Desclaux2019-03-057-16/+16
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* Support python2/python3Fabrice Desclaux2019-03-058-28/+33
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* Add x86 reg testsFabrice Desclaux2018-11-172-0/+252
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* Test: add pcmpeq and 128bit regs get/setFabrice Desclaux2018-09-192-2/+82
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* Test: add x86 64 asm test 64bit addrFabrice Desclaux2018-07-171-0/+30
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* Update symbol_pool's deprecated API -> LocationDBAjax2018-07-032-7/+7
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* symbol_pool -> loc_dbAjax2018-07-034-41/+41
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* Jitter: add simple trace apiFabrice Desclaux2018-06-211-7/+0
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* Core: replace AsmLabel by LocKeyFabrice Desclaux2018-06-093-34/+37
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* Add a regression test to ensure INT is called each time in a loopAjax2018-05-181-2/+8
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* Add support for XMM0-15 registers in x86Ajax2018-05-171-0/+16
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* Remove TCC jitter engineAjax2018-05-161-1/+1
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* Core: updt parser structureFabrice Desclaux2018-05-141-1/+0
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* X86: fix cdq/cbw...Fabrice Desclaux2018-02-021-0/+445
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* Add a regression test for DIV 128bitsAjax2017-06-272-0/+27
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* Test/X86: add push/pop regression testsFabrice Desclaux2017-05-171-1/+194
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* Core/asmbloc: move asmbloc to asmblockFabrice Desclaux2017-03-131-2/+2
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* All: rename vars bloc -> blockFabrice Desclaux2017-03-131-3/+3
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* Core/cpu: change ParseAst nameFabrice Desclaux2017-02-131-1/+1
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* Add regression test for CPUID supportAjax2017-02-021-0/+21
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* these files are not top level executables, adaptAymeric Vincent2017-01-051-8/+0
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* use python2 as executable name, give adequate permissionsAymeric Vincent2017-01-0517-17/+24
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* Jitter/win: fix TIB accessesFabrice Desclaux2016-09-061-2/+3
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* Regression test for SEH with a double handlerAjax2016-09-011-1/+41
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* Add a regression test for SEH handlingAjax2016-09-011-0/+66
| | | | | XOR EDX, EDX is used to obtain a 32bits 0 in FS:[0x0], because this is an ambiguity in Intel representation
* Test: TCC conditional testsserpilliere2016-04-2617-35/+58
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* X86/test: add pusha/popaFabrice Desclaux2016-04-181-0/+125
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* X86/test: updt test apiFabrice Desclaux2016-04-1816-51/+86
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* Test: add x86 reg testFabrice Desclaux2016-01-061-0/+26
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* Test: add x86 reg testFabrice Desclaux2015-12-241-0/+25
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* Test: add x86 reg testFabrice Desclaux2015-12-241-0/+25
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* Test: add x86 reg testFabrice Desclaux2015-12-241-1/+62
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* Test: add x86 reg testFabrice Desclaux2015-12-241-0/+63
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* Test: add x86 reg testFabrice Desclaux2015-12-241-0/+64
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* Test: add x86 reg testFabrice Desclaux2015-12-241-0/+25
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* Test: add x86 reg testFabrice Desclaux2015-12-241-0/+25
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* Test: add x86 reg testFabrice Desclaux2015-12-242-0/+80
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* Test: add a unit test for x86 interrupt_numAjax2015-11-091-0/+31
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* Core/parse_asm: update parse_txt API useserpilliere2015-10-291-1/+1
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* Test/sem: add daa/dasFabrice Desclaux2015-07-292-0/+182
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* X86/Test: add stack unit testserpilliere2015-07-201-0/+60
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* Clean: remove unecessary ast_parser modificationFabrice Desclaux2015-04-011-12/+0
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* Asmbloc: updt asmbloc apiFabrice Desclaux2015-04-011-2/+1
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* Arch/jit: add endianess support jittersFabrice Desclaux2014-10-091-1/+1
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* Remove vm_ prefix /!\ API MODIFFabrice Desclaux2014-10-071-2/+2
| | | | | | | The jitter cpu/vm modules used an unecessary vm_ prefix for various api. jitter.cpu.vm_get_gpreg() => jitter.cpu.get_gpreg() jitter.vm.vm_get_mem... => jitter.vm.get_mem...