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* Add PADDSB/PADDSW instructionAjax2018-02-091-0/+10
| | | | | | | NP 0F EC /r PADDSB mm, mm/m64 66 0F EC /r PADDSB xmm1, xmm2/m128 NP 0F ED /r PADDSW mm, mm/m64 66 0F ED /r PADDSW xmm1, xmm2/m128
* Add PSUBSB/PSUBSW instructionAjax2018-02-091-0/+10
| | | | | | | NP 0F E8 /r PSUBSB mm, mm/m64 66 0F E8 /r PSUBSB xmm1, xmm2/m128 NP 0F E9 /r PSUBSW mm, mm/m64 66 0F E9 /r PSUBSW xmm1, xmm2/m128
* Add PMULHW / PMULHUW instructionAjax2018-02-091-0/+10
| | | | | | | 0F E5 /r PMULHW mm, mm/m64 66 0F E5 /r PMULHW xmm1, xmm2/m128 NP 0F E4 /r PMULHUW mm1, mm2/m64 66 0F E4 /r PMULHUW xmm1, xmm2/m128
* Add PADDUSB/PADDUSW instructionAjax2018-02-091-0/+9
| | | | | 0F DC /r PADDUSB mm, mm/m64 66 0F DC /r PADDUSB xmm1, xmm2/m128
* Add PSUBSUB/PSUBUSW instrAjax2018-02-091-0/+11
| | | | | 0F D8 /r PSUBUSB mm, mm/m64 66 0F D8 /r PSUBUSB xmm1, xmm2/m128
* Add PMULLW instructionAjax2018-02-091-0/+5
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* Add PACKSSDW instructionAjax2018-02-091-0/+5
| | | | | 0F 6B /r PACKSSDW mm1, mm2/m64 66 0F 6B /r PACKSSDW xmm1, xmm2/m128
* Add PACKUSWB instructionAjax2018-02-091-0/+5
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* Add PACKSSWB instructionAjax2018-02-091-0/+4
| | | | | 0F 63 /r PACKSSWB mm1, mm2/m64 66 0F 63 /r PACKSSWB xmm1, xmm2/m128
* X86: fix cdq/cbw...Fabrice Desclaux2018-02-021-0/+445
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* Add PCMPGTB instructionAjax2018-01-261-0/+3
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* Add PALIGNR x86 instruction (asm & semantic)Ajax2018-01-261-0/+3
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* Add support for BNDMOV instruction (with an empty semantic)Ajax2018-01-261-0/+5
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* X86: add mfence/sfence/prefetchFabrice Desclaux2017-12-301-0/+4
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* update tests to use the new spacing of expressions' str()Aymeric Vincent2017-12-122-257/+257
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* Armt: add instr nop/cps/wfiFabrice Desclaux2017-09-241-0/+11
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* X86: add instr pcmpFabrice Desclaux2017-09-011-0/+6
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* X86: add instr aesFabrice Desclaux2017-09-011-0/+9
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* X86: fix sib generationFabrice Desclaux2017-09-011-0/+8
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* Aarch64: complete DecodeBitMasks test for full branch coverageAjax2017-07-241-0/+4
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* IR: rename add_blocFabrice Desclaux2017-07-071-1/+1
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* Add a regression test for DIV 128bitsAjax2017-06-272-0/+27
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* Test/X86: add push/pop regression testsFabrice Desclaux2017-05-171-1/+194
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* Remove absolute sys.pathAjax2017-04-241-3/+0
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* Remove PYTHONSTARTUP in end-user scriptsAjax2017-04-246-35/+2
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* Introduce a naive "System V" calling conventionAjax2017-04-061-4/+4
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* Aarch64: fix ldrFabrice Desclaux2017-04-061-1/+7
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* Core/asmbloc: move asmbloc to asmblockFabrice Desclaux2017-03-134-8/+8
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* All: rename vars bloc -> blockFabrice Desclaux2017-03-134-12/+12
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* IR/Symbexec: rename symbexec to SymbolicExecutionEngineFabrice Desclaux2017-03-133-6/+6
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* Core/cpu: change ParseAst nameFabrice Desclaux2017-02-134-5/+5
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* X86: add pslldqFabrice Desclaux2017-02-031-0/+3
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* X86: fix rex_r in reg argsFabrice Desclaux2017-02-031-0/+8
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* Add regression test for CPUID supportAjax2017-02-021-0/+21
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* these files are not top level executables, adaptAymeric Vincent2017-01-053-24/+0
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* use python2 as executable name, give adequate permissionsAymeric Vincent2017-01-0522-22/+31
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* Expr: Remove exprint_fromFabrice Desclaux2016-12-233-14/+14
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* ExprCompose: add new apiFabrice Desclaux2016-11-041-1/+1
| | | | | | | The ExprComposes uses directly its arguments sizes to guess the slices locations. Old api: ExprCompose([(a, 0, 32), (b, 32, 64)]) becomes: ExprCompose(a, b)
* Symbexec: new api for emul_ir_*Fabrice Desclaux2016-11-043-3/+3
| | | | | | | | | | | | | | Replacement: emul_ir_bloc(self, myir, addr, step=False) by: emul_ir_block(self, addr, step=False) and: emul_ir_blocs(self, myir, addr, lbl_stop=None, step=False) by: emul_ir_blocks(self, addr, lbl_stop=None, step=False) The 'myir' was already given in the symbolexec creation.
* Os_dep: fix get/set strFabrice Desclaux2016-09-291-3/+3
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* Arm: fix bkptserpilliere2016-09-121-2/+2
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* Arm: add clz/uxtabserpilliere2016-09-121-0/+6
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* Arch/x86: fix sldtFabrice Desclaux2016-09-071-1/+5
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* Jitter/win: fix TIB accessesFabrice Desclaux2016-09-061-2/+3
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* Regression test for SEH with a double handlerAjax2016-09-011-1/+41
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* Add a regression test for SEH handlingAjax2016-09-011-0/+66
| | | | | XOR EDX, EDX is used to obtain a 32bits 0 in FS:[0x0], because this is an ambiguity in Intel representation
* X86: fix pextrwFabrice Desclaux2016-08-041-0/+3
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* X86: add setalcFabrice Desclaux2016-07-291-0/+2
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* X86: add no_rex/fix xchgFabrice Desclaux2016-06-191-0/+3
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* Arch/armt: add pld instructionFabrice Desclaux2016-06-051-0/+5
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