| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Add PADDSB/PADDSW instruction | Ajax | 2018-02-09 | 1 | -0/+10 | |
| | | | | | | | | NP 0F EC /r PADDSB mm, mm/m64 66 0F EC /r PADDSB xmm1, xmm2/m128 NP 0F ED /r PADDSW mm, mm/m64 66 0F ED /r PADDSW xmm1, xmm2/m128 | |||||
| * | Add PSUBSB/PSUBSW instruction | Ajax | 2018-02-09 | 1 | -0/+10 | |
| | | | | | | | | NP 0F E8 /r PSUBSB mm, mm/m64 66 0F E8 /r PSUBSB xmm1, xmm2/m128 NP 0F E9 /r PSUBSW mm, mm/m64 66 0F E9 /r PSUBSW xmm1, xmm2/m128 | |||||
| * | Add PMULHW / PMULHUW instruction | Ajax | 2018-02-09 | 1 | -0/+10 | |
| | | | | | | | | 0F E5 /r PMULHW mm, mm/m64 66 0F E5 /r PMULHW xmm1, xmm2/m128 NP 0F E4 /r PMULHUW mm1, mm2/m64 66 0F E4 /r PMULHUW xmm1, xmm2/m128 | |||||
| * | Add PADDUSB/PADDUSW instruction | Ajax | 2018-02-09 | 1 | -0/+9 | |
| | | | | | | 0F DC /r PADDUSB mm, mm/m64 66 0F DC /r PADDUSB xmm1, xmm2/m128 | |||||
| * | Add PSUBSUB/PSUBUSW instr | Ajax | 2018-02-09 | 1 | -0/+11 | |
| | | | | | | 0F D8 /r PSUBUSB mm, mm/m64 66 0F D8 /r PSUBUSB xmm1, xmm2/m128 | |||||
| * | Add PMULLW instruction | Ajax | 2018-02-09 | 1 | -0/+5 | |
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| * | Add PACKSSDW instruction | Ajax | 2018-02-09 | 1 | -0/+5 | |
| | | | | | | 0F 6B /r PACKSSDW mm1, mm2/m64 66 0F 6B /r PACKSSDW xmm1, xmm2/m128 | |||||
| * | Add PACKUSWB instruction | Ajax | 2018-02-09 | 1 | -0/+5 | |
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| * | Add PACKSSWB instruction | Ajax | 2018-02-09 | 1 | -0/+4 | |
| | | | | | | 0F 63 /r PACKSSWB mm1, mm2/m64 66 0F 63 /r PACKSSWB xmm1, xmm2/m128 | |||||
| * | X86: fix cdq/cbw... | Fabrice Desclaux | 2018-02-02 | 1 | -0/+445 | |
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| * | Add PCMPGTB instruction | Ajax | 2018-01-26 | 1 | -0/+3 | |
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| * | Add PALIGNR x86 instruction (asm & semantic) | Ajax | 2018-01-26 | 1 | -0/+3 | |
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| * | Add support for BNDMOV instruction (with an empty semantic) | Ajax | 2018-01-26 | 1 | -0/+5 | |
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| * | X86: add mfence/sfence/prefetch | Fabrice Desclaux | 2017-12-30 | 1 | -0/+4 | |
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| * | update tests to use the new spacing of expressions' str() | Aymeric Vincent | 2017-12-12 | 2 | -257/+257 | |
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| * | Armt: add instr nop/cps/wfi | Fabrice Desclaux | 2017-09-24 | 1 | -0/+11 | |
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| * | X86: add instr pcmp | Fabrice Desclaux | 2017-09-01 | 1 | -0/+6 | |
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| * | X86: add instr aes | Fabrice Desclaux | 2017-09-01 | 1 | -0/+9 | |
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| * | X86: fix sib generation | Fabrice Desclaux | 2017-09-01 | 1 | -0/+8 | |
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| * | Aarch64: complete DecodeBitMasks test for full branch coverage | Ajax | 2017-07-24 | 1 | -0/+4 | |
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| * | IR: rename add_bloc | Fabrice Desclaux | 2017-07-07 | 1 | -1/+1 | |
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| * | Add a regression test for DIV 128bits | Ajax | 2017-06-27 | 2 | -0/+27 | |
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| * | Test/X86: add push/pop regression tests | Fabrice Desclaux | 2017-05-17 | 1 | -1/+194 | |
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| * | Remove absolute sys.path | Ajax | 2017-04-24 | 1 | -3/+0 | |
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| * | Remove PYTHONSTARTUP in end-user scripts | Ajax | 2017-04-24 | 6 | -35/+2 | |
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| * | Introduce a naive "System V" calling convention | Ajax | 2017-04-06 | 1 | -4/+4 | |
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| * | Aarch64: fix ldr | Fabrice Desclaux | 2017-04-06 | 1 | -1/+7 | |
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| * | Core/asmbloc: move asmbloc to asmblock | Fabrice Desclaux | 2017-03-13 | 4 | -8/+8 | |
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| * | All: rename vars bloc -> block | Fabrice Desclaux | 2017-03-13 | 4 | -12/+12 | |
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| * | IR/Symbexec: rename symbexec to SymbolicExecutionEngine | Fabrice Desclaux | 2017-03-13 | 3 | -6/+6 | |
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| * | Core/cpu: change ParseAst name | Fabrice Desclaux | 2017-02-13 | 4 | -5/+5 | |
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| * | X86: add pslldq | Fabrice Desclaux | 2017-02-03 | 1 | -0/+3 | |
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| * | X86: fix rex_r in reg args | Fabrice Desclaux | 2017-02-03 | 1 | -0/+8 | |
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| * | Add regression test for CPUID support | Ajax | 2017-02-02 | 1 | -0/+21 | |
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| * | these files are not top level executables, adapt | Aymeric Vincent | 2017-01-05 | 3 | -24/+0 | |
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| * | use python2 as executable name, give adequate permissions | Aymeric Vincent | 2017-01-05 | 22 | -22/+31 | |
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| * | Expr: Remove exprint_from | Fabrice Desclaux | 2016-12-23 | 3 | -14/+14 | |
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| * | ExprCompose: add new api | Fabrice Desclaux | 2016-11-04 | 1 | -1/+1 | |
| | | | | | | | | The ExprComposes uses directly its arguments sizes to guess the slices locations. Old api: ExprCompose([(a, 0, 32), (b, 32, 64)]) becomes: ExprCompose(a, b) | |||||
| * | Symbexec: new api for emul_ir_* | Fabrice Desclaux | 2016-11-04 | 3 | -3/+3 | |
| | | | | | | | | | | | | | | | Replacement: emul_ir_bloc(self, myir, addr, step=False) by: emul_ir_block(self, addr, step=False) and: emul_ir_blocs(self, myir, addr, lbl_stop=None, step=False) by: emul_ir_blocks(self, addr, lbl_stop=None, step=False) The 'myir' was already given in the symbolexec creation. | |||||
| * | Os_dep: fix get/set str | Fabrice Desclaux | 2016-09-29 | 1 | -3/+3 | |
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| * | Arm: fix bkpt | serpilliere | 2016-09-12 | 1 | -2/+2 | |
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| * | Arm: add clz/uxtab | serpilliere | 2016-09-12 | 1 | -0/+6 | |
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| * | Arch/x86: fix sldt | Fabrice Desclaux | 2016-09-07 | 1 | -1/+5 | |
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| * | Jitter/win: fix TIB accesses | Fabrice Desclaux | 2016-09-06 | 1 | -2/+3 | |
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| * | Regression test for SEH with a double handler | Ajax | 2016-09-01 | 1 | -1/+41 | |
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| * | Add a regression test for SEH handling | Ajax | 2016-09-01 | 1 | -0/+66 | |
| | | | | | | XOR EDX, EDX is used to obtain a 32bits 0 in FS:[0x0], because this is an ambiguity in Intel representation | |||||
| * | X86: fix pextrw | Fabrice Desclaux | 2016-08-04 | 1 | -0/+3 | |
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| * | X86: add setalc | Fabrice Desclaux | 2016-07-29 | 1 | -0/+2 | |
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| * | X86: add no_rex/fix xchg | Fabrice Desclaux | 2016-06-19 | 1 | -0/+3 | |
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| * | Arch/armt: add pld instruction | Fabrice Desclaux | 2016-06-05 | 1 | -0/+5 | |
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