From 6e09df71a333bf87cd68c2d08ad068a3e501462d Mon Sep 17 00:00:00 2001 From: Fabrice Desclaux Date: Fri, 5 Sep 2014 11:30:05 +0200 Subject: Modify irbloc destination mecanism. Rework API in consequence. Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon. --- example/expression/manip_expression2.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'example/expression/manip_expression2.py') diff --git a/example/expression/manip_expression2.py b/example/expression/manip_expression2.py index 4153f875..faa3f9df 100644 --- a/example/expression/manip_expression2.py +++ b/example/expression/manip_expression2.py @@ -7,20 +7,20 @@ Get read/written registers for a given instruction """ arch = mn_x86 -my_ir = ir_a_x86_32() +ir_arch = ir_a_x86_32() l = arch.fromstring('LODSB', 32) l.offset, l.l = 0, 15 -my_ir.add_instr(l) +ir_arch.add_instr(l) print '*' * 80 -for lbl, b in my_ir.blocs.items(): +for lbl, b in ir_arch.blocs.items(): print b for irs in b.irs: o_r, o_w = get_rw(irs) print 'read: ', [str(x) for x in o_r] print 'written:', [str(x) for x in o_w] print -my_ir.gen_graph() -g = my_ir.graph() +ir_arch.gen_graph() +g = ir_arch.graph() open('graph_instr.txt', 'w').write(g) -- cgit 1.4.1