From 3b339448178ba2ff41bda606829deacc21df7198 Mon Sep 17 00:00:00 2001 From: Fabrice Desclaux Date: Tue, 19 Jun 2018 17:01:20 +0200 Subject: All: fix var name to reflect object types --- example/disasm/file.py | 4 ++-- example/ida/ctype_propagation.py | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'example') diff --git a/example/disasm/file.py b/example/disasm/file.py index 88ba6162..196e1b1a 100644 --- a/example/disasm/file.py +++ b/example/disasm/file.py @@ -13,6 +13,6 @@ cont = Container.from_stream(open(sys.argv[1])) mdis = dis_x86_32(cont.bin_stream) # Inform the engine to avoid disassembling null instructions mdis.dont_dis_nulstart_bloc = True -blocks = mdis.dis_multiblock(addr) +asmcfg = mdis.dis_multiblock(addr) -open('graph.dot', 'w').write(blocks.dot()) +open('graph.dot', 'w').write(asmcfg.dot()) diff --git a/example/ida/ctype_propagation.py b/example/ida/ctype_propagation.py index d35835dc..db324833 100644 --- a/example/ida/ctype_propagation.py +++ b/example/ida/ctype_propagation.py @@ -268,7 +268,6 @@ def analyse_function(): iraCallStackFixer = get_ira_call_fixer(ira) ir_arch = iraCallStackFixer(mdis.symbol_pool) - asmcfg = mdis.dis_multiblock(addr) # Generate IR for block in asmcfg.blocks: -- cgit 1.4.1 From c6462990df3773ed4bdf82f7dc3b30f1c6331a81 Mon Sep 17 00:00:00 2001 From: Fabrice Desclaux Date: Tue, 19 Jun 2018 17:36:58 +0200 Subject: Jitter: add simple trace api --- README.md | 3 +-- example/jitter/mips32.py | 17 +++++++---------- example/jitter/msp430.py | 15 +++++++-------- example/jitter/x86_32.py | 3 +-- miasm2/analysis/sandbox.py | 11 +++++------ miasm2/jitter/jitload.py | 18 ++++++++++++++++++ test/analysis/dse.py | 3 +-- test/arch/aarch64/unit/asm_test.py | 5 ----- test/arch/mips32/unit/asm_test.py | 3 --- test/arch/x86/unit/asm_test.py | 7 ------- test/jitter/bad_block.py | 3 +-- test/jitter/jit_options.py | 3 +-- test/jitter/jmp_out_mem.py | 3 +-- test/jitter/test_post_instr.py | 4 ++-- 14 files changed, 45 insertions(+), 53 deletions(-) (limited to 'example') diff --git a/README.md b/README.md index 570bee22..498b2f02 100644 --- a/README.md +++ b/README.md @@ -217,8 +217,7 @@ def code_sentinelle(jitter): Active logs: ``` ->>> jitter.jit.log_regs = True ->>> jitter.jit.log_mn = True +>>> jitter.set_trace_log() ``` Run at arbitrary address: diff --git a/example/jitter/mips32.py b/example/jitter/mips32.py index c5b2f7f5..31ab03c8 100755 --- a/example/jitter/mips32.py +++ b/example/jitter/mips32.py @@ -5,16 +5,11 @@ from miasm2.analysis import debugging from miasm2.jitter.csts import * from miasm2.analysis.machine import Machine -from pdb import pm - parser = ArgumentParser( description="""Sandbox raw binary with mips32 engine (ex: jit_mips32.py example/mips32_sc_l.bin 0)""") -parser.add_argument("-r", "--log-regs", - help="Log registers value for each instruction", - action="store_true") -parser.add_argument("-m", "--log-mn", - help="Log desassembly conversion for each instruction", +parser.add_argument("-t", "--trace", + help="Log instructions/registers values", action="store_true") parser.add_argument("-n", "--log-newbloc", help="Log basic blocks processed by the Jitter", @@ -43,9 +38,11 @@ def jit_mips32_binary(args): myjit.init_stack() # Log level (if available with jitter engine) - myjit.jit.log_regs = args.log_regs - myjit.jit.log_mn = args.log_mn - myjit.jit.log_newbloc = args.log_newbloc + myjit.set_trace_log( + trace_instr=args.trace, + trace_regs=args.trace, + trace_new_blocks=args.log_newbloc + ) myjit.vm.add_memory_page(0, PAGE_READ | PAGE_WRITE, open(filepath).read()) myjit.add_breakpoint(0x1337BEEF, code_sentinelle) diff --git a/example/jitter/msp430.py b/example/jitter/msp430.py index 6dd67542..2f9b8649 100755 --- a/example/jitter/msp430.py +++ b/example/jitter/msp430.py @@ -8,11 +8,8 @@ from miasm2.analysis.machine import Machine parser = ArgumentParser( description="""Sandbox raw binary with msp430 engine (ex: jit_msp430.py example/msp430_sc.bin 0)""") -parser.add_argument("-r", "--log-regs", - help="Log registers value for each instruction", - action="store_true") -parser.add_argument("-m", "--log-mn", - help="Log desassembly conversion for each instruction", +parser.add_argument("-t", "--trace", + help="Log instructions/registers values", action="store_true") parser.add_argument("-n", "--log-newbloc", help="Log basic blocks processed by the Jitter", @@ -36,9 +33,11 @@ def jit_msp430_binary(args): myjit.init_stack() # Log level (if available with jitter engine) - myjit.jit.log_regs = args.log_regs - myjit.jit.log_mn = args.log_mn - myjit.jit.log_newbloc = args.log_newbloc + myjit.set_trace_log( + trace_instr=args.trace, + trace_regs=args.trace, + trace_new_blocks=args.log_newbloc + ) myjit.vm.add_memory_page(0, PAGE_READ | PAGE_WRITE, open(filepath, "rb").read()) myjit.add_breakpoint(0x1337, lambda _: exit(0)) diff --git a/example/jitter/x86_32.py b/example/jitter/x86_32.py index 1409d7aa..5272f732 100644 --- a/example/jitter/x86_32.py +++ b/example/jitter/x86_32.py @@ -24,8 +24,7 @@ data = open(args.filename).read() run_addr = 0x40000000 myjit.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) -myjit.jit.log_regs = True -myjit.jit.log_mn = True +myjit.set_trace_log() myjit.push_uint32_t(0x1337beef) myjit.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/miasm2/analysis/sandbox.py b/miasm2/analysis/sandbox.py index e77b1669..b1147adb 100644 --- a/miasm2/analysis/sandbox.py +++ b/miasm2/analysis/sandbox.py @@ -57,16 +57,15 @@ class Sandbox(object): cls.__init__(self, **kwargs) # Logging options - if self.options.singlestep: - self.jitter.jit.log_mn = True - self.jitter.jit.log_regs = True + self.jitter.set_trace_log( + trace_instr=self.options.singlestep, + trace_regs=self.options.singlestep, + trace_new_blocks=self.options.dumpblocs + ) if not self.options.quiet_function_calls: log_func.setLevel(logging.INFO) - if self.options.dumpblocs: - self.jitter.jit.log_newbloc = True - @classmethod def parser(cls, *args, **kwargs): """ diff --git a/miasm2/jitter/jitload.py b/miasm2/jitter/jitload.py index 28200997..62df5b3c 100644 --- a/miasm2/jitter/jitload.py +++ b/miasm2/jitter/jitload.py @@ -484,3 +484,21 @@ class jitter(object): self.symbexec.update_cpu_from_engine() return ret + + def set_trace_log(self, + trace_instr=True, trace_regs=True, + trace_new_blocks=False): + """ + Activate/Deactivate trace log options + + @trace_instr: activate instructions tracing log + @trace_regs: activate registers tracing log + @trace_new_blocks: dump new code blocks log + """ + + # As trace state changes, clear already jitted blocks + self.jit.clear_jitted_blocks() + + self.jit.log_mn = trace_instr + self.jit.log_regs = trace_regs + self.jit.log_newbloc = trace_new_blocks diff --git a/test/analysis/dse.py b/test/analysis/dse.py index 5a72db34..4367f6f7 100644 --- a/test/analysis/dse.py +++ b/test/analysis/dse.py @@ -34,8 +34,7 @@ class DSETest(object): self.myjit = jitter(jitter_engine) self.myjit.init_stack() - self.myjit.jit.log_regs = True - self.myjit.jit.log_mn = True + self.myjit.set_trace_log() self.dse = None self.assembly = None diff --git a/test/arch/aarch64/unit/asm_test.py b/test/arch/aarch64/unit/asm_test.py index ca27ef9d..437a8056 100644 --- a/test/arch/aarch64/unit/asm_test.py +++ b/test/arch/aarch64/unit/asm_test.py @@ -16,16 +16,11 @@ class Asm_Test(object): self.myjit = Machine("aarch64l").jitter(jitter) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - - def __call__(self): self.asm() self.run() self.check() - def asm(self): blocks, symbol_pool = parse_asm.parse_txt(mn_aarch64, 'l', self.TXT, symbol_pool = self.myjit.ir_arch.symbol_pool) diff --git a/test/arch/mips32/unit/asm_test.py b/test/arch/mips32/unit/asm_test.py index f03a32d7..a2203783 100644 --- a/test/arch/mips32/unit/asm_test.py +++ b/test/arch/mips32/unit/asm_test.py @@ -18,9 +18,6 @@ class Asm_Test(object): self.myjit = Machine("mips32l").jitter(jitter) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - def __call__(self): self.asm() self.run() diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index 961967f9..4b802606 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -18,9 +18,6 @@ class Asm_Test(object): self.myjit = Machine(self.arch_name).jitter(jitter_engine) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - def test_init(self): pass @@ -81,10 +78,6 @@ class Asm_Test_16(Asm_Test): self.myjit.stack_size = 0x1000 self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - - def init_machine(self): self.myjit.vm.add_memory_page(self.run_addr, PAGE_READ | PAGE_WRITE, self.assembly) self.myjit.push_uint16_t(self.ret_addr) diff --git a/test/jitter/bad_block.py b/test/jitter/bad_block.py index 04c1f475..ae11e696 100644 --- a/test/jitter/bad_block.py +++ b/test/jitter/bad_block.py @@ -32,8 +32,7 @@ run_addr = 0x40000000 jitter.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) -jitter.jit.log_regs = True -jitter.jit.log_mn = True +jitter.set_trace_log() jitter.push_uint32_t(0x1337beef) jitter.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/test/jitter/jit_options.py b/test/jitter/jit_options.py index 4fe936d5..a0ddbc11 100644 --- a/test/jitter/jit_options.py +++ b/test/jitter/jit_options.py @@ -33,8 +33,7 @@ def init_jitter(): # Init jitter myjit.init_stack() - myjit.jit.log_regs = True - myjit.jit.log_mn = True + myjit.set_trace_log() myjit.push_uint32_t(0x1337beef) myjit.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/test/jitter/jmp_out_mem.py b/test/jitter/jmp_out_mem.py index 49da16ad..93ae8304 100644 --- a/test/jitter/jmp_out_mem.py +++ b/test/jitter/jmp_out_mem.py @@ -35,8 +35,7 @@ run_addr = 0x40000000 jitter.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) -jitter.jit.log_regs = True -jitter.jit.log_mn = True +jitter.set_trace_log() jitter.push_uint32_t(0x1337beef) jitter.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/test/jitter/test_post_instr.py b/test/jitter/test_post_instr.py index edf86645..39e87616 100644 --- a/test/jitter/test_post_instr.py +++ b/test/jitter/test_post_instr.py @@ -23,8 +23,8 @@ jitter.vm.add_memory_page(0x1000, PAGE_READ|PAGE_WRITE, "\x00"*0x1000, "code pag # RET jitter.vm.set_mem(0x1000, "B844332211C3".decode('hex')) -jitter.jit.log_mn = True -jitter.jit.log_regs = True + +jitter.set_trace_log() def do_not_raise_me(jitter): raise ValueError("Should not be here") -- cgit 1.4.1 From b8d5b255bad4b03c57356c9af474e6d8a12105db Mon Sep 17 00:00:00 2001 From: Ajax Date: Thu, 21 Jun 2018 17:33:47 +0200 Subject: Code cleaning: remove useless / commented code --- example/expression/simplification_tools.py | 1 - example/ida/graph_ir.py | 1 - miasm2/analysis/data_analysis.py | 62 ------------------------------ miasm2/analysis/debugging.py | 2 +- miasm2/analysis/disasm_cb.py | 13 ------- miasm2/arch/arm/arch.py | 6 --- miasm2/arch/arm/sem.py | 3 -- miasm2/arch/msp430/sem.py | 1 - miasm2/jitter/loader/elf.py | 2 - test/analysis/data_flow.py | 1 - test/analysis/depgraph.py | 2 +- test/arch/arm/arch.py | 62 ------------------------------ test/arch/mips32/arch.py | 4 -- test/arch/msp430/arch.py | 4 -- test/arch/sh4/arch.py | 4 -- test/arch/x86/arch.py | 7 ---- 16 files changed, 2 insertions(+), 173 deletions(-) (limited to 'example') diff --git a/example/expression/simplification_tools.py b/example/expression/simplification_tools.py index 7c15b3e7..cb062fb3 100644 --- a/example/expression/simplification_tools.py +++ b/example/expression/simplification_tools.py @@ -32,7 +32,6 @@ x = ExprMem(a + b + ExprInt(0x42, 32), 32) def replace_expr(e): - # print 'visit', e dct = {c + ExprInt(0x42, 32): d, a + b: c, } if e in dct: diff --git a/example/ida/graph_ir.py b/example/ida/graph_ir.py index 97d30851..dd842281 100644 --- a/example/ida/graph_ir.py +++ b/example/ida/graph_ir.py @@ -116,7 +116,6 @@ def build_graph(verbose=False, simplify=False): # populate symbols with ida names for addr, name in idautils.Names(): - # print hex(ad), repr(name) if name is None: continue if (mdis.symbol_pool.getby_offset(addr) or diff --git a/miasm2/analysis/data_analysis.py b/miasm2/analysis/data_analysis.py index 5e88665e..0782c12c 100644 --- a/miasm2/analysis/data_analysis.py +++ b/miasm2/analysis/data_analysis.py @@ -4,7 +4,6 @@ from miasm2.ir.symbexec import SymbolicExecutionEngine def get_node_name(label, i, n): - # n_name = "%s_%d_%s"%(label.name, i, n) n_name = (label, i, n) return n_name @@ -69,18 +68,12 @@ def intra_block_flow_symbexec(ir_arch, flow_graph, irb, in_nodes, out_nodes): sb = SymbolicExecutionEngine(ir_arch, dict(symbols_init)) sb.emulbloc(irb) - # print "*"*40 - # print irb - # print sb.dump_id() - # print sb.dump_mem() for n_w in sb.symbols: - # print n_w v = sb.symbols[n_w] if n_w in symbols_init and symbols_init[n_w] == v: continue read_values = v.get_r(cst_read=True) - # print n_w, v, [str(x) for x in read_values] node_n_w = get_node_name(irb.loc_key, len(irb), n_w) for n_r in read_values: @@ -97,9 +90,6 @@ def intra_block_flow_symbexec(ir_arch, flow_graph, irb, in_nodes, out_nodes): def inter_block_flow_link(ir_arch, flow_graph, irb_in_nodes, irb_out_nodes, todo, link_exec_to_data): lbl, current_nodes, exec_nodes = todo - # print 'TODO' - # print lbl - # print [(str(x[0]), str(x[1])) for x in current_nodes] current_nodes = dict(current_nodes) # link current nodes to bloc in_nodes @@ -107,12 +97,10 @@ def inter_block_flow_link(ir_arch, flow_graph, irb_in_nodes, irb_out_nodes, todo print "cannot find bloc!!", lbl return set() irb = ir_arch.blocks[lbl] - # pp(('IN', lbl, [(str(x[0]), str(x[1])) for x in current_nodes.items()])) to_del = set() for n_r, node_n_r in irb_in_nodes[irb.loc_key].items(): if not n_r in current_nodes: continue - # print 'add link', current_nodes[n_r], node_n_r flow_graph.add_uniq_edge(current_nodes[n_r], node_n_r) to_del.add(n_r) @@ -137,8 +125,6 @@ def inter_block_flow_link(ir_arch, flow_graph, irb_in_nodes, irb_out_nodes, todo for lbl_dst in ir_arch.graph.successors(irb.loc_key): todo.add((lbl_dst, tuple(current_nodes.items()), x_nodes)) - # pp(('OUT', lbl, [(str(x[0]), str(x[1])) for x in current_nodes.items()])) - return todo @@ -161,18 +147,11 @@ def create_implicit_flow(ir_arch, flow_graph, irb_in_nodes, irb_out_ndes): if not isinstance(n_r, ExprId): continue - # print "###", n_r - # print "###", irb - # print "###", 'OUT', [str(x) for x in irb.out_nodes] - # print "###", irb_son - # print "###", 'IN', [str(x) for x in irb_son.in_nodes] - node_n_w = irb.loc_key, len(irb), n_r irb_out_nodes[irb.loc_key][n_r] = node_n_w if not n_r in irb_in_nodes[irb.loc_key]: irb_in_nodes[irb.loc_key][n_r] = irb.loc_key, 0, n_r node_n_r = irb_in_nodes[irb.loc_key][n_r] - # print "###", node_n_r for lbl_p in ir_arch.graph.predecessors(irb.loc_key): todo.add(lbl_p) @@ -220,46 +199,11 @@ class symb_exec_func: b = self.ir_arch.get_block(ad) if b is None: raise ValueError("unknown bloc! %s" % ad) - """ - dead = b.dead[0] - for d in dead: - if d in variables: - del(variables[d]) - """ variables = variables.items() s = parent, ad, tuple(sorted(variables)) - """ - state_var = s[1] - if s in self.states_var_done: - print 'skip state' - return - if not ad in self.stateby_ad: - self.stateby_ad[ad] = set() - self.stateby_ad[ad].add(state_var) - - """ self.todo.add(s) - """ - if not ad in self.cpt: - self.cpt[ad] = 0 - """ - """ - def get_next_min(self): - state_by_ad = {} - for state in self.todo: - ad = state[1] - if not ad in state_by_ad: - state_by_ad[ad] = [] - state_by_ad[ad].append(state) - print "XX", [len(x) for x in state_by_ad.values()] - state_by_ad = state_by_ad.items() - state_by_ad.sort(key=lambda x:len(x[1])) - state_by_ad.reverse() - return state_by_ad.pop()[1][0] - """ - def get_next_state(self): state = self.todo.pop() return state @@ -273,16 +217,10 @@ class symb_exec_func: self.total_done += 1 print 'CPT', self.total_done while self.todo: - # if self.total_done>20: - # self.get_next_min() - # state = self.todo.pop() state = self.get_next_state() parent, ad, s = state self.states_done.add(state) self.states_var_done.add(state) - # if s in self.states_var_done: - # print "state done" - # continue sb = SymbolicExecutionEngine(self.ir_arch, dict(s)) diff --git a/miasm2/analysis/debugging.py b/miasm2/analysis/debugging.py index fc03eb17..6b88f00a 100644 --- a/miasm2/analysis/debugging.py +++ b/miasm2/analysis/debugging.py @@ -273,7 +273,7 @@ class DebugCmd(cmd.Cmd, object): def add_breakpoints(self, bp_addr): for addr in bp_addr: - addr = int(addr, 0) + addr = int(addr, 0) good = True for i, dbg_obj in enumerate(self.dbg.bp_list): diff --git a/miasm2/analysis/disasm_cb.py b/miasm2/analysis/disasm_cb.py index e759e313..0dc482ac 100644 --- a/miasm2/analysis/disasm_cb.py +++ b/miasm2/analysis/disasm_cb.py @@ -5,7 +5,6 @@ from miasm2.expression.simplifications import expr_simp from miasm2.core.asmblock \ import AsmSymbolPool, AsmConstraintNext, AsmConstraintTo from miasm2.core.utils import upck32 -# from miasm2.core.graph import DiGraph def get_ira(mnemo, attrib): @@ -32,11 +31,8 @@ def arm_guess_subcall( ir_arch.add_block(cur_bloc) ir_blocks = ir_arch.blocks.values() - # flow_graph = DiGraph() to_add = set() for irblock in ir_blocks: - # print 'X'*40 - # print irblock pc_val = None lr_val = None for exprs in irblock: @@ -53,17 +49,13 @@ def arm_guess_subcall( l = cur_bloc.lines[-1] if lr_val.arg != l.offset + l.l: continue - # print 'IS CALL!' l = symbol_pool.getby_offset_create(int(lr_val)) c = AsmConstraintNext(l) to_add.add(c) offsets_to_dis.add(int(lr_val)) - # if to_add: - # print 'R'*70 for c in to_add: - # print c cur_bloc.addto(c) @@ -80,16 +72,11 @@ def arm_guess_jump_table( ir_blocks = ir_arch.blocks.values() for irblock in ir_blocks: - # print 'X'*40 - # print irblock pc_val = None - # lr_val = None for exprs in irblock: for e in exprs: if e.dst == ir_arch.pc: pc_val = e.src - # if e.dst == mnemo.regs.LR: - # lr_val = e.src if pc_val is None: continue if not isinstance(pc_val, ExprMem): diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index 17b57ba4..624642cf 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -1038,16 +1038,12 @@ class arm_op2(arm_arg): shift_kind = shift & 1 shift_type = (shift >> 1) & 3 shift >>= 3 - # print self.parent.immop.value, hex(shift), hex(shift_kind), - # hex(shift_type) if shift_kind: # shift kind is reg if shift & 1: - # log.debug('error in shift1') return False rs = shift >> 1 if rs == 0xf: - # log.debug('error in shift2') return False shift_op = regs_expr[rs] else: @@ -2155,12 +2151,10 @@ class armt_rlist_pclr(armt_rlist): reg_l = list(e.args) self.parent.pclr.value = 0 if self.parent.pp.value == 0: - # print 'push' if regs_expr[14] in reg_l: reg_l.remove(regs_expr[14]) self.parent.pclr.value = 1 else: - # print 'pop', if regs_expr[15] in reg_l: reg_l.remove(regs_expr[15]) self.parent.pclr.value = 1 diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index c80e9826..ccd56e8f 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -635,7 +635,6 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False) base, off = b.args[0], b.args[1] # ExprInt(size/8, 32) else: base, off = b, ExprInt(0, 32) - # print a, wb, base, off, postinc if postinc: ad = base else: @@ -734,13 +733,11 @@ def ldrsh(ir, instr, a, b): def st_ld_m(ir, instr, a, b, store=False, postinc=False, updown=False): e = [] wb = False - # sb = False dst = None if isinstance(a, ExprOp) and a.op == 'wback': wb = True a = a.args[0] if isinstance(b, ExprOp) and b.op == 'sbit': - # sb = True b = b.args[0] regs = b.args base = a diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index 877c2a70..a3521fb5 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -434,7 +434,6 @@ class ir_msp430(IntermediateRepresentation): pass def get_ir(self, instr): - # print instr#, args args = instr.args instr_ir, extra_ir = mnemo_func[instr.name](self, instr, *args) self.mod_sr(instr, instr_ir, extra_ir) diff --git a/miasm2/jitter/loader/elf.py b/miasm2/jitter/loader/elf.py index deaebd09..01dea647 100644 --- a/miasm2/jitter/loader/elf.py +++ b/miasm2/jitter/loader/elf.py @@ -32,7 +32,6 @@ def preload_elf(vm, e, runtime_lib, patch_vm_imp=True): # XXX quick hack fa = get_import_address_elf(e) dyn_funcs = {} - # log.debug('imported funcs: %s' % fa) for (libname, libfunc), ads in fa.items(): for ad in ads: ad_base_lib = runtime_lib.lib_get_add_base(libname) @@ -77,7 +76,6 @@ def vm_load_elf(vm, fdata, name="", **kargs): # -2: Trick to avoid merging 2 consecutive pages i += [(a_addr, b_addr - 2)] for a, b in i.intervals: - # print hex(a), hex(b) vm.add_memory_page(a, PAGE_READ | PAGE_WRITE, "\x00" * (b + 2 - a), repr(name)) diff --git a/test/analysis/data_flow.py b/test/analysis/data_flow.py index c3469109..d5b197d2 100644 --- a/test/analysis/data_flow.py +++ b/test/analysis/data_flow.py @@ -673,7 +673,6 @@ for test_nb, test in enumerate([(G1_IRA, G1_EXP_IRA), reaching_defs = ReachingDefinitions(g_ira) defuse = DiGraphDefUse(reaching_defs, deref_mem=True) - #open("defuse_%02d.dot" % (test_nb+1), "w").write(defuse.dot()) # # Simplify graph dead_simp(g_ira) diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py index 4e023761..86857182 100644 --- a/test/analysis/depgraph.py +++ b/test/analysis/depgraph.py @@ -1058,7 +1058,7 @@ for test_nb, test in enumerate([(G1_IRA, G1_INPUT), all_results.add(unflatGraph(flatGraph(result.graph))) open("graph_test_%02d_%02d.dot" % (test_nb + 1, i), "w").write(dg2graph(result.graph)) - # print all_flat + if g_ind == 0: all_flat = sorted(all_flat) all_flats.append(all_flat) diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 90d137d0..f69bb104 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -5,41 +5,6 @@ from pdb import pm symbol_pool = AsmSymbolPool() -if 0: - a = bs('00') - b = bs('01') - c = bs(l=2) - d = bs(l=4, fname='rd') - e = bs_name(l=1, name={'ADD': 0, 'SUB': 1}) - assert(isinstance(e, bs_divert)) - scc = bs_mod_name(l=1, mn_mod=['', 'S']) - f = bs(l=1, cls=(arm_reg,)) - - class arm_mov(mn_arm): - fields = [bs('0000'), bs('0000'), bs('0000')] - - class arm_DATA(mn_arm): - fields = [bs('1111'), e, scc, f, bs('0')] - mn = mn_arm.dis(0xF000000) - - -if 0: - import cProfile - cProfile.run('mn_arm.dis("\xe1\xa0\xa0\x06", "l")') - # l = mn_arm.dis(bin_stream("\xe1\xa0\xa0\x06"), mode_arm) - # print l - """ - mode = 64 - l = mn_x86.fromstring("ADC DWORD PTR [RAX], 0x11223344", mode) - print 'xx' - #t= time.time() - import cProfile - def f(): - x = l.asm(mode) - print x - cProfile.run('f()') - """ - def h2i(s): return s.replace(' ', '').decode('hex') @@ -268,15 +233,11 @@ for s, l in reg_tests_arm: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] l = mn_arm.fromstring(s, symbol_pool, 'l') - # print l assert(str(l) == s) a = mn_arm.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) reg_tests_armt = [ @@ -720,36 +681,14 @@ for s, l in reg_tests_armt: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] l = mn_armt.fromstring(s, symbol_pool, 'l') - # print l assert(str(l) == s) print 'Asm..', l a = mn_armt.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) -""" -print "*"*30, "START SPECIAL PARSING", "*"*30 -parse_tests = [ - "MOV LR, toto", - "MOV LR, 1+toto", - "MOV LR, (lend-lstart)^toto<<