From 6e09df71a333bf87cd68c2d08ad068a3e501462d Mon Sep 17 00:00:00 2001 From: Fabrice Desclaux Date: Fri, 5 Sep 2014 11:30:05 +0200 Subject: Modify irbloc destination mecanism. Rework API in consequence. Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon. --- miasm2/analysis/debugging.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'miasm2/analysis/debugging.py') diff --git a/miasm2/analysis/debugging.py b/miasm2/analysis/debugging.py index 28e5ab3c..82710b6a 100644 --- a/miasm2/analysis/debugging.py +++ b/miasm2/analysis/debugging.py @@ -190,7 +190,7 @@ class Debugguer(object): def set_reg_value(self, reg_name, value): # Handle PC case - if reg_name == self.myjit.my_ir.pc.name: + if reg_name == self.myjit.ir_arch.pc.name: self.init_run(value) setattr(self.myjit.cpu, reg_name, value) -- cgit 1.4.1