From 6e09df71a333bf87cd68c2d08ad068a3e501462d Mon Sep 17 00:00:00 2001 From: Fabrice Desclaux Date: Fri, 5 Sep 2014 11:30:05 +0200 Subject: Modify irbloc destination mecanism. Rework API in consequence. Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon. --- miasm2/arch/mips32/jit.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'miasm2/arch/mips32/jit.py') diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 70e05380..132e5da5 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -16,8 +16,8 @@ class jitter_mips32(jitter): def __init__(self, *args, **kwargs): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_mips32(sp), *args, **kwargs) - self.my_ir.jit_pc = self.my_ir.arch.regs.PC - self.my_ir.attrib = 'l' + self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC + self.ir_arch.attrib = 'l' def vm_push_uint32_t(self, v): self.cpu.SP -= 4 -- cgit 1.4.1