From b8d6b97b0f47a8e97f7c52ef0bd7b44a2e1fdc2b Mon Sep 17 00:00:00 2001
From: Fabrice Desclaux <fabrice.desclaux@cea.fr>
Date: Sun, 5 Aug 2018 18:50:42 +0200
Subject: LLVM: zero/sign ext support

---
 miasm2/jitter/llvmconvert.py | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'miasm2')

diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py
index 4a0eae93..de5f19df 100644
--- a/miasm2/jitter/llvmconvert.py
+++ b/miasm2/jitter/llvmconvert.py
@@ -830,6 +830,28 @@ class LLVMFunction():
                 self.update_cache(expr, ret)
                 return ret
 
+
+            if op.startswith('zeroExt_'):
+                arg = expr.args[0]
+                if expr.size == arg.size:
+                    return arg
+                new_expr = ExprCompose(arg, ExprInt(0, expr.size - arg.size))
+                return self.add_ir(new_expr)
+
+            if op.startswith("signExt_"):
+                arg = expr.args[0]
+                add_size = expr.size - arg.size
+                new_expr = ExprCompose(
+                    arg,
+                    ExprCond(
+                        arg.msb(),
+                        ExprInt(size2mask(add_size), add_size),
+                        ExprInt(0, add_size)
+                    )
+                )
+                return self.add_ir(new_expr)
+
+
             if op == "segm":
                 fc_ptr = self.mod.get_global("segm2addr")
 
-- 
cgit 1.4.1