From 99363b7eabb12cbbad02a589efe2b5fc360e45f5 Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sat, 17 Oct 2015 20:57:52 +0200 Subject: Test/Arch/x86: dt mnemonics --- test/arch/x86/arch.py | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 2109aa53..734c8086 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2056,6 +2056,14 @@ reg_tests = [ (m32, "00000000 SIDT DWORD PTR [EAX]", "0f0108"), + (m32, "00000000 SLDT DWORD PTR [EAX]", + "0f0000"), + + + (m32, "00000000 LGDT DWORD PTR [EAX]", + "0f0110"), + (m32, "00000000 LIDT DWORD PTR [EAX]", + "0f0118"), -- cgit 1.4.1 From 1d3a33cf6b1b9d744e4df4bafaf72bae2857b045 Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sat, 17 Oct 2015 21:15:13 +0200 Subject: Test/Arch/x86: comiss comisd --- test/arch/x86/arch.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 734c8086..8ea0f65f 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2459,6 +2459,18 @@ reg_tests = [ (m32, "00000006 CVTSS2SD XMM4, DWORD PTR [EAX+EDX*0x8]", "F30F5A24D0"), + + (m32, "00000000 COMISS XMM0, XMM0", + "0f2fc0"), + (m64, "00000000 COMISS XMM0, XMM8", + "410f2fc0"), + (m64, "00000000 COMISS XMM0, DWORD PTR [RAX]", + "0f2f00"), + (m64, "00000000 COMISS XMM0, DWORD PTR [RSP+0x34]", + "0F2F442434"), + (m32, "00000000 COMISD XMM7, XMM6", + "660F2FFE"), + ] -- cgit 1.4.1 From 33ef80c0cb66aa412696497dc1d35ed4bbd0dff0 Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sat, 17 Oct 2015 21:26:54 +0200 Subject: Test/Arch/x86: call far --- test/arch/x86/arch.py | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 8ea0f65f..022d387e 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -765,6 +765,11 @@ reg_tests = [ (m32, "00000000 CALL 0x6655:0xFF332211", "9a112233FF5566"), + (m32, "00000000 CALL DWORD PTR [0xFFFFFFA3]", + "FF1DA3FFFFFF"), + (m64, "00000000 CALL QWORD PTR [RIP+0xFFFFFFFFFFFFFFA3]", + "FF1DA3FFFFFF"), + (m16, "00000000 CBW", "98"), @@ -2471,6 +2476,8 @@ reg_tests = [ (m32, "00000000 COMISD XMM7, XMM6", "660F2FFE"), + + ] -- cgit 1.4.1 From 619a75e44fdf0a9e9e0a485615f41941fd60d78e Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sat, 17 Oct 2015 22:05:55 +0200 Subject: Test/Arch/x86: movq --- test/arch/x86/arch.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 022d387e..b6d277ad 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2326,6 +2326,8 @@ reg_tests = [ (m64, "00000000 MOVQ XMM1, QWORD PTR [R12+0xFFFFFFFFFFFFFFE0]", "f3410f7e4c24e0"), + (m64, "00000000 MOVQ RCX, XMM0", + "66480F7EC1"), (m32, "00000000 PAND MM2, MM6", "0fdbd6"), -- cgit 1.4.1 From 4a493a61dc36890b12efc5a9b0dc8d47cfbe4c22 Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sat, 17 Oct 2015 23:03:49 +0200 Subject: Test/Arch/x86:: fix wbinvd --- test/arch/x86/arch.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index b6d277ad..4f6fef22 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2132,7 +2132,7 @@ reg_tests = [ (m32, "00000000 VERW DWORD PTR [EAX]", "0f0028"), - (m32, "00000000 WBIND", + (m32, "00000000 WBINVD", "0f09"), (m32, "00000000 WRMSR", -- cgit 1.4.1 From c92d6b342bf2ff7ab569ba3851a9a23c8862befc Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sun, 18 Oct 2015 01:40:26 +0200 Subject: Test/Arch/x86:: add cvt --- test/arch/x86/arch.py | 48 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 4f6fef22..5216b3ae 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2248,10 +2248,56 @@ reg_tests = [ (m32, "00000000 MAXSS XMM0, DWORD PTR [EBX+0x2CBD37]", "f30f5f8337bd2c00"), + (m32, "00000000 CVTDQ2PD XMM0, XMM3", + "f30fe6c3"), + (m32, "00000000 CVTDQ2PS XMM0, XMM3", + "0f5bc3"), + (m32, "00000000 CVTPD2DQ XMM0, XMM3", + "f20fe6c3"), + (m32, "00000000 CVTPD2PI MM0, XMM3", + "660f2dc3"), + (m32, "00000000 CVTPD2PS XMM0, XMM3", + "660f5ac3"), + (m32, "00000000 CVTPI2PD XMM0, MM3", + "660f2ac3"), + (m32, "00000000 CVTPI2PS XMM0, MM3", + "0f2ac3"), + (m32, "00000000 CVTPS2DQ XMM0, XMM3", + "660f5bc3"), + (m32, "00000000 CVTPS2PD XMM0, XMM3", + "0f5ac3"), + (m32, "00000000 CVTPS2PI MM0, XMM3", + "0f2dc3"), + (m32, "00000000 CVTSD2SI EAX, XMM3", + "f20f2dc3"), + (m32, "00000000 CVTSD2SS XMM0, XMM3", + "f20f5ac3"), (m32, "00000000 CVTSI2SD XMM0, EBX", "f20f2ac3"), (m32, "00000000 CVTSI2SS XMM0, EBX", "f30f2ac3"), + (m32, "00000000 CVTSS2SD XMM0, XMM0", + "f30f5ac0"), + (m32, "00000000 CVTSS2SI EAX, XMM3", + "f30f2dc3"), + (m32, "00000000 CVTTPD2PI MM0, XMM3", + "660f2cc3"), + (m32, "00000000 CVTTPD2DQ XMM0, XMM3", + "660fe6c3"), + (m32, "00000000 CVTTPS2DQ XMM0, XMM3", + "f30f5bc3"), + (m32, "00000000 CVTTPS2PI MM0, XMM3", + "0f2cc3"), + (m32, "00000000 CVTTSD2SI EAX, XMM3", + "f20f2cc3"), + (m32, "00000000 CVTTSS2SI EAX, XMM3", + "f30f2cc3"), + + + + + (m32, "00000000 CVTSI2SD XMM0, EBX", + "f20f2ac3"), (m32, "00000000 PMINSW MM0, MM1", "0feac1"), @@ -2456,8 +2502,6 @@ reg_tests = [ ## # SSE - (m32, "00000000 CVTSS2SD XMM0, XMM0", - "f30f5ac0"), (m32, "00000000 CVTSS2SD XMM0, DWORD PTR [EBP+0xFFFFFFD0]", "f30f5a45d0"), -- cgit 1.4.1 From f7ce75fca55241784a7e81f6c0243781f953695f Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sun, 18 Oct 2015 18:04:57 +0200 Subject: Test/x86/arch: add fcmovcc --- test/arch/x86/arch.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 5216b3ae..46bb264b 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -898,6 +898,20 @@ reg_tests = [ (m32, "00000000 FCMOVB ST, ST(2)", "dac2"), + (m32, "00000000 FCMOVE ST, ST(2)", + "daca"), + (m32, "00000000 FCMOVBE ST, ST(2)", + "dad2"), + (m32, "00000000 FCMOVU ST, ST(2)", + "dada"), + (m32, "00000000 FCMOVNB ST, ST(2)", + "dbc2"), + (m32, "00000000 FCMOVNE ST, ST(2)", + "dbca"), + (m32, "00000000 FCMOVNBE ST, ST(2)", + "dbd2"), + (m32, "00000000 FCMOVNU ST, ST(2)", + "dbda"), (m32, "00000000 FCOM DWORD PTR [EAX]", "d810"), -- cgit 1.4.1 From 6342f13ad2c341f01b1861f1ca8bb1209d5cf59c Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sun, 18 Oct 2015 18:44:02 +0200 Subject: Test/Arch/x86:: add fcom/fcomp --- test/arch/x86/arch.py | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 46bb264b..50921b07 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -921,9 +921,13 @@ reg_tests = [ "d818"), (m32, "00000000 FCOMP QWORD PTR [EAX]", "dC18"), + (m32, "00000000 FCOM ST, ST(1)", + "d8d1"), (m32, "00000000 FCOM ST, ST(2)", "d8d2"), + (m32, "00000000 FCOMP ST, ST(1)", + "d8d9"), (m32, "00000000 FCOMPP", "ded9"), -- cgit 1.4.1 From 477a0dd1bd1ac0eadc9a8f4dd4d0ba1ccf52e7b6 Mon Sep 17 00:00:00 2001 From: serpilliere Date: Sun, 18 Oct 2015 22:50:07 +0200 Subject: Test/Arch/x86:: add cpuid --- test/arch/x86/arch.py | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 50921b07..6970bc6c 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -61,6 +61,12 @@ m16 = 16 # (16, 16) m32 = 32 # (32, 32) m64 = 64 # (64, 64) reg_tests = [ + (m16, "XXXXXXXX CPUID", + "0fa2"), + (m32, "XXXXXXXX CPUID", + "0fa2"), + (m64, "XXXXXXXX CPUID", + "0fa2"), (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EAX]", -- cgit 1.4.1 From 11fbc33187c678edf12f8357521045a7fa5a3c6a Mon Sep 17 00:00:00 2001 From: serpilliere Date: Mon, 19 Oct 2015 21:29:26 +0200 Subject: Test/Arch/x86:: add por/pxor --- test/arch/x86/arch.py | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 6970bc6c..ca824130 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2212,6 +2212,13 @@ reg_tests = [ (m32, "00000000 XORPD XMM1, XMM2", "660f57ca"), + (m32, "00000000 ORPS XMM1, XMM2", + "0f56ca"), + (m32, "00000000 ORPS XMM1, XMMWORD PTR [EDI+0x42]", + "0f564f42"), + (m32, "00000000 ORPD XMM1, XMM2", + "660f56ca"), + (m32, "00000000 MOVAPS XMMWORD PTR [EBP+0xFFFFFFB8], XMM0", "0f2945b8"), (m32, "00000000 MOVAPS XMM0, XMMWORD PTR [EBP+0xFFFFFFB8]", @@ -2255,8 +2262,13 @@ reg_tests = [ "f20f5911"), - (m32, "00000000 PXOR XMM0, XMM0", - "0fefc0"), + (m32, "00000000 PXOR MM0, MM1", + "0fefc1"), + (m32, "00000000 PXOR XMM0, XMM1", + "660fefc1"), + (m32, "00000000 PXOR XMM6, XMMWORD PTR [ECX+0x10]", + "660fef7110"), + (m32, "00000000 UCOMISD XMM0, QWORD PTR [EBP+0xFFFFFFD8]", "660f2e45d8"), (m32, "00000000 ANDPS XMM0, XMMWORD PTR [EBX+0x2CBD27]", @@ -2412,6 +2424,10 @@ reg_tests = [ (m32, "00000000 POR XMM0, XMM1", "660febc1"), + (m32, "00000000 POR XMM6, XMMWORD PTR [ECX+0x10]", + "660febb110000000"), + (m32, "00000000 POR MM6, QWORD PTR [ECX+0x10]", + "0febb110000000"), (m32, "00000000 MOVDQU XMM1, XMMWORD PTR [ESI]", "f30f6f0e"), -- cgit 1.4.1 From 9381162cad9aecaaa507bddffb5108d4f84c9f6e Mon Sep 17 00:00:00 2001 From: serpilliere Date: Thu, 22 Oct 2015 20:51:50 +0200 Subject: Test/arch/x86: remove wildcard imports --- test/arch/x86/arch.py | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'test') diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index ca824130..5721d72a 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -1,6 +1,10 @@ import os import time -from miasm2.arch.x86.arch import * +import miasm2.expression.expression as m2_expr +from miasm2.arch.x86.arch import mn_x86, deref_mem_ad, parse_ast, ast_int2expr, \ + base_expr, rmarg, print_size +from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 +from miasm2.core.bin_stream import bin_stream_str filename = os.environ.get('PYTHONSTARTUP') if filename and os.path.isfile(filename): @@ -15,9 +19,9 @@ for s in ["[EAX]", print '---' -mylabel16 = ExprId('mylabel16', 16) -mylabel32 = ExprId('mylabel32', 32) -mylabel64 = ExprId('mylabel64', 64) +mylabel16 = m2_expr.ExprId('mylabel16', 16) +mylabel32 = m2_expr.ExprId('mylabel32', 32) +mylabel64 = m2_expr.ExprId('mylabel64', 64) reg_and_id = dict(mn_x86.regs.all_regs_ids_byname) reg_and_id.update({'mylabel16': mylabel16, @@ -27,7 +31,7 @@ reg_and_id.update({'mylabel16': mylabel16, def my_ast_id2expr(t): - r = reg_and_id.get(t, ExprId(t, size=32)) + r = reg_and_id.get(t, m2_expr.ExprId(t, size=32)) return r my_var_parser = parse_ast(my_ast_id2expr, ast_int2expr) -- cgit 1.4.1