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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
| commit | 3e4c5a6261770bced301b5e74233e7866166ea5b (patch) | |
| tree | 9379fddaba693ef8a045da06efee8529baa5f6f4 /gitlab/issues_text/target_i386/host_missing/accel_missing/1164 | |
| parent | e5634e2806195bee44407853c4bf8776f7abfa4f (diff) | |
| download | qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.tar.gz qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.zip | |
clean up repository
Diffstat (limited to 'gitlab/issues_text/target_i386/host_missing/accel_missing/1164')
| -rw-r--r-- | gitlab/issues_text/target_i386/host_missing/accel_missing/1164 | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 b/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 deleted file mode 100644 index d79ec6483..000000000 --- a/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 +++ /dev/null @@ -1,17 +0,0 @@ -q35: incorrect values for PCIEXBAR masks -Description of problem: -https://lore.kernel.org/all/1fded151ce5ecbf7010427871b908000b2aba9ee.1520867956.git.x1917x@gmail.com/ - -In function [mch_update_pciexbar](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/pci-host/q35.c#L295) - -There are two small issues in PCIEXBAR address mask handling: -- wrong bit positions for address mask bits (see PCIEXBAR description - in Q35 datasheet) -- incorrect usage of 64ADR_MASK - -Due to this, attempting to write a valid PCIEXBAR address may cause it to -shift to another address, causing memory layout corruption where emulated -MMIO regions may overlap real (passed through) MMIO ranges. Fix this -by providing correct values. -Additional information: -Q35 datasheet: https://www.intel.com/Assets/PDF/datasheet/316966.pdf ( 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ) |