gitlab scraper: download in toml and text format

1 files changed, 27 insertions, 0 deletions

diff --git a/gitlab/issues_text/target_missing/host_missing/accel_missing/1458 b/gitlab/issues_text/target_missing/host_missing/accel_missing/1458
new file mode 100644
index 000000000..7a8b493c9
--- /dev/null
+++ b/gitlab/issues_text/target_missing/host_missing/accel_missing/1458
@@ -0,0 +1,27 @@
+ns16550a reg-shift incorrect for qemu-system-riscv64
+Description of problem:
+Missing reg-shift 0 on the ns16550n in qemu-system-riscv64 creates an impossible assumption case.
+Steps to reproduce:
+1. qemu-system-riscv64 -M virt,dumpdtb=dtb
+2. dtc dtb | less
+
+                serial@10000000 {
+                        interrupts = <0x0a>;
+                        interrupt-parent = <0x03>;
+                        clock-frequency = "\08@";
+                        reg = <0x00 0x10000000 0x00 0x100>;
+                        compatible = "ns16550a";
+                };
+
+Generally, ns16550a has a default reg-shift of 0 on x86,x86_64 for compatibility reasons.  All other architectures have an assumed reg-shift of 2 (or having the reg-shift assumption overridden by fdt providing a reg-shift property)
+
+Beyond the above, anything non-standard is assumed to be specified by the "reg-shift" property fdt.
+
+qemu-system-riscv64 seems to "assume" a reg-shift of 0.  Other riscv64 devices don't supply "reg-shift" (SiFive Unmatched) and "assume" 2.
+The above means driver writers don't actually know what to "assume" on riscv64 ns16550a when no reg-shift is present.
+
+
+Essentially, qemu-system-riscv64 needs to do one of the following:
+
+* If serial ns16550a with a uart reg-shift of 0 is intentional, qemu needs to advertise the deviance via "reg-shift 0"
+* If serial ns16550a with a uart reg-shift of 0 is unintentional, it needs updated to 2 so drivers can assume 2 on riscv64.