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authorChristian Krinitsin <mail@krinitsin.com>2025-06-01 21:35:14 +0200
committerChristian Krinitsin <mail@krinitsin.com>2025-06-01 21:35:14 +0200
commit3e4c5a6261770bced301b5e74233e7866166ea5b (patch)
tree9379fddaba693ef8a045da06efee8529baa5f6f4 /gitlab/issues_text/target_riscv/host_missing/accel_missing/1093
parente5634e2806195bee44407853c4bf8776f7abfa4f (diff)
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clean up repository
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-RISC-V: signal frame is misaligned in signal handlers
-Description of problem:
-`qemu-user` misaligns the signal frame (to 4 bytes rather than 16 bytes) on RISC-V 64, e.g causing pointer misalignment diagnostics to be triggered by UBSan.
-Steps to reproduce:
-1. Create a C file with the following contents:
-```c
-#include <signal.h>
-#include <stdio.h>
-
-void handler(int sig, siginfo_t *info, void *context) {
-	printf("signal occurred, info: %p, context: %p\n", info, context);
-}
-
-int main() {
-	struct sigaction act;
-	act.sa_flags = SA_SIGINFO;
-	act.sa_sigaction = handler;
-	sigaction(SIGINT, &act, NULL);
-
-	// Deliberately misalign the stack
-	asm volatile ("addi sp, sp, -4");
-
-	while(1);
-	// Unreachable
-}
-```
-2. Compile with an appropriate RISC-V toolchain and run with `qemu-riscv64 ./a.out`.
-3. Send a `SIGINT` (e.g by hitting Ctrl-C), and observe that the signal frame will be misaligned:
-```
-signal occurred, info: 0x400080025c, context: 0x40008002dc
-```
-Additional information:
-This issue is alluded to in the source code, see https://gitlab.com/qemu-project/qemu/-/blob/master/linux-user/riscv/signal.c#L68-69. It should be sufficient to change that constant to 15.