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authorChristian Krinitsin <mail@krinitsin.com>2025-05-30 16:52:07 +0200
committerChristian Krinitsin <mail@krinitsin.com>2025-05-30 16:52:17 +0200
commit9260319e7411ff8281700a532caa436f40120ec4 (patch)
tree2f6bfe5f3458dd49d328d3a9eb508595450adec0 /gitlab/issues_text/target_riscv/host_missing/accel_missing/1606
parent225caa38269323af1bfc2daadff5ec8bd930747f (diff)
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+riscv: fence.i is not functional
+Description of problem:
+The attached user-level test is designed to do the following (in iteration):
+
+  - Thread P0 on CPU0 changes some text/code, while
+
+  - Thread P1 on CPU1 checks/reads the code, fence.i, then executes the same code.
+
+Results (in stdout) indicates that CPU1 has read the new code (1:x5=a009) but executed the old one (1:x7=1) (against the specification).
+Steps to reproduce:
+1. echo 2 > /proc/sys/vm/nr_hugepages
+2. ./CoRF+fence.i
+Additional information:
+Example output:
+```[CoRF+fence.i.c](/uploads/c150ca0910783cc4bfc3886789b64c28/CoRF+fence.i.c)
+Test CoRF+fence.i Allowed
+Histogram (4 states)
+25784  :>1:x5=0xa009; 1:x7=2;
+24207  *>1:x5=0xa009; 1:x7=1;   <--  THIS LINE
+8      :>1:x5=0xa019; 1:x7=1;
+1      :>1:x5=0xa019; 1:x7=2;
+Ok
+Witnesses
+Positive: 24207 Negative 25793
+Condition exists (1:x5=0xa009 /\ 1:x7=1) is  validated
+Observation CoRF+fence.i Sometimes 24207 25793
+Time CoRF+fence.i 0.85
+Hash=
+```