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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
| commit | 3e4c5a6261770bced301b5e74233e7866166ea5b (patch) | |
| tree | 9379fddaba693ef8a045da06efee8529baa5f6f4 /gitlab/issues_text/target_riscv/host_missing/accel_missing/904 | |
| parent | e5634e2806195bee44407853c4bf8776f7abfa4f (diff) | |
| download | qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.tar.gz qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.zip | |
clean up repository
Diffstat (limited to 'gitlab/issues_text/target_riscv/host_missing/accel_missing/904')
| -rw-r--r-- | gitlab/issues_text/target_riscv/host_missing/accel_missing/904 | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_missing/904 b/gitlab/issues_text/target_riscv/host_missing/accel_missing/904 deleted file mode 100644 index 440aaf90f..000000000 --- a/gitlab/issues_text/target_riscv/host_missing/accel_missing/904 +++ /dev/null @@ -1,16 +0,0 @@ -RISC-V: Cannot set SEIP bit of mip csr register in M mode -Description of problem: - -Steps to reproduce: -1. run assembly instructions **in M mode**: -``` -not t0, x0 // set t0 to 0b11..11 -csrs mip, t0 // write mip with t0, mip registers are WARL(Write Any Values, Reads Legal Values) -csrr t1, mip // read value from mip to t1 -``` -2. GDB enters the command `display/z $t1` to see that the content of the t1 register is 0x466, which means that the SEIP bit of mip is not set. -3. According to page 47 of [riscv-privileged-20211203](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf), `SEIP is writable in mip`. -4. According to page 81 of the same manual,`If implemented, SEIP is read-only in sip`. -5. However, the above code and results show that the SEIP bit of mip cannot be set by software **in M mode**. -Additional information: - |