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authorChristian Krinitsin <mail@krinitsin.com>2025-06-01 21:35:14 +0200
committerChristian Krinitsin <mail@krinitsin.com>2025-06-01 21:35:14 +0200
commit3e4c5a6261770bced301b5e74233e7866166ea5b (patch)
tree9379fddaba693ef8a045da06efee8529baa5f6f4 /gitlab/issues_text/target_sparc/host_missing/accel_TCG/847
parente5634e2806195bee44407853c4bf8776f7abfa4f (diff)
downloadqemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.tar.gz
qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.zip
clean up repository
Diffstat (limited to 'gitlab/issues_text/target_sparc/host_missing/accel_TCG/847')
-rw-r--r--gitlab/issues_text/target_sparc/host_missing/accel_TCG/84730
1 files changed, 0 insertions, 30 deletions
diff --git a/gitlab/issues_text/target_sparc/host_missing/accel_TCG/847 b/gitlab/issues_text/target_sparc/host_missing/accel_TCG/847
deleted file mode 100644
index 38a2e4c28..000000000
--- a/gitlab/issues_text/target_sparc/host_missing/accel_TCG/847
+++ /dev/null
@@ -1,30 +0,0 @@
-rdhpr %htstate unimplemented in translator
-Description of problem:
-I accidentally mixed up a copy of T1 and T2 sun4v firmwares and was able to trigger the following TCG assert ``tcg_reg_alloc_mov: Assertion `ts->val_type == TEMP_VAL_REG' failed.`` upon boot.
-
-Having discovered my mistake I was expecting the guest to crash at some point but without triggering an
-assert.
-Steps to reproduce:
-1. Download the attached file bug.tar.gz and extract it
-
-2. Apply the following diff to update the UART address for the T2 firmware
-
-```
-diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c
-index ccad2c43a3..7af64bd50f 100644
---- a/hw/sparc64/niagara.c
-+++ b/hw/sparc64/niagara.c
-@@ -51,7 +51,7 @@ typedef struct NiagaraBoardState {
- 
- #define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL
- 
--#define NIAGARA_UART_BASE   0x1f10000000ULL
-+#define NIAGARA_UART_BASE   0xfff0c2c000ULL
- 
- #define NIAGARA_NVRAM_BASE  0x1f11000000ULL
- #define NIAGARA_NVRAM_SIZE  0x2000
-```
-
-3. Run `./qemu-system-sparc64 -M niagara -L ./bug/ -m 256 -nographic`
-Additional information:
-