add new results

1 files changed, 52 insertions, 0 deletions

diff --git a/results/classifier/011/semantic/gitlab_semantic_addsubps b/results/classifier/011/semantic/gitlab_semantic_addsubps
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@@ -0,0 +1,52 @@
+semantic: 0.513
+other: 0.170
+device: 0.065
+debug: 0.047
+graphic: 0.035
+vnc: 0.027
+performance: 0.024
+permissions: 0.024
+PID: 0.021
+files: 0.020
+boot: 0.017
+socket: 0.015
+network: 0.013
+KVM: 0.009
+semantic: 0.848
+debug: 0.039
+files: 0.020
+other: 0.019
+PID: 0.013
+performance: 0.011
+network: 0.009
+device: 0.007
+permissions: 0.007
+boot: 0.007
+socket: 0.006
+vnc: 0.005
+graphic: 0.005
+KVM: 0.004
+
+x86 SSE/SSE2/SSE3 instruction semantic bugs with NaN
+
+Description of problem
+The result of SSE/SSE2/SSE3 instructions with NaN is different from the CPU. From Intel manual Volume 1 Appendix D.4.2.2, they defined the behavior of such instructions with NaN. But I think QEMU did not implement this semantic exactly because the byte result is different.
+
+Steps to reproduce
+
+Compile this code
+
+void main() {
+    asm("mov rax, 0x000000007fffffff; push rax; mov rax, 0x00000000ffffffff; push rax; movdqu XMM1, [rsp];");
+    asm("mov rax, 0x2e711de7aa46af1a; push rax; mov rax, 0x7fffffff7fffffff; push rax; movdqu XMM2, [rsp];");
+    asm("addsubps xmm1, xmm2");
+}
+
+Execute and compare the result with the CPU. This problem happens with other SSE/SSE2/SSE3 instructions specified in the manual, Volume 1 Appendix D.4.2.2.
+
+CPU xmm1[3] = 0xffffffff
+
+QEMU xmm1[3] = 0x7fffffff
+
+Additional information
+This bug is discovered by research conducted by KAIST SoftSec.