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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 19:39:53 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 19:39:53 +0200 |
| commit | dee4dcba78baf712cab403d47d9db319ab7f95d6 (patch) | |
| tree | 418478faf06786701a56268672f73d6b0b4eb239 /results/classifier/118/assembly-risc-v | |
| parent | 4d9e26c0333abd39bdbd039dcdb30ed429c475ba (diff) | |
| download | qemu-analysis-dee4dcba78baf712cab403d47d9db319ab7f95d6.tar.gz qemu-analysis-dee4dcba78baf712cab403d47d9db319ab7f95d6.zip | |
restructure results
Diffstat (limited to 'results/classifier/118/assembly-risc-v')
| -rw-r--r-- | results/classifier/118/assembly-risc-v/904 | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/results/classifier/118/assembly-risc-v/904 b/results/classifier/118/assembly-risc-v/904 deleted file mode 100644 index 4840d6368..000000000 --- a/results/classifier/118/assembly-risc-v/904 +++ /dev/null @@ -1,76 +0,0 @@ -risc-v: 0.994 -assembly: 0.991 -register: 0.963 -permissions: 0.887 -architecture: 0.881 -graphic: 0.875 -device: 0.846 -peripherals: 0.767 -performance: 0.730 -semantic: 0.662 -debug: 0.641 -network: 0.599 -kernel: 0.551 -mistranslation: 0.507 -vnc: 0.485 -PID: 0.479 -ppc: 0.468 -boot: 0.425 -socket: 0.381 -files: 0.356 -arm: 0.335 -TCG: 0.263 -i386: 0.257 -VMM: 0.234 -KVM: 0.219 -x86: 0.201 -hypervisor: 0.191 -user-level: 0.185 -virtual: 0.165 --------------------- -register: 0.932 -assembly: 0.927 -risc-v: 0.913 -debug: 0.794 -architecture: 0.412 -TCG: 0.093 -files: 0.026 -PID: 0.019 -device: 0.015 -peripherals: 0.014 -semantic: 0.014 -performance: 0.011 -kernel: 0.009 -virtual: 0.007 -hypervisor: 0.005 -VMM: 0.003 -vnc: 0.003 -KVM: 0.002 -user-level: 0.002 -boot: 0.002 -network: 0.002 -graphic: 0.001 -socket: 0.001 -permissions: 0.001 -mistranslation: 0.000 -arm: 0.000 -i386: 0.000 -x86: 0.000 -ppc: 0.000 - -RISC-V: Cannot set SEIP bit of mip csr register in M mode -Description of problem: - -Steps to reproduce: -1. run assembly instructions **in M mode**: -``` -not t0, x0 // set t0 to 0b11..11 -csrs mip, t0 // write mip with t0, mip registers are WARL(Write Any Values, Reads Legal Values) -csrr t1, mip // read value from mip to t1 -``` -2. GDB enters the command `display/z $t1` to see that the content of the t1 register is 0x466, which means that the SEIP bit of mip is not set. -3. According to page 47 of [riscv-privileged-20211203](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf), `SEIP is writable in mip`. -4. According to page 81 of the same manual,`If implemented, SEIP is read-only in sip`. -5. However, the above code and results show that the SEIP bit of mip cannot be set by software **in M mode**. -Additional information: - |