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Diffstat (limited to 'gitlab/issues/target_arm/host_missing/accel_missing/2916.toml')
| -rw-r--r-- | gitlab/issues/target_arm/host_missing/accel_missing/2916.toml | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/gitlab/issues/target_arm/host_missing/accel_missing/2916.toml b/gitlab/issues/target_arm/host_missing/accel_missing/2916.toml new file mode 100644 index 000000000..e678e0c6c --- /dev/null +++ b/gitlab/issues/target_arm/host_missing/accel_missing/2916.toml @@ -0,0 +1,34 @@ +id = 2916 +title = "qemu-system-arm hangs when attempting to enable MMU on Cortex-A7" +state = "opened" +created_at = "2025-04-07T11:27:39.291Z" +closed_at = "n/a" +labels = ["target: arm", "workflow::Needs Info"] +url = "https://gitlab.com/qemu-project/qemu/-/issues/2916" +host-os = "Ubuntu 22.04.5 LTS" +host-arch = "x86_64" +qemu-version = "QEMU emulator version 9.2.3" +guest-os = "bare-metal/?" +guest-arch = "ARM" +description = """QEMU 9.x.x+ hangs when attempting to do enable the MMU from SCTLRL - M bit: https://developer.arm.com/documentation/ddi0601/2025-03/AArch32-Registers/SCTLR--System-Control-Register + +The instruction that hangs is the writing of the SCTLR register: + +``` +mrc p15, 0, r0, c1, c0, 0 +orr r0, r0, 1 +mcr p15, 0, r0, c1, c0, 0 +``` + +I am attempting to enable unaligned accesses and SCTLR-A bit doesn't seem to have any effect if the SCTLR-M is not enabled. Doing an unaligned access on cortex-a7 should be supported but it always trigger a Fault.""" +reproduce = """1. add the mrc/orr/mcr instruction sequence in the ResetHandler +2. link the elf +3. attempt to execute it""" +additional = """The unaligned access looked like it was working in QEMU 8.x.x but it might not have been emulated(?). I also am facing the same issues with MCR hanging and unaligned access not supported with latest 10.0.0-RC2. + +When it hangs, QEMU has to be killed and terminal reset. + +There might be two separate issues here: + +1. writing SCTLR register +2. emulated cortex-a7 not supporting unaligned access (hardware supports it)""" |