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diff --git a/gitlab/issues/target_i386/host_missing/accel_TCG/2578.toml b/gitlab/issues/target_i386/host_missing/accel_TCG/2578.toml
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+id = 2578
+title = "x86: exception during hardware interrupt pushes wrong error code"
+state = "opened"
+created_at = "2024-09-19T09:09:25.955Z"
+closed_at = "n/a"
+labels = ["accel: TCG", "target: i386", "workflow::Patch available"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/2578"
+host-os = "- OS/kernel version:"
+host-arch = "- QEMU flavor:                 qemu-system-x86_64 qemu-system-i386"
+qemu-version = "all"
+guest-os = "- OS/kernel version:"
+guest-arch = "x86"
+description = """Exceptions during IDT traversal push the wrong error code when triggered by a hardware interrupt.
+The EXT bit in TCG mode is never set.  However, it works fine in KVM mode as hardware is generating the number."""
+reproduce = """1. load a short IDT e.g. with 64 entries
+2. trigger a self IPI through the LAPIC with a vector 100
+3. the pushed error code is 802 instead of 803."""
+additional = """It can be fixed in the lines `raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);` in `seg_helper.c` 
+which must include the `is_hw` field when calculating the error number. Something like `intno * 8 + 2 + (is_hw != 0)` 
+works here.
+
+Nevertheless, all the other exception cases in the `do_interrupt_*` functions have to set the same bit as well."""