1 files changed, 0 insertions, 33 deletions

diff --git a/gitlab/issues/target_missing/host_missing/accel_missing/2550.toml b/gitlab/issues/target_missing/host_missing/accel_missing/2550.toml
deleted file mode 100644
index 708d2067a..000000000
--- a/gitlab/issues/target_missing/host_missing/accel_missing/2550.toml
+++ /dev/null
@@ -1,33 +0,0 @@
-id = 2550
-title = "GICv3 vGIC system registers not initialized on ARM Cortex-A15"
-state = "closed"
-created_at = "2024-09-02T12:32:04.192Z"
-closed_at = "2024-09-02T13:51:35.616Z"
-labels = []
-url = "https://gitlab.com/qemu-project/qemu/-/issues/2550"
-host-os = "Debian/unstable"
-host-arch = "x86"
-qemu-version = "9.0.92 (v9.1.0-rc2-57-g2ee4170ae6)"
-guest-os = "L4Re"
-guest-arch = "ARM"
-description = """For Cortex-A15, the GICv3 vGIC registers are not initialized like for AArch64 CPUs, for example Cotex-A35, Cortex-A55, etc"""
-reproduce = """The setup is not trivial. I can provide a boot image on request. But I hope the problem is straight-forward."""
-additional = """Suggested fix:
-```diff
-index 20c2737f17..136b513bda 100644
---- a/target/arm/tcg/cpu32.c
-+++ b/target/arm/tcg/cpu32.c
-@@ -569,6 +569,12 @@ static void cortex_a15_initfn(Object *obj)
-     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
-     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
-     cpu->isar.reset_pmcr_el0 = 0x410F3000;
-+
-+    /* From B3.5 VGIC Type register */
-+    cpu->gic_num_lrs = 4;
-+    cpu->gic_vpribits = 5;
-+    cpu->gic_vprebits = 5;
-+
-     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
- }
-
-```"""