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diff --git a/gitlab/issues/target_riscv/host_missing/accel_missing/1093.toml b/gitlab/issues/target_riscv/host_missing/accel_missing/1093.toml
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+id = 1093
+title = "RISC-V: signal frame is misaligned in signal handlers"
+state = "closed"
+created_at = "2022-06-29T20:45:51.271Z"
+closed_at = "2022-08-02T13:35:56.948Z"
+labels = ["Closed::Fixed", "linux-user", "target: riscv"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1093"
+host-os = "Linux"
+host-arch = "x86_64"
+qemu-version = "7.0.0"
+guest-os = "n/a"
+guest-arch = "RISC-V 64"
+description = """`qemu-user` misaligns the signal frame (to 4 bytes rather than 16 bytes) on RISC-V 64, e.g causing pointer misalignment diagnostics to be triggered by UBSan."""
+reproduce = """1. Create a C file with the following contents:
+```c
+#include <signal.h>
+#include <stdio.h>
+
+void handler(int sig, siginfo_t *info, void *context) {
+\tprintf("signal occurred, info: %p, context: %p\\n", info, context);
+}
+
+int main() {
+\tstruct sigaction act;
+\tact.sa_flags = SA_SIGINFO;
+\tact.sa_sigaction = handler;
+\tsigaction(SIGINT, &act, NULL);
+
+\t// Deliberately misalign the stack
+\tasm volatile ("addi sp, sp, -4");
+
+\twhile(1);
+\t// Unreachable
+}
+```
+2. Compile with an appropriate RISC-V toolchain and run with `qemu-riscv64 ./a.out`.
+3. Send a `SIGINT` (e.g by hitting Ctrl-C), and observe that the signal frame will be misaligned:
+```
+signal occurred, info: 0x400080025c, context: 0x40008002dc
+```"""
+additional = """This issue is alluded to in the source code, see https://gitlab.com/qemu-project/qemu/-/blob/master/linux-user/riscv/signal.c#L68-69. It should be sufficient to change that constant to 15."""