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diff --git a/gitlab/issues/target_riscv/host_missing/accel_missing/2787.toml b/gitlab/issues/target_riscv/host_missing/accel_missing/2787.toml
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@@ -0,0 +1,25 @@
+id = 2787
+title = "Opentitan timer layout incorrect"
+state = "opened"
+created_at = "2025-01-21T14:49:55.743Z"
+closed_at = "n/a"
+labels = ["target: riscv"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/2787"
+host-os = "Ubuntu 22.04.3"
+host-arch = "x86"
+qemu-version = "9.1.1"
+guest-os = "Bare Metal"
+guest-arch = "riscv32"
+description = """It looks as if some of the timer register offsets here are incorrect:
+
+https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L37
+
+Compare with:
+
+https://opentitan.org/book/hw/ip/rv_timer/doc/registers.html
+
+I suspect they're out of date. The documentation link on line 7 is not working anymore - the current documentation URL for Opentitan is the one just given.
+
+It might also make sense to rename this file `opentitan_timer.c`, instead of  `ibex_timer.c`. The timer is an Opentitan hardware IP block, rather than a feature of the Ibex CPU."""
+reproduce = "n/a"
+additional = "n/a"