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diff --git a/gitlab/issues/target_riscv/host_missing/accel_missing/2796.toml b/gitlab/issues/target_riscv/host_missing/accel_missing/2796.toml
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+id = 2796
+title = "Opentitan Timer ignores COMPARE_UPPER0/COMPARE_LOWER0"
+state = "opened"
+created_at = "2025-01-27T22:06:46.621Z"
+closed_at = "n/a"
+labels = ["target: riscv"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/2796"
+host-os = "Ubuntu 22.04.3"
+host-arch = "x86"
+qemu-version = "9.1.1"
+guest-os = "Bare Metal"
+guest-arch = "riscv32"
+description = """In a bare metal application, running on an emulated Opentitan board, if you set a timer interrupt threshold by writing to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before writing to `rv_timer.CTRL` to start the timer, then the interrupt does not fire. If you write to the `COMPARE_*` registers *after* starting the timer by writing to `CTRL`, then the interrupt fires correctly.
+
+I think the explanation is that [ibex_timer_update_irqs](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L61) has an early return if `rv_timer.CTRL` is not set. As a result, although writes to `COMPARE_*` always call `ibex_timer_update_irqs`, they don't have their intended side-effects before `CTRL` is unset."""
+reproduce = """Write to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before you have set `rv_timer.CTRL`. Observe that no timer interrupt occurs."""
+additional = "n/a"