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-rw-r--r--gitlab/issues_text/target_missing/host_missing/accel_missing/255025
1 files changed, 0 insertions, 25 deletions
diff --git a/gitlab/issues_text/target_missing/host_missing/accel_missing/2550 b/gitlab/issues_text/target_missing/host_missing/accel_missing/2550
deleted file mode 100644
index e0925fdc2..000000000
--- a/gitlab/issues_text/target_missing/host_missing/accel_missing/2550
+++ /dev/null
@@ -1,25 +0,0 @@
-GICv3 vGIC system registers not initialized on ARM Cortex-A15
-Description of problem:
-For Cortex-A15, the GICv3 vGIC registers are not initialized like for AArch64 CPUs, for example Cotex-A35, Cortex-A55, etc
-Steps to reproduce:
-The setup is not trivial. I can provide a boot image on request. But I hope the problem is straight-forward.
-Additional information:
-Suggested fix:
-```diff
-index 20c2737f17..136b513bda 100644
---- a/target/arm/tcg/cpu32.c
-+++ b/target/arm/tcg/cpu32.c
-@@ -569,6 +569,12 @@ static void cortex_a15_initfn(Object *obj)
-     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
-     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
-     cpu->isar.reset_pmcr_el0 = 0x410F3000;
-+
-+    /* From B3.5 VGIC Type register */
-+    cpu->gic_num_lrs = 4;
-+    cpu->gic_vpribits = 5;
-+    cpu->gic_vprebits = 5;
-+
-     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
- }
-
-```