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-qemu-system-ppc: extra IPI interrupt on core0
-Description of problem:
-When I try to emit an IPI interrupt from core0 to another core via the MPIC controller(IPIDR1—Interprocessor interrupt dispatch register 1), core0 itself generates an unwanted IPI interrupt.
-Steps to reproduce:
-1. Prepare ISR routine, something like:
-
-    void ipi_handler (void)
-    {
-	int core_id = CORE_ID_GET(); 
-        myprintf("\n IPI interrupt triggered on core:%d\n",core_id);
-    }
-2. Create a task and bind it to core0. This task is mainly to write the MPIC controller to emit IPI interrupts to other cores.
-    MPIC_REG_WRITE(MPIC_BASE + IPIDR1, **0xe**);
-
-3. run the test task
-Additional information:
-/* Below test was tested on Qemu6.1 */
-
-IPI interrupts are emitted by core:0
-
-**IPI interrupt triggered on core:0** /* it's a bug, it should not trigger on core 0. */
-
-IPI interrupt triggered on core:1
-
-IPI interrupt triggered on core:2
-
-IPI interrupt triggered on core:3
-
-
-This bug only occurs when "emitting an IPIDR1 interrupt from **core0**".
-
-------------
-
-
-/* Below test was tested on real board(fsl_p4080ds) */
-
-IPI interrupts are emitted by core:0
-
-IPI interrupt triggered on core:1
-
-IPI interrupt triggered on core:2
-
-IPI interrupt triggered on core:3