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Diffstat (limited to 'gitlab/issues_text/target_riscv/host_missing/accel_TCG/1060')
| -rw-r--r-- | gitlab/issues_text/target_riscv/host_missing/accel_TCG/1060 | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_TCG/1060 b/gitlab/issues_text/target_riscv/host_missing/accel_TCG/1060 deleted file mode 100644 index 8e3de1692..000000000 --- a/gitlab/issues_text/target_riscv/host_missing/accel_TCG/1060 +++ /dev/null @@ -1,33 +0,0 @@ -RISC-V: mtval/stval is not correctly set to the instruction itself on illegal instructions -Description of problem: -QEMU 7.0 claims to support `stval`/`mtval` for illegal instructions, but `mtval`/`stval` is actually set to `0` -Steps to reproduce: -1. Assemble and link `mtval-illegal.elf`. The code simply sets up a trap handler and generates an illegal instruction exception - -2. Start QEMU with: - - ``` - qemu-system-riscv64 -cpu rv64,h=off -bios mtval-illegal.elf -nographic -icount shift=0 -s -S - ``` - -3. Attach with GDB: - - ``` - gdb mtval-illegal.elf - - # Within GDB - target extended-remote :1234 - break trap - disp $mtval - - # Keep single stepping until breakpoint - stepi - ``` - -4. When control flow reaches `trap`, `mtval` is written with `0` instead of the encoding of `csrw time, x0` (`0xc0101073`) -Additional information: -Writing `0` to `mtval` on a illegal instruction trap is allowed by the specs, but since the [changelog of QEMU 7.0][changelog] says it should be supported, I would consider it a bug. - -[changelog]: https://wiki.qemu.org/ChangeLog/7.0#RISC-V - -I encountered this when trying to figure out why my program worked with QEMU 6 but breaks with QEMU 7. It's more complicated, but in that case I managed to get `mtval` written with neither `0` nor the actual illegal instruction, but a different illegal instruction. I will try gathering up all the dependencies and write down the steps to reproduce if needed and if I find the time. |