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-rw-r--r--gitlab/issues_text/target_riscv/host_missing/accel_TCG/122410
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diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_TCG/1224 b/gitlab/issues_text/target_riscv/host_missing/accel_TCG/1224
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index 960dc2e9c..000000000
--- a/gitlab/issues_text/target_riscv/host_missing/accel_TCG/1224
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@@ -1,10 +0,0 @@
-QEMU crashes with failed assertion when executing compressed instructions with C extension support disabled
-Description of problem:
-When executing compressed instructions with compressed instruction support disabled (c=off), the tcg riscv translations fails an assertion.
-```
-qemu-system-riscv64: qemu/accel/tcg/translate-all.c:1449: tb_gen_code: Assertion `tb->size != 0' failed.
-```
-
-I believe that the issue is caused due to the fact that the compressed instruction without RVC support branch of the `decode_opc` function does not update `ctx->pc_succ_insn`, which causes `ctx->base.pc_next` to not be updated in `riscv_tr_translate_insn`, which then finally triggers the assertion once the tcg generation returns to `tb_gen_code`.
-
-Side note, it also seems like the `gen_exception_illegal` call in the same if case is not needed, since we also call it again at the end of the function.