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diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_missing/2787 b/gitlab/issues_text/target_riscv/host_missing/accel_missing/2787
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--- a/gitlab/issues_text/target_riscv/host_missing/accel_missing/2787
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-Opentitan timer layout incorrect
-Description of problem:
-It looks as if some of the timer register offsets here are incorrect:
-
-https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L37
-
-Compare with:
-
-https://opentitan.org/book/hw/ip/rv_timer/doc/registers.html
-
-I suspect they're out of date. The documentation link on line 7 is not working anymore - the current documentation URL for Opentitan is the one just given.
-
-It might also make sense to rename this file `opentitan_timer.c`, instead of  `ibex_timer.c`. The timer is an Opentitan hardware IP block, rather than a feature of the Ibex CPU.