diff options
Diffstat (limited to 'gitlab/issues_text/target_riscv/host_missing/accel_missing/2796')
| -rw-r--r-- | gitlab/issues_text/target_riscv/host_missing/accel_missing/2796 | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_missing/2796 b/gitlab/issues_text/target_riscv/host_missing/accel_missing/2796 deleted file mode 100644 index 07f66a8c1..000000000 --- a/gitlab/issues_text/target_riscv/host_missing/accel_missing/2796 +++ /dev/null @@ -1,7 +0,0 @@ -Opentitan Timer ignores COMPARE_UPPER0/COMPARE_LOWER0 -Description of problem: -In a bare metal application, running on an emulated Opentitan board, if you set a timer interrupt threshold by writing to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before writing to `rv_timer.CTRL` to start the timer, then the interrupt does not fire. If you write to the `COMPARE_*` registers *after* starting the timer by writing to `CTRL`, then the interrupt fires correctly. - -I think the explanation is that [ibex_timer_update_irqs](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L61) has an early return if `rv_timer.CTRL` is not set. As a result, although writes to `COMPARE_*` always call `ibex_timer_update_irqs`, they don't have their intended side-effects before `CTRL` is unset. -Steps to reproduce: -Write to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before you have set `rv_timer.CTRL`. Observe that no timer interrupt occurs. |