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@@ -0,0 +1,30 @@
+device: 0.761
+other: 0.671
+graphic: 0.636
+vnc: 0.574
+performance: 0.532
+socket: 0.479
+network: 0.468
+semantic: 0.402
+boot: 0.344
+permissions: 0.304
+files: 0.292
+debug: 0.229
+PID: 0.130
+KVM: 0.094
+
+ARMv7-M software-triggered interrupts-- unexpected behaviour
+
+The handling of the NVIC "Software Triggered Interrupt Register" in qemu-2.1.0/hw/intc/armv7m_nvic.c:375 isn't quite right.  As things stand, writing a zero to the STIR ends up transferring control to vector table entry zero, which, on ARMv7-M, holds the reset value of the stack pointer.  That's what I see with lm3s811evb emulation, and that's not what happens on my STM NUCLEO-F103RB board (Cortex-M3).
+
+Seems like an oversight-- the handler probably wants armv7m_nvic_set_pending(), not gic_set_pending_private(), and the IRQ number needs 16 added onto it to get the exception number for the interrupt.
+
+ARM DUI 0552A (Cortex-M3 Devices: Generic User's Guide), p. 134:
+  "Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3."
+
+Cheers,
+Boris
+
+This bug was fixed in QEMU 2.9 as part of the rewrite of M profile exception handling.
+
+